WO2004100131A2

WO2004100131A2 - Digital device configuration and method

Info

Publication number: WO2004100131A2
Application number: PCT/US2004/012554
Authority: WO
Inventors: Curtis H. Bruner; Lance R. Carlson; Jeffrey E. Mast
Original assignee: Cornice, Inc.
Priority date: 2003-04-28
Filing date: 2004-04-23
Publication date: 2004-11-18
Also published as: US7546411B2; US20040034724A1; US6973535B2; US20050154824A1; US20050166015A1; TW200516475A; US7149891B2; US7165139B2; US20050160195A1; WO2004100131A3

Abstract

An electromechanical data storage arrangement is interfaced with a host. The interface may include a conductor that carries read and write gate signals. Another conductor carries both a servo sync mark and an error signal. The storage arrangement includes an external serial interface connected to a host serial interface applying a device identification to a portion of serial control-related data that travels over the interface. A serial router in the storage arrangement uses the device identification to manage the control-related data between the interface and a number of serial devices and associated interfaces within the storage arrangement. The serial router is in selective data communication with each of the device serial interfaces, for using the device identification to direct a host-asserted command to a targeted device where each device is controlled by a different command set such that the system can be customized for different command sets of different devices.

Description

DIGITAL DEVICE CONFIGURATION AND METHOD

RELATED APPLICATIONS

l The present application is a Continuatioή-in-Part of co-pending U.S. Patent Application Serial No. 10/313,550, filed on December 6, 2002, which is itself a Continuation-in-Part of co-pending U.S. Patent Application Serial No. 09/952,998 filed on September 14, 2001, both of which are incorporated herein by reference in their entirety. The present application further claims priority from U.S. Provisional Application Serial No. 60/466,221, filed on April 28, 2003, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

2 The present application is related generally to a digital device architecture and, more particularly, to a digital system configuration and associated method for devices including an electromechanical data Storage Element. The invention is particularly well suited for use in a portable device.

3 One need only briefly survey virtually any public area in modern society in order to gain an appreciation for (he popularity of electronic devices. Such devices include, but are not limited to cellular phones, music players, portable computers, personal digital assistants, pagers, digital cameras, digital camcorders, personal gaming devices and e-books. Continuous improvement has been seen in the capabilities present in these devices attributable, at least in part, to a movement into digital implementations.

4 Demands, with regard to future electronic devices, include further miniaturization coupled with still further i improvements in performance. These demands are markedly intense with regard to portable devices. A particular area of concern resides in a desire to store ever-increasing amounts of digital information. At the same time, it should be appreciated that an electronic device, especially in a portable or miniaturized form, is likely to be subjected to a somewhat harsh environment, particularly with regard to mechanical ξhock. In an attempt to cope with the need for a significant amount of digital data storage while, at the same time, dealing with the problem of mechanical shock, designers resorted to the use of electronic memory, particularly in the form of flash memory. This solution is evident in the instance of state-of-the-art music players, including MP3 players. As of this writing, the popular configuration of these players is to use a removable flash memory card having a size of approximately 32 MB. Unfortunately, several problems are associated with this solution, as will be described.

5 One problem seen with regard to the flash memory solution resides in the fact that 32 MB is, in itself, a somewhat limited amount of storage. It is not unforeseeable that in the near future even amounts less than 512 MB will be considered as small. Considering present day devices, the owner of a portable device that relies on the use of flash memory cards typically must own a number of the cards in order to provide a sufficient overall amount of storage. Otherwise, the portable device owner may be forced to frequently reload the flash memory card via a personal computer or otherwise be subjected, for example, to listening to a quite limited music selection in the instance of an MP3 player. Moreover, the cost of flash memory cards is currently somewhat prohibitive. Many portable device owners simply choose not to incur the expense of buying numbers of additional flash memory cards. 6 In coping with the problems inherent in the- use of flash memory cards, a recent alternative solution has been the provision of a larger, electromechanical digital storage arrangement that is nonetheless removable. This solution is exemplified by the IBM Microdrive™. The latter is a removable miniaturized computer hard disk drive provided with a connector that mates with a corresponding connector incorporated within the portable device to be served. It is noted that such miniature hard drives, including the Microdrive, have essentially the same configuration as prior art hard drives seen in personal computers. That is, the miniature hard drive is made up of two general assemblies including a head disk assembly (HDA) and a printed circuit board assembly (PCBA). The HDA itself includes a rotatable magnetic media, a sensor assembly for reading from and writing to the rotatable media and motors for accomplishing rotation of the rotatable media and positioning of the sensor assembly. The PCBA includes essentially all of the electronics needed to operate the HDA with the common exception of a preamplifier. While the Microdrive brings improvement in data capacity, as of this writing, the cost of the Microdrive is quite high in terms of megabytes per dollar and absolute cost when compared to such costs in conventional drives. It is submitted that this absolute cost, in and by itself, will prove to be a significant barrier with regard to broad-based use of the product.

7 The Microdrive utilizes a CompactFlash interface. This interface raises concerns for a number of reasons, not the least of which is the requirement for a rather bulky interface connector having fifty pins, as described in the CF+ and CompactFlash Specification Revision 1.4. Further concerns with regard to CompactFlash will be addressed below.

5f8 With regard to the removable configuration of the Microdrive, it is noted that the perceived need for removable media has been greatly reduced in certain environments once viable, significant levels of "permanently" installed storage space has been provided. Available embedded storage has traditionally taken a precedent over removable storage, as evidenced in desktop computers. Still further concerns are associated with removable storage, as will be discussed below.

9 While the use of a miniaturized hard disk drive effectively resolves the problem of limited storage by providing many times the storage currently available in a typical flash memory card, the issue of the use of such a component in the potentially harsh environment of a portable device is once again brought to the forefront. It should be appreciated that, under certain circumstances, prior art hard disk drives tolerate relatively high levels of mechanical shock- even as high as 1500Gs. Under operational circumstances, unfortunately, hard disk drives are generally quite susceptible to mechanical shock events, for example, during the time that the head or sensing assembly is actually accessing the rotating media. Consequences of a mechanical shock event occurring at precisely the most inopportune time include potential drive failure. For instance, a drive may fail when subjected to a 175G event during an access. In this regard, Applicants are unaware of a miniaturized hard drive or overall device architecture incorporating effective features specifically intended to cope, for example, with the potentially harsh environment of a portable electronic device.

10 U.S. Patent number 6,061,751 (hereinafter the '751 patent), sharing the lead inventor of the present application, serves as one reference point with regard to several suggestions which may be utilized within a system incorporating a hard drive. The framework of the 751 patent, however, resides not in the area of drive miniaturization, ruggedization or portability, but primarily in reducing the cost of a hard disk drive as provided in an overall computer system. One approach taken by the patent encompasses moving all possible functionality out of the overall hard disk drive, including the controller, and onto the motherboard of the host device. For example, unused silicon "real estate" might be utilized for implementation of the controller. Moreover, such a controller may utilize memory fhat is already present on the host side. Thus, the drive cost is reduced to some extent. At the same time, it should be appreciated that the prior art functional control implemented as between the CPU and the controller is unchanged with respect to locating the controller on the motherboard. Specifically, the controller includes processing power which executes control code that is "native" to the peripheral device. As used herein, "native code" refers to the lowest level control code required to control a particular peripheral device. It is that code which is customarily executed by a device controller in a fashion that is isolated from the CPU resident within the host system.

Ifll Figure 1 is a representation of Figure 2 of the 751 patent, including alternative reference numbers assigned consistent with the present discussion. Accordingly, a prior art computer system 10 includes a host circuit board 12. A controller 14 is included as a single integrated circuit having further functions, as will be mentioned. A servo integrated circuit 16 is used to spin motors in any attached peripheral devices. Three peripheral devices are shown including a head disk assembly (HDA) 20, a CDROM DVD 22 and a floppy drive 24. Alternatively, the latter may comprise a high capacity floppy drive, a miniature drive, or other suitable device.

!fl One advantage, alluded to above, in the patent is the use of the HDA as an alternative to a complete hard disk drive (HDD) since costs are lessened by including components such as, for example, controller 14 within the host system. Components of the HDA (described above, but not illustrated) include a data media, a sensor/head mechanism to read and/or write data to and from the media, and motors to spin the media and position the sensor/head mechanism. A preamplifier is included to amplify the data read from or to be written to the media. The preamplifier may be installed on a flex circuit (see item 17 in Fig. 1A of the 751 patent) that electrically connects the HDA to the PCBA. It is appropriate to note, at this juncture, that the 751 patent also describes the location of a read/write channel, electrically in communication with the preamplifier, as potentially being arranged in the host system, distributed between the host system and the peripheral device or being within the peripheral device. The conventional location of the read/write channel in prior art HDD's is on the PCBA in close physical proximity to the electrical connection point of the HDA, for reasons described below.

^[13 Continuing with a description of Figure 1, each peripheral device may also have an associated personality ROM 26. The specific location of the personality ROM is shown for an individual component in Figure 3 (item 64) of the 751 patent. It is noted that the personality ROM is isolated from the rest of the individual component and is accessed via the PCI arrangement. It is important to understand that the personality ROM contains information which may define characteristics of controller firmware that is required to operate a particular component (see the table beginning in cols. 7 and 8 of the patent), however, the disclosure presents no way in which to update the firmware with code provided from the personality ROM. As an example, if the host system in the 751 patent is to operate four d fferent types of HDA, each of which requires completely different firmware, four sets of different firmware must be stored in the host device. As will be discussed below, the present invention considers this approach as unacceptable, at least for the reason that a great deal of storage space is required as a tradeoff for flexibility. Integrated circuit 14, in Figure 1, further includes peripheral component interconnect (PCI) bus functionality such that the integrated circuit is interfaced to a PCI bus 28. It is noted provided with ihe chipset connected to PCI bus 2&. CPU 30 is, in turn, interfaced with chipset 32. A RAM section 34 is also interfaced to chipset 32. It is important to note that CPU 30 is indirectly connected to the peripheral components. Specifically, PCI bus 28 is interposed between the peripheral components, including HDA 26, and the CPU. While this arrangement may be advantageous with regard to cost reduction, certain disadvantages that accompany this configuration will be considered at appropriate points below. For the moment, it is noted that system control is accomplished by the CPU issuing commands that are placed on PCI bus 28 in accordance with mandated PCI protocol. It is submitted that certain penalties are associated with this style of command configuration. For example, commands issued through levels or layers of protocol higher than the native code are particularly inflexible.

. l4 Attention is now directed to Figure 21, which illustrates a prior art computer system that is generally indicated by the reference numeral 50. System 50 includes a conventional HDD 52 that is connected to a host computer 54 by a parallel interface arrangement 56 such as, for example, an IDE or SCSI interface. Only selected electronic components of HDD 52 have been illustrated for purposes of clarity, however, it is to be understood that these electronic components are connected in a conventional manner with their typical electromechanical counterparts, as will be understood by one having ordinary skill in the art. The electronic components of HDD 52 include a servo IC 58, a read write IC 60 and a preamp IC 62. Further, a controller IC 64 is individually interfaced with each of the servo IC, read write IC and preamp IC. While the present figure illustrates one prior art configuration, there have been a number of modifications in the individual interfaces with ICs that are serviced by controller 64. As one example, functionality has been moved from the controller IC into servo IC 58 in a way which eliminates the Zero-Crossing and Commutate lines. As another example, servo IC 58 and Read Write IC 60 can share a serial clock line and a serial data line, however, each IC is provided with a unique enable line.

l5 Still referring to Figure 21, controller 64 is also externally connected with interface arrangement 56 for communication with host computer 54. Individual signals that are present within the interfaces between controller IC 64 have been labeled in the figure, but will not be described in detail since these signals will be familiar to one having ordinary skill in the art. For present purposes, it is important to understand, however, that each of the servo IC, the read/write IC and the preamp IC includes a dedicated serial interface indicated by the reference numbers 70, 72 and 74, respectively, that is connected to controller IC 64 for control purposes. Each serial IC interface includes a dedicated serial port enable line, a dedicated serial port clock line and a dedicated serial port data line. Accordingly, controller IC 64 must include individual serial interfaces that are adapted for each of the individual ICs which the controller services. Share serial port data and serial port clock but with unique enable signals

1fl In addition to each serial device requiring a dedicated serial interface and port, each serial device is configured to operate responsive to a particular, customized command set mat is often quite unlike the command sets that are associated with other serial devices that are present. Often, commands, as well as device responses thereto, are issued utilizing internal registers within each serial device. In order to access one of these internal registers, a command must include some sort of address field, identifying the internal register, and may include a data field. The response to the command may comprise a response data field. Unfortunately, there is no standardization from device to device with respect to the registers used, the command set, the address field length or data field length. In the general context of the prior art, this configuration has not been a concern since the controller is co-located with the serial devices. While the 751 patent moves the controller to the høst device, PCI mass storage IC 14 is provided to cope with disk data transfer issues, rather than serial control-related data issues. The patent appears to leave the serial control-related data issue in a still further complicated state, as is particularly evidenced with regard to the servo IC. Specifically, Figure 3 of the 751 patent shows the servo IC in the host device and merely extends the drive interface between the servo IC and the servo motor such that individual, "analog" drive signals for each coil of the motor are present in the interface. The present invention considers this approach as unacceptable at least for the reason that the number of signals present in the interface is unduly multiplied.

7 With continuing reference to Figure 21, traditional disk drives, as well as other forms of data storage devices, contain a control arrangement such as controller IC 64. This IC traditionally provides all of the control functions for the disk drive including, but not limited to:

Receiving, interpreting, and executing commands from the host system;

Operating and controlling the spindle motor system, using Servo IC 58 in the present example;

Operating and controlling the VCM/Actuator (again, using Servo IC 58);

Managing writes and reads of data to/from the disk by controlling other ICs such as Preamp IC 62 and

Read/Write IC 60; and

Detecting various error conditions, as well as executing recovery algorithms, if appropriate.

18 While the traditional controller IC includes many circuits to assist in these functions, much of the functionality is optimally implemented in firmware algorithms. This firmware is traditionally large and complex in order to provide all the required functionality.

^[1 The firmware is traditionally stored on a separate IC (not shown) from the Controller Processor IC within the drive. This IC is usually some type of programmable ROM device such as one-time-programmable ROM, Flash, EEPROM or other suitable device. Such programmable electronic devices as these are typically used because the firmware for a disk drive or any data storage device, for that matter, often must be revised and/or improved frequently as the product evolves. These changes are usually to improve manufacturing yields, operational reliability or to add new functionality, all of which improve the cost or competitive advantage of the product. The firmware change being described here is not so much a field upgrade, but a revision to the firmware incorporated in the product at the time of manufacture. ,

20 The frequency of firmware changes is typically highest during early product introduction and manufacturing (early in the product's life cycle). As a product continues to be manufactured over time, the firmware is often stabilized and, as a cost reduction, the programmable ROM parts mentioned above are changed to either one-time-only programmable parts or mask-programmed parts. The point being that, early in a product's life cycle, it is necessary to have a design which allows for rapid revision of the firmware placed onto the product during manufacture so that problems can be resolved, yields improved and the like.

21 The prior art has developed a number of approaches in coping with these concerns. For example, as time and experience accumulate on a family of products, the firmware becomes stable. When, at some point a new product is introduced, the firmware can include a "core" set of firmware that is based on stable firmware for the family of products from which the new product was derived. This stable core of firmware can be implemented in masked ROM which is incorporated into the controller IC. This core firmware is, ideally, functional, reliable and able to operate the product to a level which enables additional firmware (for full product functionality) to be read from the disk into RAM memory may also be co-located on in the controller IC. This additional firmware can be easily revised and written onto the disk at the time of manufacture. Accordingly, this prior art solution eliminates the need for a separate ROM device, thereby reducing cost and providing for revisions of the additional firmware which is located on the disk. It is important to recognize, however, that a very stable/reliable "core" firmware must be available. Thus, this prior art approach is not well suited for a completely new product technology introduction.

«f22 In view of the foregoing, it would be desirable to provide a new approach allowing for flexible firmware development, particularly in new, early generation product lines.

.3 The present invention provides a highly advantageous digital device configuration and method that are submitted to resolve the foregoing problems and concerns while providing still further advantages, as described hereinafter.

SUMMARY OF THE INVENTION

,4 As will be described in more detail hereinafter, there is disclosed herein a Storage Element as well as associated devices and method. In one aspect of the invention, a device is configured for access by a user and includes an assembly having an electromechanical digital data storage arrangement configured for operation responsive to a native control code. The device further includes a processing arrangement which executes a control program for controlling the overall device and which executes at least a portion of the native control code, as part of the control program, for use in directly interfacing with the storage arrangement.

,5 In another aspect of the present invention, an assembly includes a digital data storage arrangement made up of a rotatable read/write media, a head arrangement configured for reading and writing the rotatable media and a programmable channel at least for forming an interface between the rotatable media and the head arrangement. Additionally, a programming arrangement, produced separate from the digital storage arrangement, is electrically cormectable with the digital storage arrangement at least sufficient to program the channel in a particular way that serves to customize the interface formed by the channel between the rotatable media and the head arrangement such that the digital storage arrangement is later to be used, without the programming arrangement, in an end installation including the customized channel.

26 In yet another aspect of the present invention, a system is described for providing a digital storage arrangement for end use in an end device. The system includes a rotatable read/write media forming a first part of the digital storage arrangement and a head arrangement forming a second part of the digital storage arrangement and configured for reading and writing the rotatable media. A programmable channel forms a third part of the digital storage arrangement and is configured at least for forming an interface between the rotatable media and .the head arrangement. A programming arrangement, produced separate from the digital storage arrangement, is configured for electrical connection with the digital storage arrangement at least sufficient to program the channel in a particular way that serves to customize the interface formed by the channel between' the rotatable media and the head arrangement such that the digital storage arrangement is later used in the end device including the customized channel.

27 In still another aspect of the present invention, in a device having a user access arrangement for receiving a user interaction and including a processing arrangement, the improvement includes a command execution arrangement for interpreting the user interaction in a way that defines a command to be executed by the processing arrangement and for initiating the execution of the command prior to termination of the user interaction. In one feature, a digital data storage arrangement is further included for storing digital information under control of the processing arrangement wherein the command defines a data access that uses the digital storage arrangement and the processing arrangement is programmed to initiate execution of the data access responsive to partial entry of the command during the user interaction. In another feature, the digital storage arrangement utilizes a rotatable media and an electronic memory arrangement is provided wherein the processing arrangement is programmed to execute the data access by reading certain information from the digital storage arrangement, after spinning up the rotatable media on which the certain information is stored, and for transferring that certain information to an electronic memory arrangement such that the certain information is available without the need to access the digital data storage arrangement.

28 In a further aspect of the present invention, within a device including an electromechanical digital storage arrangement and configured for receiving a plurality of external interactions, at least some of which require one or more data transfers using the storage arrangement, and at least some, but not all of which are user interactions, an assembly includes: a first arrangement for receiving a first one of the interactions requiring a first data transfer by the storage arrangement, a second arrangement for determining that the first interaction is a non-user interaction, and a third arrangement for delaying execution of the first data transfer, associated with the first non-user interaction, at least until a next user interaction.

^[29 In a continuing aspect of the present invention, within a device including an electronic memory arrangement having a capacity wherein the device is configured for responding to a plurality of external interactions including user interactions, at least a specific one of which interactions requires a specific data transfer to the electronic memory arrangement such that the specific data transfer is of a size that exceeds the capacity of the electronic memory arrangement, an assembly includes a first arrangement for loading the electronic memory arrangement with an initial portion of the specific data transfer to fill the electronic memory arrangement to its capacity such that the initial portion of data is available for use in a predetermined way. A second arrangement monitors the use, in the predetermined way, of any data stored in the electronic memory arrangement and a third arrangement is provided for loading an additional portion of the specific data transfer into the electronic memory arrangement to replace that part of the initial portion of the specific data transfer which has been used in the predetermined way such that an unused part of the initial portion of the specific data transfer and the additional portion of the specific data transfer are concurrently stored in the electronic memory aπangement. In one feature, the assembly includes an electromechanical digital storage arrangement such that the specific data transfer is stored by the electromechanical digital storage arrangement for transfer to the electronic storage arrangement in the first and additional portions.

If30 In an ongoing aspect of the present invention, within a portable electronic device configured for receiving a user interaction and for operating in an overall environment which may subject the portable electronic device to mechanical shock, the device including an electromechanical Storage Element which is susceptible to such mechanical shock when reading and or writing data and which is otherwise substantially less susceptible to mechanical shock, the electromechanical Storage Element is protected from shock at least to a limited extent by providing an electronic memory arrangement in the portable device. The user interaction is monitored to define a particular use of a selection of data stored on the electromechanical Storage Element. The selection of data is copied from the electromechanical Storage Element to the electronic memory arrangement. After using the electromechanical Storage Element in the copying step, availability of the selection of data for the particular use is indicated such that the user is able to initiate the particular use of the selection of data, through accessing the electronic memory arrangement, only after the electromechanical Storage Element is not in use and is substantially less susceptible to mechanical shock.

^[31 In another aspect of the present invention, in a device configured for access by a user and including a processing arrangement which executes a control program for controlling the overall device, an assembly includes an electromechanical digital data storage arrangement responsive to a native control code and a peripheral control arrangement configured such that the processing arrangement executes at least a portion of the native control code of the storage arrangement as part of the control program. The peripheral control arrangement includes an interface configured for implementing the native code between the processing arrangement and the electromechanical digital storage arrangement.

.* 2 In still another aspect of the present invention, a digital data storage arrangement includes a rotatable media as well as a head arrangement configured for accessing the rotatable media by first initiating a control sequence intended to move the head arrangement from an imparked position to a parked position. Thereafter, a predetermined status is detected, related to head arrangement position which confirms that the head arrangement is in the parked position. An indication is then produced based on the predetermined status. In one feature, the indication is stored at a predetermined register location. In another feature, the storage arrangement is configured with a ramp for receiving the head aπangement in its parked position such that, when so received, the ramp and the head aπangement cooperate in a way which produces the indication thereby confirming that the head is in the parked position.

33 In another aspect of the present invention, in a digital data storage aπangement including a rotatable media as well as a head aπangement configured for accessing the rotatable media and for moving to a parked position, an apparatus includes a first aπangement for initiating a control sequence intended to move the head aπangement to the parked position after having accessed the rotatable media, a second aπangement for thereafter detecting a predetermined status related to head aπangement position by testing the head aπangement for reading from the rotatable media such at an inability of the head aπangement to read indicates that the head aπangement is at least away from the rotatable media, and a third aπangement for producing an indication based on the predetermined status.

34 In yet another aspect of the present invention, in a device including a processing aπangement for controlling operation of the device and including an electromechanical digital storage aπangement is described. A status of a particular attribute is established related to operation of the electromechanical digital storage aπangement. Using the processing aπangement, the status of the particular attribute is monitored for use in a further control operation. 35 In a continuing aspect of the present invention, in an electromechanical storage device including a rotatable magnetic media and a head aπangement configured for movement to access the rotatable media and for moving to a parked position, an assembly includes a first aπangement for producing a position signal which confirms that the head aπangement is in the parked position and an electrical interconnection aπangement in electrical communication with the head aπangement for use in controlling the head aπangement and which electrical interconnection aπangement is configured for receiving the position signal from the first aπangement for a control use.

36 In a further aspect of the present invention, in an electromechanical storage device including a housing supporting a spin motor for rotating a magnetic media disk and supporting an actuator aπangement for accessing the magnetic media disk using at least one head positioned on a distal end of the actuator arrangement, an assembly includes an electrical interconnection arrangement in electrical communication with said actuator aπangement and configured for forming an external interface to the storage device. The assembly is further configured such that at least a portion of the electrical interconnection aπangement is supported by the housing and includes a parking aπangement supported by the housing supported portion of the electrical interconnection aπangement for receiving the distal end of the actuator arm in a parked position.

1(3 In another aspect of the present invention, as applied to an electromechanical storage device including a rotatable magnetic media and a head aπangement configured for movement to access the rotatable media and for moving to a parked position responsive to at least one parameter in a parking sequence, an aπangement is provided as part of the electromechanical storage device, for producing a position signal which confirms the parked position of the head aπangement when so positioned. A calibration procedure is performed using the position signal to establish an operational value of the parameter for later use in parking the head aπangement.

1[38 In still another aspect of the present invention, as applied to a plurality of electromechanical storage devices each of which includes a rotatable magnetic media and a head aπangement configured for movement to access the rotatable media and for moving to a parked position responsive to a parking sequence, an aπangement is provided, as part of each electromechanical storage device, for producing a position signal which confirms the parked position of the head aπangement when so positioned. A calibration procedure is performed on each electromechanical storage device, in which the parking sequence is applied to each electromechanical storage device with the head aπangement initially in a data access position intended to move the head aπangement to the parked position. The parking sequence being repeatedly performed in a way which establishes a failure configuration of the parking sequence for each electromechanical storage device in which failure configuration the head aπangement at least once fails to achieve the parked position. A set of failure configurations, including at least one failure configuration for each electromechanical storage device, is tracked across the plurality of electromechanical storage devices.

39 Further in accordance with the present invention, a digital data storage apparatus and associated method are described wherein a housing defines a housing interior. A rotatable magnetic media is supported for rotation within the housing interior. A head aπangement is supported within the housing interior, including an actuator arm configured for pivotally accessing the rotatable media and for pivotally moving to a parked position from an access position. A flexible circuit aπangement is configured to include a flexible circuit stifiener having a major surface defining a stiffener plane and which is directly attached to the housing within- the housing interior. A ranφ aπangement is directly attachable to the flexible circuit stiffener and is configured for receiving the actuator arm in the parked position when so attached. The ramp aπangement further includes an indexing aπangement for engaging the housing in a way which positions the ramp aπangement with at least one controlled tolerance relative to the head aπangement. In one feature, the indexing aπangement and the flexible circuit stiffener are cooperatively configured such that attachment of the ramp aπangement to the flexible circuit stiffener captures at least a selected part of the indexing aπangement between the housing and the flexible circuit stiffener so as to resiliently bias the indexing aπangement against the housing. In a related feature, the housing defines a ramp indexing recess and the indexing aπangement of the ramp aπangement includes a ramp indexing pin which is resiliently biased into the ramp indexing recess to locate the ramp indexing pin with a first controlled tolerance.

40 In one aspect of the present invention, within a digital system, an assembly includes an electromechanical digital data storage aπangement including a rotatable disk and the assembly is at least responsive to a read gate signal for initiating a read therefrom and responsive to a write gate signal for initiating a write thereto. A host device, within the system, is configured for controlling the data storage aπangement and for generating the read gate signal and the write gate signal in a mutually exclusive way. An interface electrically interconnects the data storage aπangement and the host device using a plurality of electrical conductors such that a selected one of the conductors carries both the read gate signal and the write gate signal.

^[41 In another aspect of the present invention, within a system, an assembly includes an electromechanical digital data storage aπangement including a rotatable disk having servo information and user data storable thereon and is configured for generating a servo synchronization signal responsive to the servo information and for generating an eπor signal responsive to detection of an eπor relating at least to the user data. A host device, as part of the system, is configured for controlling the data storage aπangement, at least in part, by using the servo synchronization signal and the eπor signal. An interface electrically interconnects the data storage aπangement and the host device using a plurality of electrical conductors such that a selected one of the conductors caπies both the servo synchronization signal and the eπor signal in a mutually exclusive manner.

f 42 In still another aspect of the present invention, a system includes an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from the disk under the control of a servo electronics device having a servo serial interface, in cooperation with a read/write electronics device having a read write serial interface for control thereof, and a preamp electronics device having a preamp serial interface for control thereof, such that digital data can be written to or read from the disk responsive to a host device, the storage aπangement thereby including a plurality of device serial interfaces. An interface aπangement includes an external serial interface, forming part of the storage aπangement, for use in externally electrically connecting the storage aπangement and for bi-directionally externally transferring a serial control-related data, for use in operating each of the servo device, the read write device and the preamp device. A host serial interface, forms part of the host device, in data communication with the external serial interface of the storage aπangement, configured for applying a device identification on the external serial interface in a way which directly associates at least a portion of the serial control-related data with each of the device serial interfaces. A serial router, forms part of the storage aπangement, in data communication with each of the device serial interfaces, for using the device identification to manage the serial control-related data bi-directionally between the device serial interfaces and the external serial interface.

^[ 3 In yet another aspect of the present invention, as part of an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from the disk under the control of a servo electronics device having a servo serial interface, in cooperation with a read/write electronics device having a read/write serial interface for control thereof, and a preamp electronics device having a preamp serial interface for control thereof, such that digital data can be written to or read from the disk, and the storage aπangement thereby including a plurality of device serial interfaces, an external interface aπangement includes a primary serial gateway for implementing external bi-directional transfer of a serial control-related data that is used in operating each of the servo device, the read/write device and the preamp device, consistent with a serial protocol. A serial router is placed in data coinmunication with the primary serial gateway for using the serial protocol to manage the serial control-related data bi-directionally between the primary serial gateway and each of the device serial interfaces.

44 In a continuing aspect of the present invention, in a system including an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from the disk under the control of a servo electronics device having a servo serial interface, in cooperation with a read/write electronics device having a read write serial interface for control thereof, and a preamp electronics device having a preamp serial interface for control thereof, such that digital data can be written to or read from the disk responsive to a host device, and said storage aπangement thereby including a plurality of device serial interfaces, an interface aπangement including a primary serial gateway, forming part of the storage aπangement for externally bi-directionally transferring a serial control-related data, which is used in operating each of the servo device, the read/write device and the preamp device. A host serial interface, forming part of the host device and in data communication with the primary serial gateway of the storage aπangement, is configured for applying a serial protocol to the serial control-related data passing between the host device and the storage aπangement. A serial router, forming part of the storage aπangement and in data communication with the primary serial gateway, uses the serial protocol to manage the serial control-related data between the primary serial gateway and each of the device serial interfaces.

45 In a further aspect of the present invention, in a system including an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from the disk under the control of a servo device having a servo serial interface, in cooperation with a read/write device having a read write serial interface for control thereof, and a preamp device having a preamp serial interface for control thereof, such that digital data can be written to or read from the disk responsive to a host device, and the storage aπangement thereby including a plurality of device serial interfaces each of which is associated with a device such that each device is operated responsive to a read and write command set that is unique to that device, an interface aπangement includes a primary serial gateway, forming part of the storage aπangement, for electrically interconnecting the storage aπangement to the host device to implement external bi-directional transfer of a serial control-related data which is used in operating each of the servo device, the read write device and the preamp device. A host serial interface, forming part of the host device and in data communication with the primary serial gateway of the storage aπangement, is configured for use in selectively asserting each read and write command set to each of said devices on said primary serial gateway for use in managing each device and for identifying a command that is asserted by the host device to a targeted one of the devices using a device identification. A serial router, forming part of the storage aπangement, in selective data communication with each of the device serial interfaces, uses the device identification to direct the asserted command to the targeted device.

f46 In another aspect of the present invention, in an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for use in electromagnetically writing user data to the disk and for use in electromagnetically reading the user data from the disk under the control of an electronics aπangement through the use of control-related data, and which electronics aπangement is externally interfaced for transferring the user data, a data interface aπangement includes at least one data line that carries said user data during said read operations and said write operations. A configuration, forming part of the data interface aπangement, uses the data line during operation of the storage aπangement to cany at least a portion of said control related data at a time when the data line is not carrying the user data.

^[47 In still another aspect of the present invention, in an electromechanical digital data storage aπangement including a disk for storing user data thereon which user data is transfeπed through a data port, a configuration including a serial port for operating the storage aπangement using bi-directional control-related serial data that is clocked using a clock signal and means for using the clock signal as a time base reference for writing the user data to the disk.

f 48 In a continuing aspect of the present invention, in an overall system including a host device for operational support of an electromechanical storage aπangement, which is provided separate from the host device, and which stores digital data on a rotatable disk, and the host device is provided with a particular firmware configuration for controlling a particular version of the storage aπangement and the storage aπangement may be provided in a updated version which requires an updated firmware configuration in the host device, such that the particular firmware configuration, provided with the host device, is unable to control the updated version of the storage aπangement, the updated firmware configuration is provided as part of the updated version of the storage aπangement. The particular firmware configuration of the host device is configured to automatically query, iπespective of the version of the storage aπangement, any storage aπangement with which the host device is connected for the presence of the updated firmware configuration such that connecting the host device to an updated version of the storage aπangement, upon detection of the updated firmware configuration responsive to the query, causes the host device to operate the system using the updated firmware configuration.

f 49 In a system including a host device having a host processing aπangement for controlling the overall host device and for operational support of an electromechanical storage aπangement, which is initially provided separate from the host device, and which stores digital data on a rotatable disk, and a particular firmware configuration is used for controlling a particular version of the storage aπangement such that a first portion of the particular firmware configuration is required to allow the storage aπangement to access any digital data that is stored on the rotatable disk, and where the storage aπangement may be provided in an updated version which requires an updated firmware configuration that changes at least the first portion of the updated firmware configuration, compared to the first portion of the particular firmware configuration, in a way which would at least limit access to the digital data that is stored on the rotatable disk, a firmware control aπangement .is provided. The firmware control aπangement includes storage aπangement control means electrically interfaced with the host processing aπangement of the host device and with the updated version of the storage aπangement. The storage aπangement control means includes the particular firmware configuration for controlling the particular version of the storage aπangement. A firmware update is stored in the host device and coπesponds at least to a difference between the first portion of the particular firmware and the first portion of tiie updated firmware configuration in a way that is accessible to the host processing aπangement. Means is provided for transferring the firmware update to the storage aπangement control means, using the host processing aπangement, in a way that causes the storage aπangement control means to, thereafter, execute the first portion of the updated firmware configuration in controlling the storage aπangement. In one feature, the firmware control aπangement includes a second firmware update stored on the rotatable disk, approximately at a time of manufacture of the storage aπangement, coπesponding to an additional difference between a second portion of the particular firmware configuration, as compared to a second portion of the updated firmware configuration. The storage aπangement control means is configured for accessing the second firmware update, using the storage aπangement control means, after installing the first portion of the updated firmware configuration, to install the second portion of the updated firmware configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

1f50 The present invention may be understood by reference to the following detailed description taken in conjunction with the drawings briefly described below.

5[51 FIGURE 1 is a block diagram taken directly from U.S. Patent number 6,061,751 shown here to serve as one focal point for discussion relative to prior art design considerations regarding hard disk drives.

52 FIGURE 2 is a diagrammatic block diagram illustrating one embodiment of a device implemented including a Storage Element of the present invention.

53 FIGURE 3 is a diagrammatic plan view illustrating one possible physical embodiment of the Storage Element of the present invention.

1f54 FIGURES 4a-4c are diagrammatic timelines illustrating various approaches for performing data transfers in accordance with the present invention.

^[55 FIGURE 4d is a diagram illustrating the status of data stored in an electronic memory aπangement of the device of the present invention at a particular point in time.

56 FIGURE 5a is an illustration of one possible appearance of the device of Figure 2 produced in accordance with the present invention including a display screen and connectable, for example, with a headset, as shown.

57 FIGURES 5b-5g are diagrammatic illustrations of the appearance of the display screen of the device of Figure 5a, shown here to illustrate potential operational sequences occurring during interactions with a user of the device performed in accordance with the teachings of the present invention. 58 FIGURE 6 is a diagrammatic illustration; in perspective, of a portion of the Storage Element of the present invention, shown here for the purpose of describing several embodiments of a highly advantageous head aπangement position sensor.

59 FIGURE 7 is a schematic block diagram illustrating a position sensing circuit interfaced with the head aπangement position sensor of Figure 6.

0 FIGURE 8 is a partial cut-away diagrammatic view of the voice coil motor arm end of the Storage Element of the present invention, shown here to facilitate discussion of a highly advantageous mechanical shock sensing aπangement implemented in accordance with the present invention.

61 FIGURE 9 is a schematic block diagram illustrating a mechanical shock sensing circuit interfaced with the mechanical shock sensing aπangement of Figure 8.

>2 FIGURE 10 is a flow diagram illustrating one possible implementation of a parking calibration method performed in accordance with the present invention and utilizing the highly advantageous head position sensing aπangement of the present invention.

63 FIGURE 11 is a flow diagram illustrating one possible implementation of a parameter tracking method performing in accordance with the present invention and utilizing the head position sensing aπangement of the present invention.

64 FIGURE 12 is a flow diagram illustrating one possible implementation of an advanced parking control and monitoring sequence performed in accordance with the present invention and utilizing the head position sensing aπangement of the present invention.

f 5 FIGURE 13 is a block diagram of a testprogramming board produced in accordance with the present invention and interfaced with the Storage Element (partially shown) of the present invention during manufacturing procedures.

66 FIGURE 14 is a perspective view of the base plate and interior components of another embodiment of the Storage Element of the present invention, shown here to illustrate details of its structure.

67 FIGURE 15 is an exploded perspective view of selected components of the Storage Element of Figure 14 illustrating its base plate, flexible circuit stiffener and a ramp aπangement in a spaced apart positional relationship.

1J68 FIGURE 16 is another perspective view of selected components of the Storage Element of Figure 14 showing the flexible circuit assembly positioned in the base plate and the ramp aπangement in a spaced apart relationship thereto.

69 FIGURE 17 is a partial cutaway plan view of the Storage Element of Figure 14 shown here to illustrate details with regard to installation of the ramp aπangement.

ψO FIGURE 18 is a partial cutaway view, in perspective of the Storage Element of Figure 14 illustrating the installed ramp aπangement and its relationship to the landing point load tip on the actuator arm. T|7l FIGURE 19 is partial cutaway hottotn view, in perspective, of certain components of the Storage Element of Figure 14 including the flexible circuit aπangement and ramp aπangement shown here to illustrate details of their cooperating structures.

72 FIGURE 20 is a partial diagrammatic cross-sectional view, in elevation, taken in a plane which bisects the T- lock arms of the installed ramp aπangement of Figures 14 and 18, shown here to illustrate further details of the structures of the flexible circuit aπangement, base plate and installed ramp assembly as well as associated advantages.

f 73 FIGURE 21 is a block diagram of a prior art system showing a host computer interfaced with a conventional hard disk drive.

1J74 FIGURE 22 is block diagram illustrating the Storage Element of the present invention interfaced with a host device, shown here to illustrate details with regard to a highly advantageous interface between the Storage Element and host device, as well as cooperating features within the Storage Element and host device.

75 FIGURE 23a is a greatly enlarged plan view which diagrammatically illustrates the signals which are present in the Storage Element to host device interface, which signals may be present, for example, in a flexible cable that extends from the Storage Element.

f 76 FIGURE 23b is a block diagram partially showing the Storage Element and the host device for purposes of illustrating a highly advantageous differential-like clock that is implemented therebetween in accordance with the present invention.

1J77 FIGURE 24 is a partial block diagram of the Storage Element, shown here in order to illustrate details with respect to a highly advantageous composite RG WG signal that is implemented as part of the Storage Element to host device in accordance with the present invention.

^[78 FIGURE 25 is a is a partial block diagram of the Storage Element, shown here in order to illustrate details with respect to a highly advantageous composite SSM/ERR signal that is implemented as another part of the Storage Element to host device in accordance with the present invention.

79 FIGURE 26 is a flow diagram, shown here to illustrate details with respect to the highly advantageous serial protocol of the present invention.

1(80 FIGURE 27 is a partial block diagram of the Storage Element shown interfaced with a host device illustrating, one embodiment of an aπangement for sharing an NRZ line which forms a portion of the Storage Element to host device interface, specifically, an NRZ <0> line is used to share NRZ <0> data with zero crossing data.

1f8l FIGURE 28 is another partial block diagram of the Storage Element shown interfaced with a host device illustrating another embodiment of an aπangement for sharing another NRZ line which forms a portion of the Storage Element to host device interface, specifically, an NRZ <1> line is used to share NRZ <-l> data with spindle motor commutation data. i[82 FIGURE 29 is a partial functionally partitioned block diagram, illustrating the Storage Element interfaced with a host device for purposes of providing further details with respect to shared use of the NRZ lines, as implemented by the present invention.

83 FIGURE 30 is a flow diagram illustrating details of one embodiment of a process for sharing NRZ lines in which the NRZ <0> line and the NRZ <1> line are used to transfer zero crossing and commutation data, respectfully, during a start-up procedure.

84 FIGURE 31 is a diagrammatic illustration showing the Storage Element in relation to locations from which Patch data is provided having Pre-Patch data stored in a non-volatile electronic memory while Post-Patch data is stored on-disk in accordance with the highly advantageous firmware management system of the present invention.

85 FIGURE 32 is a diagrammatic illustration of the highly advantageous firmware structure of the present invention showing one method in which Patches are used in concert with original firmware that is provided with the host device.

^[86 FIGURE 33 is a flow diagram which illustrates one embodiment of a process for implementing the highly advantageous RAM Patch structure that is shown in Figure 32.

87 FIGURE 34 is a block diagram of one embodiment of the Transition IC of the present invention, shown here to illustrate details with respect to its structure.

88 FIGURE 35 is a schematic representation of one embodiment of the TIC interfaced with the Storage Element, shown here to illustrate various electrical interconnects and signals on the host side.

89 FIGURE 36A, 36B, and 36C, in combination, comprise an overall system schematic in which the Storage Element is interfaced to the TIC.

90 FIGURE 37 is a block diagram of one embodiment of the Servo/Control (Nova) IC of the present invention, shown here to illustrate details with respect to its highly advantageous structure.

ψl FIGURE 38 is a plan view of the pinout of the IC of Figure 37.

92 FIGURE 39 is a block diagram of one implementation of the overall system of the present invention.

93 FIGURE 40 is a timing diagram illustrating the highly advantageous serial protocol of the present invention

94 FIGURE 41 is a block diagram of one embodiment of an integrated Voice Coil Motor driver that is provided in the Servo/Control IC.

95 FIGURE 42 is a block diagram showing one embodiment of a spindle driver system in accordance with the present invention.

1f96 FIGURE 43 is a schematic diagram showing one implementation of gate drivers and ΠOWPΓ FKTV «-« Λ~ spindle driver system of Figure 42.

f 97 FIGURE 44 is a block diagram illustrating one implementation of the Nova commutation control logic.

98 FIGURE 45 is a schematic diagram showing one implementation of a highly advantageous Back EMF measurement circuit.

DETAILED DESCRIPTION OF THE INVENTION

!f9 Returning now to the drawings, wherein like components are indicated by like reference numbers throughout the various figures, attention is immediately directed to Figure 2, which illustrates an electronic device, generally indicated by the reference number 300, manufactured in accordance with the present invention. It is to be understood that device 300 is intended to be representative of any number of digitally implemented device types including, but not limited to wireless telephones, Internet appliances, personal digital assistants, music players, multi-function pagers, multimedia devices or any other device adaptable to use permanently installed digital storage of a size that is typically provided using electromechanical, rather than electronic storage. Moreover, the present invention facilitates the inclusion of additional functionality in devices traditionally having more limited, dedicated functionality. For example, a wireless phone maybe provided including such features as a digital camera and/or a digital music player. Specific teachings with regard to integration of such functionality in particular device types will be provided at appropriate points below. The present invention is particularly suited for use in devices which may, at times, be subjected to use in a "hostile" environment in which the device experiences large mechanical shock forces. Portable devices are commonly exposed to such an environment. The present invention, however, is in no way limited to use in portable devices, but finds application in essentially any form of device that is likely to be subjected, at least briefly, to mechanical shock.

00 Continuing with a description of Figure 2, device 300 includes a processing aπangement 302 configured for operating the overall device. Processing aπangement 302 includes at least one processor or central processing unit (CPU, not shown). Such a CPU may be designed to cooperate with a chipset (not shown) forming part of the processing aπangement. At the same time, additional, slave CPU's or chips (not shown) may operate at the behest of a master CPU, all of which are considered to form the processing aπangement. It should be appreciated that all of these configurations are considered as being within the scope of the present invention so long as certain teachings are practiced, as will be described.

101 A memory section 304 is associated with processing section 302 which may be, for example, a suitable form of ROM. Alternatively, the memory section can be made up of a suitable combination of ROM and RAM wherein a volatile RAM portion of the memory section is loaded for device operation during an initial boot-up. Memory section 304 itself includes device code 306 and native code 308. The latter will be described in detail below. Device code 306 enables functionality dedicated to operational and housekeeping tasks common to any particular type of device that is implemented. Moreover, it should be appreciated that the minimum amount of computational power that is commonly needed to operate a device, having somewhat limited dedicated functionality, is conespondingly quite limited with respect to the capabilities of the processors that are commonly employed in such state-of-the-art devices. As one example, processors in wireless telephones may typically be idle for a majority of the time. The present invention may rely on under-utilized capabilities of the .processing aπangement in a highly advantageous way, as will be described hereinafter.

l02 With continuing reference to Figure 2, device 300 further comprises a user interface aπangement 310, for example, in the form of a keypad (only partially illustrated). Other items include an electronic memory aπangement 312 and a Storage Element 320, all of which are connected to processing aπangement 302. Buses/interfaces 322 and 324 connect the processing aπangement to the Storage Element and electronic memory aπangement, respectively. Electronic memory aπangement 312 may comprise volatile memory such as RAM having a predetermined size for use in performing particular operations under control of processing aπangement 302. As one example, the electronic memory aπangement may be loaded, in a manner yet to be described, with digital music that is later read by the processing aπangement, processed and, thereafter, provided to an audio output jack 325 via a suitable audio section 326. It is noted that, while certain features are described herein with regard to processing and handling digital audio, these descriptions are intended for illustrative purposes only and that the underlying concepts of the present invention enjoy a broad range of applicability. A digital interface 328 is provided having an external connection such that device 300 may be connected to an external computer. Suitable interface configurations include, for example, a Universal Serial Bus (USB) interface and IEEE 1394. With appropriate software installed on the external computer, a user may perform maintenance operations with regard to the content available on Storage Element 320. For example, a user may create playlists which are loaded onto the Storage Element. It should be appreciated that any form of digital information may be transfeπed to or from the Storage Element in this manner.

f 103 Storage Element 320 comprises electromechanical storage interfaced to device 300 by a flexible circuit 330 to be described in further detail along with descriptions of other components which make up the Storage Element. For the moment, it is sufficient to note that a connector 332 is provided which accepts a free end of flexible circuit 330 for purposes of interfacing Storage Element 320 to processing aπangement 302 within device 300 via bus 322.

^[104 Native code 308, used by processing aπangement 302, is directed to the sole purpose of operating Storage Element 320. The term native code, as mentioned above, encompasses code that is used in the direct control of a device that is peripheral to the processing aπangement. Native code is typically executed by a prior art controller chip and represents the lowest and most direct level of control of the peripheral device. In accordance with the present invention, processing aπangement 302 controls Storage Element 320 using its native code with no intervening protocol layers; comprising instructions that are directly received and acted on by components (to be described) in the Storage Element. No translation of these native code instructions is performed. In essence, native code is the inherent, executable language of the Storage Element. Prior art controllers serve to receive higher level protocol commands and interpret these into native code. In view of the foregoing discussions, direct control of the Storage Element exemplifies an advantageous application of potentially unused, but available processing power of processing aπangement 302. In the event that otherwise unused capability is used, device 300 generally exhibits no user-perceptible performance degradation, as compared to the same device operating conventionally; that is, compared to a device in which a dedicated controller executes native code. Moreover, processing power dedicated to the operation of the Storage Element may deliberately be limited to unused capabilities of a host processor (CPU) already present in the architecture of a particular device. Further, a "transitional" configuration may be provided as an interim solution which includes a transitional IC assisting the host processor in the execution of the native code of the Storage Element. The transitional implementation is advantageous in requiring minimal hardware changes in a preexisting host processor. Cost associated with the modification in the host processor may be limited so as to be essentially insignificant. That is, the modified processor may be provided for any application previously employing the unmodified processor as well as for new applications including Storage Element control functionality.

^1 5 The transitional IC may be integrated in the chipset of the host IC using, for example, an interface made up of a clock line, one or more control lines and one or more data lines such as NRZ lines. The width of this interface may be limited to further reduce impact on the host processor in terms of pin count. The control line or lines, separate from the data line or lines, is considered to be advantageous in providing direct and immediate control over the Storage Element. In the instance of an interface requiring sharing of control, data and disk-related data (i.e., servo or "user" data stored by the Storage Element), control delays may be encountered as a result of waiting while disk-related data is being transfeπed. The present invention contemplates a need for immediate control, for example, when a sufficiently high probability of mechanical shock is predicted. Over time, functionality present in a transitional IC may migrate into the host processor. It should be appreciated that the host IC and the transitional IC may utilize vendor unique commands with regard to implementation of specialized features of the present invention within a prior art interface aπangement so long as such commands are compatible with the overall interface protocol that is used. Where the transitional IC is configured to respond to one or more vendor unique commands, the host side requires knowledge of the commands and appropriate programming on the host side to implement the vendor unique commands. For example, a Compact Flash Interface may be implemented between the transitional IC and the host IC utilizing one or more vendor unique commands. The foregoing feature will be discussed further at an appropriate point below.

106 Referring to Figure 3 in conjunction with Figure 2, a further advantage of the present invention resides in the "visibility" of the Storage Element to the processing aπangement. Since virtually every aspect of the operation of the Storage Element is controlled by processing aπangement 302 via native code 308, certainty as to the exact operational status of the Storage Element is achieved. In this regard, Storage Element 320 includes a housing 338. A rotatable magnetic media 340 is rotated by a spin motor 342 which is, in turn, supported by housing 338. A sensor aπangement 344 is positioned by a voice coil motor (VCM) 346 (only a portion of which is shown). The term sensor aπangement is interchangeable with the terms head aπangement and actuator arm. As is best seen in Figure 3, illustrated portions of the VCM include a lower magnet assembly 348 and a voice coil 350 which is supported on the VCM end of actuator arm 346. The upper magnet assembly is not illustrated for purposes of clarity. The actuator arm is supported by an actuator pivot 351 which is, in turn, supported by housing 338 such that the distal end of the actuator arm opposing the VCM may engage magnetic media 340. The Storage Element of the present invention is not limited to the use of magnetic media. Any suitable media may be used such as, for example, optical media so long as the teachings herein are practiced. It should be appreciated that awareness of the status of the components of the Storage Element is important with regard to exposure to external mechanical shock and further in consideration of other attributes of the operation of the Storage Element such as, for example, power consumption wherein the status of spin motor 342 is crucial.

107 Still referring to Figure 3, the distal end of the actuator arm opposing the VCM includes a transducer aπangement 352 and a lift tab 354. It should be appreciated that flexible circuit 330 includes various portions serving different components within the Storage Element.- A free end 330a of the flexible circuit is configured for engaging connector 332 (see Figure 2). A flex carrier platform 356 supports a main portion 330b of the flexible circuit. Flex carrier platform 356 is mounted (not shown) in a suitable way such as, for example, using stand-offs which engage housing 338. In one highly advantageous feature, a ramp 360 is supported by flex circuit main portion 330b. Ramp 360 is engaged by tab 354 on the outermost end of the actuator arm when the actuator arm is moved into its illustrated parked configuration. Supporting the ramp in this manner, having the parked actuator arm proximate to the flexible circuit, facilitates application of the flexible circuit in confirming the parked position of the actuator arm, as will be further described. Other parts of the flexible circuit include an actuator arm connection 330c (also refened to as a dynamic loop of the flexible circuit), which is connected to main portion 330b, and a flex loop portion 330d which is connected between spindle motor 342 and main portion 330b.

1J108 Attention is now directed to Figure 1 for the purpose of continuing the discussion of the visibility aspect of the present invention relative to the 751 patent. It is important to understand, with regard to prior art Figure 1, that visibility of peripheral components to the processing aπangement, consisting of CPU 30 and chipset 32, is limited based on constraints imposed by PCI bus 28. An associated penalty, alluded to above, resides in a degree of uncertainty accompanying issuance of commands through the PCI bus to a controller which interprets the commands and, in turn, issues native code directly to the peripheral. Applicants are aware that, in some instances, discretion is present in the way that commands are implemented within the controller. As an example, in the context of the 751 patent, it is assumed that a read command is issued by CPU 30 for the purpose of transferring certain data from HDA 28 to RAM 34. Accordingly, the disk (not shown) of the HDA will spin-up prior to reading the data and a sensor (not shown) will then be used to read from the disk. As is well known to one having ordinary skill in the art, the HDA is especially susceptible to external mechanical shock during sensor access to the disk At some point thereafter, the requested data will return via the PCI bus. From the perspective of the present invention, it is of interest that the status of the HDA disk motor and the sensor may be unknown. Specifically, the time at which the spin motor spins down and the sensor is parked are under control of the metrics of PCI mass storage IC 14, serving here as a controller. For example, the HDA spin motor may spin down if an additional command is not received within a predetermined period of time. Thus, spin down may occur long after completion of the requested data transfer. CPU 30 has no way of establishing the status of the HDA disk motor beyond issuing a "spin down" command, which may or may not be available, depending upon the protocol in use. Essentially, this is an open loop aπangement which is considered by Applicants as being unacceptable.

1Q9 Attention is now directed to another prior art interface, CF+ which is mentioned above with regard to its use in the IBM Microdrive, in further examining discretion in command implementation with its accompanying problems. CF+ is an expanded version of CompactFlash that is enhanced to encompass various I/O devices including magnetic disk data storage. CF+ implements a CF-ATA command set which is taken from the ATA interface of IDE (Integrated Drive Electronics). One aspect of drive operation that is of particular interest with regard to the present invention resides in an awareness of the status of the head aπangement. Generally, as described, the head aπangement may be parked so as to provide its highest resistance to mechanical shock. It should be appreciated, however, that even though a head aπangement is not reading or writing data, it may be left in a floating state. One IDE command encompassed by CF+ is "Idle Immediate" (see page 74 of the CF+ specification). Typically, an idle state means that the spin motor is spinning, but there is no required status as to the head aπangement. That is, the head aπangement could be parked or floating. The actual status is left to the discretion of >the implementer. The CF+ specification and IDE/ATA itself are therefore ambiguous with regard to head aπangement status in Idle. Other CompactFlash commands which exhibit similar ambiguity include Idle, Standby, Standby Immediate and Set Sleep Mode. While the designers of the interface perhaps considered this ambiguity as advantageous in allowing design flexibility, the present invention considers this ambiguity as unacceptable in view of the contemplated operating environment.

f 110 Unfortunately, the commands described immediately above are implemented in an open loop manner whereby no confirmation of actually accomplishing a physical act thought to be associated with the command is provided. The commands merely require clear BSY and generate an interrupt without defining an associated hardware status. The response may be generated as a mere response to receipt of the command by the receiving electronics. Thus, the capability to be certain as to the operational state or condition of a peripheral is limited at best and may be essentially nonexistent.

ill The present invention, in contrast, resolves this ambiguity through operating using the processing aπangement of the overall device in direct native code communication with the Storage Element while, at the same time, serving the entire device. That is, among many available control actions, the processing aπangement directly executes head parking using native code. In this way, there is no discretion as to implementation of an "intermediate" command which requires translation by a controller to, in turn, operate the peripheral device. Further, as will be seen, highly advantageous provisions are available for confirming the positional status of the head aπangement as well as other operational aspects of the Storage Element of the present invention. Again, such monitoring provisions, in being implemented with direct control by the processing aπangement, do not exhibit the command ambiguity seen, for example, in IDE and PCI. Moreover, the present invention incorporates highly advantageous status monitoring capabilities which are implemented via native code control and which are submitted to provide sweeping advantages when operating in a potentially hostile environment, as will be described in detail at an appropriate point hereinafter.

fll2 Any degree of discretion permitted in command execution is considered as problematic, particularly with respect to operation where potential exposure to mechanical shock is a reality. The processing aπangement and Storage Element of the present invention cooperate in a heretofore unseen way wherein the processing aπangement directly controls the Storage Element in a series of control events forming a data interchange sequence. The latter is typically initiated when no more than an initial portion of the user interaction defines no more than an initial portion of the data interchange sequence. Entry of a command during a user interaction is interpreted "on-the-fly" by processing aπangement 302 in a way that serves to define control events that are related to the native code of the device that is being controlled. Additional control events are then executable immediately upon interpretation, with continuing command entry by the user. Thus, the present invention copes with potential exposure to mechanical shock, in the first instance, through a!n intimate awareness of the operational status of a shock-sensitive peripheral. Still further features cooperate with this initial feature, as will be seen.

113 As described above, even prior art hard drives resist mechanical shock at relatively high levels when the actuator is parked and the spin motor is not spinning. Storage Element 320 is similar in this regard, including still further features which enhance its resistance to mechanical shock beyond the capabilities of prior art drives. Various ones of these features will be taken up at appropriate points in the discussion below. Electronic memory, on the other hand, is immune to mechanical shock for practical purposes. In this context, the present invention recognizes that placing Storage Element 320 into its most mechanical shock-resistant state, which may be refened to as its "safe state", is highly advantageous when exposure to shock events is more likely. Of course, electronic memory aπangement 312 remains usable iπespective of the potential mechanical shock exposure environment.

114 Under the assumption mat device 300 comprises a cellular telephone incorporating a music player, it should be appreciated that such portable device genres may be subjected to significant levels of mechanical shock, for example, in being dropped or hit. The present invention recognizes that a device such as a cellular telephone is used in a general way which characteristically includes periods of time during which the phone/player combo is not likely to receive a significant mechanical shock. In particular, during actual access by the user of the device, for example, participating in a call, the device experiences a stable environmental condition. At other times, when the phone is not in use, the environment, relative to mechanical shock, is not so predictable. Such times include storage of the phone, for example, on a belt clip or in a purse. Even more precarious times include those times during which the user transitions the device from actual use to storage and vice versa. It is submitted mat the transition time is the most hazardous since the user may drop the device, thereby subjecting it to high mechanical shock. Therefore, device 300 is configured so as to utilize Storage Element 320 primarily during user access while avoiding the use of the Storage Element during transition times which immediately precede and follow user access periods. Details with regard to implementation of this highly advantageous configuration are provided immediately hereinafter.

115 Referring to Figure 2, in order to further mitigate the potential for subjecting device 300 to mechanical shock, the device includes a headphone receptacle disconnect feature. Accordingly, processing aπangement 302 unloads the Storage Element heads responsive to disconnect of a headphone plug 362 from device receptacle 325. Hence, if the device has been dropped, the heads are unloaded prior to contact of the device with the ground. In order to further enhance this feature and assuming that a headset 364 (or earpiece) is positioned on the user's head during playback, the length of a cable 366 leading to the headset and connected to the receptacle may be selected whereby disconnection will generally occur prior to the device contacting the ground. Still further benefit may be derived by providing elasticity in the headset cable. In an associated feature, head unloading time defines a minimum headphone disconnect drop height, above which there is sufficient time to accomplish the unloading operation, but below which there is insufficient time to perform head unloading. When the device is dropped below the minimum headphone disconnect height, shock susceptibility may be reduced or effectively eliminated due to protection imparted by a shock isolation mounting system provided for the Storage Element in conjunction with initial near proximity to the ground.

116 Having described certain physical attributes of device 300, attention is now directed to Figure 4a in conjunction with Figure 2. The former figure illustrates the operation of device 300, in accordance with the present invention, under a first operational scenario. A timeline is indicated by the reference number 400 with individual time periods from to to t₃₂. A user interaction 402 takes place via user interface aπangement 310 and is made up of a sequence of individual commands. Initiation of the user interaction begins with the user actuating a song selection/play button 404 (Figure 2). Thereafter, commands are used to select three songs to be played by the device. It is noted that selection of each individual song is not illustrated in the user interaction for purposes of simplicity. One example of a command sequence in selecting songs to play might be to initially depress play button 404. The initial actuation of the play button occurs over time periods o to t». The user might then use numerical menu indications (not shown) within a song menu to enter specific songs from the list over the interval comprising time periods to t^. Songs may be selected either as a group or individually. It is noted that a limited number of song titles are selected in the present exanφle for clarity of illustration; however, any number of song titles may be selected, limited only by the constraints of the physical storage available in device 300.

117 For further purposes of the present example, all three selections are made in the form of a set at one point in time such that associated data transfers may be performed without intervening delays. Having selected these songs, the user concludes the command by again engaging play button 404 in a predetermined way, as will be described, over t₂₃ to

118 Initially, the digital data representative of each of the song selections is stored by Storage Element 320. Conversion of the digital information to an audio signal by processing aπangement 302, ultimately to be made available to a user at audio jack 325, first requires moving the data associated with the songs from Storage Element 320 to electronic memory aπangement 312. As mentioned above, playing the songs from electronic memory aπangement 320 is performed with relative immunity to mechanical shock, after moving the coπesponding data from Storage Element 320 to the electronic memory aπangement During the course of user interaction 402, processing aπangement 302 monitors the user interaction to interpret user input commands, as represented by a command entry line 406.

119 Processing aπangement 302 monitors user interaction 402 for the earliest possible indication that a data transfer involving Storage Element 320 is imminent. That point may be chosen, for example, as that time when the user views a song selection menu on a display screen (not shown) of the cell phone/music player device, when the user first depresses play button 404, when the user depresses a player selection button or device operation branches to player-oriented features during a menu-driven selection sequence being performed by the user. Rather than wait until user command period 402 is complete at t₂₈, processing aπangement 302 immediately readies Storage Element 320 for the access.

120 In the present example, the chosen point in time is selected as to, when play button 404 is first actuated. Accordingly, processing aπangement 302 responds by spinning up rotatable media 340. The spin-up event is shown in a data transfer execution line 408, indicated as S/U, beginning at time to and continuing up to time - It is noted that the spin-up process can comprise the most time consuming event in the overall operation of Storage Element 320. For this reason, anticipation of the pending data access, in the manner taught by the present invention, is considered to be highly advantageous. Further in this regard, spin-up time is not an arbitrary factor, but rather, can be controlled to provide optimum results. A number of factors should be weighed in this optimization including, for example, the fact that mandating a very fast spin-up in a portable device may result in shortened battery life. Still other factors affect the rate at which data transfers can be accomplished. Among these are the speed at which the magnetic media disk is rotated. It is noted that the typical point at which the prior art initiates command execution (i.e., spin-up) is typically at t∞. The present invention achieves a sweeping advantage, in terms of mechanical shock protection, by initiating command execution at a far earlier chosen point in time.

121 Having accomplished spin-up, data transfers can be accomplished in very rapid succession thereafter. In this regard, transfers illustrated in the present figures >are shown as each taking one time period, while the spin-up time is shown as taking four time periods. It should be appreciated, however, that the time durations of the spin-up and data transfers may vary relative to one another according to particular implementations. The data transfers are indicated as T1-T3 wherein one of the transfers is associated with each song to be played. The present invention recognizes that the duration of data transfers to and from the electronic memory aπangement can be controlled in an affirmative manner that is not only operationally effective with regard to limiting exposure of Storage Element 320 to mechanical shock, but is also cost-effective.

f 122 Still referring to Figures 2 and 4a, data transfer TI begins at time t₈, immediately upon completion of entry of transfer command 406. Transfers T2 and T3 begin at times and tio, respectively. In essence, each transfer requires a data interchange sequence defining a series of control events that are discreetly executable by processing aπangement 302. As noted above, each transfer is completed in a single time period. Following completion of transfer T3 at time tn, processing aπangement 302 "shuts down" the Storage Element spin motor and parks its head sensor aπangement over time periods tu and tι₂, indicated as S/D, to place the Storage Element in the safe state. In this regard, it is noted that the shut-down process may be somewhat long compared to the data transfer times, again depending upon the particular implementation. The more important component of the process essentially consists of unloading sensor aπangement 344 to its mechanical shock-resistant parked position. It should be appreciated that this latter operation can be performed in a rapid manner. For example, prior art hard drives are capable of parking the actuator or sensor aπangement in time periods on the order of 200 miUiseconds. With certain enhancements, the present invention contemplates parking of sensor aπangement 344 of Storage Element 320 in a time period of no more than approximately 100 miUiseconds. In any case, time periods of these orders of magnitude are typicaUy far shorter than responses seen as a result of human interaction. In the present example, the command period of user interaction 402 extends considerably beyond completion of transfer command 406 such that the Storage Element has long since been placed into its safe state pending a potential mechanical shock event during a subsequent transitional movement by the user. Alternative scenarios will be presented below.

123 Still considering Figure 4a, it is important to understand that the capability of the present invention to provide for the best protection against mechanical shock for the Storage Element during the transitory period is derived from beginning the command execution sequence at the soonest possible moment. This precept allows for completion of associated data transfers at the soonest possible time, even prior to conclusion of the user interaction. The beginning of data transfer execution may be delayed somewhat, for example, by initiating the spin-up at the conclusion of the initial actuation of play button 404 at time t_t or even until conclusion of transfer command entry at time t₈. In this regard, it is noted that nine time periods make up the actual spin-up, data transfer and spin down operations. Therefore, spin-up could be initiated as late as time t₁₉ in order to successfully complete all of the operations by time t₂s. It should be mentioned that this capability is available, at least in part, as a result of the intimate control and awareness present between processing aπangement 302 and Storage Element 320 enabled by running native code in the processing aπangement. As will be described below, a number of features may be provided to ensure that data transfer operations are at least partiaUy complete and return to the safe state is accomplished prior to a user transition of the device.

f 124 Refeπing now to Figures 2 and 4b, one highly advantageous feature of the present invention, relating to mechanical shock resistance of Storage Element 320, resides in control of the size of data transfers to and from the Storage Element. For descriptive purposes, Figure 4b iUustrates a transfer command entry 410 interpreted over time periods tι₉ through t_ to define T1-T3. It should be appreciated that these transfers utilize electronic memory aπangement 312. Spin-up occurs concuπent with transfer command entry. By sufficiently limiting the overaU storage capacity of the electronic memory aπangement, the duration of time required by any data transfer is limited to the coπesponding time that is required to fill electronic memory aπangement 312. In the example of Figure 4b, it is assumed that the electronic memory aπangement can be filled (or completely written to Storage Element 320) and then spun down by processing aπangement 302 in no more than five time periods, providing for completion of data transfers T1-T3. Hereinafter, this specific length of time may be refened to as the "memory fill" time period indicated by the reference number 412. In this connection, the reader is reminded mat the user of device 300 is required to actuate play button 404 so as to conclude the user interaction. In order to ensure that all data transfers involving Storage Element 320 are completed at or before the conclusion of the user interaction, the user is required to press play button 404 for a time period that is at least as long as the memory fill time or may require a confirmation action (such as, for example, subsequently depressing a button). This actuation of the play button may be refened to hereinafter as "play initiation" or "command initiation". Again, such time durations, as contemplated here, are extremely short in terms of human perception. As a practical example, the present invention contemplates a memory fill time of approximately 2-4 seconds using an electronic memory aπangement having a capacity of 32 MB. It should be mentioned that limiting the size of the electronic memory aπangement is attended by the further advantage of cost savings. As wiU be seen, the present invention uses the electronic memory aπangement in ways that might lead a user to beUeve that an electronic memory of a much greater size has been provided. Of course, larger size electronic memories may be employed while still practicing the teachings disclosed herein by appropriately setting a maximum size data transfer.

f 125 Other modifications are equally within the scope of the present invention. For example, the Storage Element spin-up time may be included as part of the memory fill time to define an "extended memory fiU time". In this instance, the user is required to press play button 404 for the additional length of time encompassing the drive spin-up time. The Storage Element spin-up time may be on the order of, for example, less than 500 milliseconds. In the event that the user fails to depress the play button for a sufficient period of time, an audio and/or visual alert may be provided. Moreover, insufficient actuation of the play button may trigger an immediate shutdown of the Storage Element, ignoring any pending data transfers in order to avoid the mechanical shock threat which is present during user transitioning of the device, foUowing the incomplete user interaction. In the presence of such constraints placed upon the user, it is considered that the user wiU quickly learn to use the device consistent with imposed requirements for best protecting Storage Element 320 from the risk presented by mechanical shock. Even with the foregoing operational constraints in place, it is considered that a user may operate and treat device 300 in essentiaUy the same manner as a device conventionally configured without Storage Element 320. That is, any differences are intended to be essentiaUy inconsequential from the viewpoint of the user. As an alternative, presentation of a play option may be precluded until such time that data transfers from the Storage Element to memory have been completed.

126 Turning now to Figures 2 and 4c, in one feature associated with the use of a limited size electronic memory aπangement, the present invention operates in an opportunistic manner when handling data transfers that are larger than tiie memory fill size. Figure 4c illustrates a user interaction sequence 420 having a first User Access Event which itself defines six data transfers having a combined size ithat is twice the siz;e of electronic memory aπangement 312. That is, the user interaction defines a total transfer size that exceeds the capacity of the electronic memory aπangement. The first user interaction begins at to and continues until time tπ upon release of play button 404 or other such identifiable event. The six transfer commands are entered during a transfer command entry period 422. In the present example, the first three transfers are selected as a group whUe the last three are individually selected. The user may have selected the song items to he played by viewing different song lists in some random order, thereby creating an extended command entry period having idle times between selections. Again, this command entry period has been shown in a way that accommodates iUustrative limitations of the present forum which, when drawn in proportion, would appear much longer in duration compared, for example, to transfer times. Individual transfer commands are not shown in User Access Event 1 for purposes of simplicity.

127 Spin-up of rotatable media 340 of Storage Element 320 is initiated at time to with actuation of play button 404 (indicated as P/B), prior to transfer selections made by the user. Transfer of the digital data coπesponding to the first song selection ensues on a data transfer execution fine 424 at a time during the transfer command entry when the user selects the song coπesponding to TI. Thus, in the present example, command execution begins not only prior to the end of user interaction 400, but even before actual completion of command entry 422 by the user. Alternatively, spin-up of tiie Storage Element magnetic media may be delayed until time t₂, coπesponding to the definition of transfer TI being available, in view of the ongoing entry of the transfer command sequence during transfer command entry 422; however, entry into the safe state of the Storage Element is thereafter delayed by a portion of the spin-up time.

128 By initiating spin-up upon detection of actuation of the play button, each of the T1-T3 data transfers may be performed almost simultaneously with the associated command defined within User Access Event 1. As mentioned above, it is also considered to be advantageous to spin-up responsive to a menu selection sequence initiated by the user at a point which branches to player functionality. In any case, for play initiation, the user is required to depress play button 404 for the predetermined period of time from β to tπ, coπesponding to that time which is required to completely fill electronic memory aπangement 312 after the command entry selections. The actuation is indicated as play initiate (PI) in user interaction 420. It is observed that the transfers are complete and the Storage Element is placed into its safe state weU before the earliest time (tn) at which the user may release the play button for play initiation of aU pending data transfers. In the event that the user fails to successftdly play initiate the selections, the pending transfers may be canceled and the Storage Element immediately placed into its safe state. At the same time, an enor signal may be provided to the user. The eπor signal serves at least two purposes. First, it informs the user that an eπor was made such that the user may modify future selection entry to avoid the inconvenience of canceled selection transfers. Second, the eπor signal is intended to introduce a delay prior to the user transitioning the device, for example, to a belt clip or purse. In this regard, it is considered that even the slightest delay on behalf of the user will provide for proper entry of the Storage Element into the safe state prior to transitioning of the device. As another alternative, the Storage Element may be placed in the safe state immediately upon indication by the user that no additional selections are to be made which would require an associated transfer. For example, upon being presented with a screen display asking, either alone or as one choice in an overall menu, "Make another selection? y=l, n=2. x?", an "n" or "no" choice may result in immediately placing the Storage Element into the safe state, iπespective the status of ongoing and/or pending transfers. In most cases, it is considered that a majority of the transfers requested by the user will opportunistically be completed while the user interaction is underway. StiU further alternatives may be developed by one having ordinary skiU in the art in view of this overaU disclosure.

f 129 Having fiUed the electronic memory aπangement using T1-T3, the data stored therein may be used in any suitable way. For exemplary purposes, the present discussion assumes that the data is used to generate a music signal during an interval labeled as II. The present example further assumes that the data is used to form the music signal at a rate that is one-sixth the rate at which the data may be transfeπed. Of course, such data is much more likely to be used at a far slower rate, in comparison with the data transfer times. For the purpose of playing music files with state-of-the-art compression, AppUcants contemplate a play time of approximately 60 minutes where the electronic memory aπangement has a size of approximately 32 MB. Because the user-defined transfer is incomplete until such time that all six song selections have been made avaUable for listening, processing aπangement 302 is advantageously configured for tracking use of the data that is stored by the electronic memory aπangement.

130 With regard to mechanical shock, it is desirable to perform the remaining data transfers, comprising T4-T6, so as to limit potential exposure of Storage Element 320. In accordance with the present invention, the remaining data transfers are performed at one or more opportune times. In the present example, one additional transfer of all three remaining song titles is capable of completely filling electronic memory aπangement 312. Such a transfer would include aU of T4-T6. According to the teachings above, the most opportune time to perform data transfers is generaUy during a user access. Unfortunately, because tire precise timing of subsequent user accesses is unknown, there is no certainty as to a user access taking place at the precise time when playback of the three initial transfers concludes. As will be seen, the present invention provides a highly advantageous feature to address this problem in an effective manner.

131 It should be remembered that user accesses are performed for various purposes. In the present example, accesses may be performed for the purpose of selecting songs to be played or to use other features of device 300, for example, in telecommunications modes which may include receiving and originating telephone calls and/or the implementation of other messaging services such as paging and sending and/or receiving e-maUs. When device 300 is used for any of these other intended purposes, the associated user access, like the access for the purpose of entering song selections, is likewise less subject to the receipt of a mechanical shock. For this reason, device 300 is configured to opportunisticaUy execute data transfers involving Storage Element 320 during user accesses whenever possible.

fl32 Referring to Figure 4d in conjunction with Figures 2 and 4c, one important feature associated with this opportunistic configuration resides in replacing "used" data resident in electronic memory aπangement 312 during subsequent user accesses, iπespective of the specific purpose to which the subsequent user accesses might be directed. For purposes of illustrating this feature, user interaction 420 includes a series of interactions, labeled as User Access Events 2-4, subsequent to User Access Event 1. It is assumed, for illustrative purposes, that each of these subsequent events involves using device 300 in a telecommunications mode, for example, receiving or originating a telephone call, such that playback of audio data stored in the electronic memory aπangement 312 ceases for the duration of the caU. At time tπ, User Access Event 2 is initiated. Playback of audio data stored by electronic memory aπangement 312 takes place during an interval II from the conclusion of playback initiation at tπ to tπ- At the onset of User Access Event 2, six playback time periods have elapsed, coπesponding to the playback of the song associated with the TI transfer. It should be remembered that the duration of the subsequent 'user events has been iUusttated as being extremely short in order to fit these events into Figure 4d. In reaUty, it is likely that these user events would appear extremely long relative to events such as placing Storage Element 320 into its safe state. Nonetheless, the concepts of the present invention remain effective, even in the face of the extremely short user access intervals illustrated.

133 Figure 4d Ulustrates the state of elecfronic memory aπangement 312 at tp. One-third of the stored data has been used during II; while the data transfeπed in T2 and T3 remains unused, fiUing the remaining two-thirds of the capacity of the electronic memory aπangement. When User Access Event 2 is initiated at tπ, processing aπangement 302 recognizes the opportunity to safely replace the used TI data contained by the electronic memory aπangement. Accordingly, magnetic media 340 of the Storage Element is spun up at tπ for the purpose of transferring T4 at time t₂₀. Immediately thereafter, the Storage Element is placed into its safe state. As illusfrated in Figure 4c, this process is repeated for fransfers T5 and Tθ at User Access Events 3 and 4, respectively. The data stored in the electronic memory aπangement 312 coπesponding to the T2 transfer is replaced by the T5 transfer, while the data coπesponding to the T3 transfer is replaced by the T6 transfer, respectively. Processing aπangement 302, operating as described, has orchestrated a highly advantageous cooperation taking place between the electronic memory aπangement and the Storage Element that is transparent to the user. In the instance of events which necessitate ceasing audio playback such as, for example, receipt or initiation of a caU, it is generaUy considered to be desirable to require the user to re-initiate audio playback even though audio playback could resume automaticaUy. Re-initiation serves the purpose of confirming that the user indeed wishes to continue listening to audio that is electronicaUy saved. This subsequent event re-initiation has not been iUustrated in Figure 4c due to drawing space limitations. In one feature, the user may receive a prompt to view a menu with various selections as to the use of electronicaUy saved data. As an example, the menu selections might include: 1) Resume audio playback; 2) Add more playback selections; 3) Edit playback selections; 4) Suspend playback until later; and 5) Erase cuπent selections.

f 134 It should be appreciated that there may be times when no subsequent user access events occur to enable opportunistic performance of data transfers. The behavior of device 300 can be controUed, under such circumstances, so as to implement a desired level of mechanical shock protection for the Storage Element. In order to provide the highest possible level of protection, the device may signal to the user, via processing aπangement 302, that it has run out of data to play and, thereafter, stop playing. For example, an audio statement may voiceover the playback audio saying, for example, "Please refresh the song play list." Visual notifications maybe provided as an alternative or accompanying the voiceover. Alternatively, the device may be configured to repeat playback of the data that is already present in the electronic memory aπangement. The user then has the option of initiating a user interaction in order to permit an opportunity to refresh data stored by the electronic memory aπangement.

135 The present invention provides a particular feature which is considered to be highly advantageous, for example, in the context of refreshing the electronic memory aπangement. SpecificaUy, an aπangement and method are disclosed for monitoring the environment of the Storage Element. One aspect of environmental monitoring at is encompassed is measurement of mechanical shock at the location of the Storage Element. Thus, rather than attempting to control the environment by requiring a user interaction to refresh the electronic memory, the processing aπangement may observe the cuπent shock environment and/or a record thereof in making an assessment as to whether the cuπent environment is safe enough to proceed with a "refresh" transfer. These environmental monitoring features wiU be described in detail at appropriate points below.

l36 Inputs or events, other than user accesses, may take place which ultimately require use of the Storage Element so as to create pending data transfers. In the absence of a user access coincident with the input, however, it is prefeπed to store data in the electronic memory aπangement. For example, an incoming email or voice message may be received. Under such circumstances, the present invention contemplates electronic storage, at least temporarily, within electronic memory aπangement 312. For example, an incoming email or voicemail message may always be given storage priority over digital music stored in the elecfronic memory aπangement. Initially, audio data that has aheady been played back may be replaced. When a user access is thereafter initiated, such as a telephone caU, the electronicaUy stored messages may opportunisticaUy be moved from electronic storage to the Storage Element in a manner that is consistent with the foregoing descriptions.

f 137 Under the aforedescribed situation in which pending data transfers are defined as a result of the limited storage capacity of the electronic memory aπangement, another operational condition may arise wherein a subsequent event itself requires access to the Storage Element. In this instance, the associated transfers may be performed in a sequential or interleaved manner. The reader is again reminded that the combined size of all transfers is limited by the capacity of the electronic memory aπangement which, in turn, limits the potential time duration of a "memory fiU" transfer. Additional priorities may be prescribed such that communications transfers (e.g., voice and email) have priority over music data transfers.

138 When an incoming message such as, for example, a voice mail or email is of a size that is larger than the electronic memory aπangement, storage of the message may begin in the electronic memory aπangement. In the absence of a user interaction, the user may be notified of the incoming message in a suitable manner so as to initiate a user interaction. If the user is unavailable, the highest level of protection for the Storage Element mandates postponing receipt of that particular message until a more opportune time.

139 In view of the foregoing, attention is now directed to the command design concept and command interpreter of the present invention. Having the highly advantageous recognition in hand that command entry and execution may occur concuπently, rather than sequentially, Applicants further recognize that cooperation between the processing aπangement, Storage Element and electronic memory aπangement can provide even more enhancement with regard to completion of data transfers in the most expedient manner possible, relative to a specific command. In particular, the present invention provides for "building" or designing commands in a way which is thought to implement the most rapid possible execution of associated data fransfers. One example, seen frequently in the foregoing discussions, resides in when the command specifies spin-up of the rotatable media of the Storage Element. In one feature, spin-up of media 340 of Storage Element 320 takes place once the number of defined transfers have a combined capacity that approaches or exceeds the storage capacity of elecfronic memory aπangement 312. Thus, referring again to Figure 4c, assuming that transfers T1-T3 equal the capacity of electronic memory aπangement 340 and further assuming that T1-T3 are all defined at time t» (during entry of transfer command 422), spin-up (not shown) takes place at - hi association with this . feature, the command interpreter may on-the-fly examine the size of each transfer as it is defined to monitor the overall size of the combination of defined transfers. A determination may be made, for example, of an average size transfer. At a point during user selections when the combined total size of all transfers leaves less space available in the electronic memory aπangement than one average size transfer, spin-up may be initiated. In other words, spin-up occurs when the user is within one average size selection of memory fiU.

140 The command interpreter of the present invention may also establish optimum spin-up time based on the rate of user activity during entry of transfer commands. For example, the command interpreter of the present invention may monitor the rate at which a user makes selections. In this way, an average selection rate can be established such that optimum spin-up time is determinable based, at least in part, on the average selection rate. The optimum spin-up time is determined, in essence, based on the user's history in making selections, it can be estimated at what time the user will have made a sufficient number of selections to fill or nearly fiU the electronic memory. It should be appreciated that the objective of these various features is to spin the rotatable media for a minimal amount of time necessary. In other words, it is desirable to begin transfers as soon as possible during a command entry sequence, but to avoid idle times between defined transfers such that the Storage Element is generaUy experiencing data transfers when it is spinning whereby to save battery power as one advantage. The described features may be combined in any suitable manner in order to accomplish these objectives.

141 Command design is also important with regard to implementation of other features such as the play initiate feature, described above, which serves to ensure that the Storage Element is in its safe state prior to the conclusion of a user interaction. In this connection, it should be appreciated that commands issued through the present invention encompass the complexity of the native code of the device being controlled. It is submitted that the absence of intervening layers of protocol provides, to a large degree, the capabihty to design commands in accordance with the teachings herein. Other features, typical of control events, that are at the discretion of the command designer include but are not limited to head and spin motor status. As wfll be further described, the present invention contemplates environmental status as a factor in command execution.

l42 Attention is now directed to Figure 5a which illusfrates an external view of one potential implementation of device 300. Device 300 may selectively incorporate any of the features and concepts described herein with regard to those described in this overaU disclosure. Accordingly, the device may comprise a hybrid combining the functionality of two or more separate prior art devices. SpecifϊcaUy, the combination of a wireless or ceUular telephone and a digital music player is implemented in device 300. The latter includes a housing 450, a user accessible keypad 452, a speaker area 454 positionable proximate to a user's ear, a microphone having a sound pickup (neither of which is shown) at an appropriate location on housing 450 and a display screen 460. Storage Element 320 is mounted using mechanical shock isolation features within housing 450, but is not visible in the present Ulustration. Since the capabUity to play digital music is provided, device 300 further includes an audio output jack such as indicated by the reference number 325 in Figure 2. The audio output jack is selectively connectable, for example, with audio headset 364 or any other earpiece aπangement suited for individual listening. Alternatively, the output may be provided to an audio or computer system. As described above, device 300 may incorporate a digital interface (see interface 328 in Figure 2) at a suitable location on the housing. In this way, the device may interface with a user's computer at least for purposes of monitoring and controlling the digital music or other data saved on the Storage Element. The present invention further contemplates connection of device 300 to another portable device including, but not Umited to another, identical portable device for purposes of data sharing.

f 143 Turning now to Figure 5b in conjunction with Figure 5a, a series of screen shots wiU be described illustrating the operation of device 300 primarily with respect to its digital music mode and associated features. Figure 5b illustrates screen 460 of device 300 wherein a selection menu is presented to the user. The user may select either "Phone" or "Player", for example, by using up and down aπow keys 464 and 466, respectively, on keypad 452. In the present example, it is assumed that the user selects the Player option.

f 144 After selection of the Player mode, Figure 5c iUustrates one possible presentation given on screen 460. Upon entering the player mode, it should be appreciated that the user may have previously been using the player only to be interrupted by a telephone caU or perhaps may have stopped playback for some other reason at a point during a playlist. Accordingly, a menu is presented having four choices including "Resume Play", "Review Playlists", "Create New PlayUst" and "Previous Menu". The "Resume Play" selection starts play of a previously selected playUst at the point where playback was last stopped or paused. Such a previously selected playlist wiU remain available in electronic memory aπangement 312 (see Figure 2) until such time that the user chooses to replace it. The "Review PlayUsts" selection permits the user to select any previously created playUst available on the Storage Element. PlayUsts may be created using keypad 452 and display 460 or may be created using an external computer interfaced with device 300 via its USB interface port (Figure 2) or other suitable interface aπangements. The former process is initiated with the selection of the "Create New PlayUst" selection. Selection of "Previous Menu" returns the user to the display of Figure 5b.

145 Turning to Figure 5d, for purposes of this figure, it is assumed that the "Review Playlist" selection was made in Figure 5c. Consistent with this selection, a playlist menu is Ulustrated in Figure 5d. The present example iUustrates the display of Playlists 1-3 as well as the option to select "More Playlists" wherein the choices coπesponding to PlayUsts 4-6 may be displayed (not shown) along with continuing to display the "More PlayUsts" selection where stiU further playUsts are available. While the playlists described here are genericaUy numbered, the user may create customized names that are displayed in association with each playlist. For example, the artist's name and/or the title of the work may be displayed.

146 Selection of one of the playlists on the screen of Figure 5d results in the presentation of screen 460 of Figure 5e. Selection options are presented for "Song 1", "Song 2" and "Song 3". Selection of any one of these initiates playback of the associated song from electronic memory aπangement 300. Again, the songs have been genericaUy numbered here, but the user is readily provided with the option of customizing the song names, for example, with the actual song title. Additional options may be selected in Figure 5e including "More Songs" which presents the next three song selections and which may be repeated until the playUst has been exhausted. A "Load PlayUst" selection returns the user to the display of Figure 5d. The user may alternatively select "Edit Playlist" for the purpose of modifying an existing playUst or for creating a new playlist.

147 Referring to Figures 5d and 5f, selection of one of the playlists shown in the display of Figure 5d that is available on Storage Element 320, but which is not cuπently available in electronic memory aπangement 312 requires transfer of the associated data from the Storage Element to the electronic memory aπangement. Consistent with the desire to protect the Storage Element during data accesses, as described above, the iUusttated "Loading" screen or a sirmlar such display may be presented to the user during the data transfer. This screen may be presented, for example, coπesponding to the time during which the Storage Element is not in its aforedescribed safe state.

f 148 Referring to Figure 5g in conjunction with Figure 5f, after the Storage Element has returned to its safe state, a "Play" and "Previous Menu" selection are presented to the user. Generally, in this situation the user is awaiting availabitity of the playlist for immediate Ustening (ie., viewing the display of Figure 5f) and is thought to be very Ukely to wait the few seconds required until the display of Figure 5g is presented in order to make the "Play" selection. Thus, the user is given the option to initiate playback only after the Storage Element is in its safe state. Any of the foregoing screen displays may be modified in any suitable manner while remaining within the scope of the present invention.

149 Referring again to Figure 3, attention is now directed to certain aspects of the aπangement and operation of electronic components as part of Storage Element 300. In particular, a channel IC 500 is physically supported by and in electrical coinmunication via main portion 330b of flexible circuit 330. A pre-amp IC 502 is also supported on portion 330b of the flexible circuit. One advantage attendant to positioning the channel IC on the flexible circuit resides in eliminating the need for a printed circuit board (PCB) as part of the Storage Element. It should be mentioned that main portion 330b of the flexible circuit is "wrapped" around flex carrier platform 356 such that signal routing and components may be mounted on the flexible circuit below the flex canier platform. One component so positioned, in the present example, is a servo IC. Of course, such components are not visible in the present iUustration. Main portion 330b of the flexible circuit may be bonded to platform 356 in any appropriate manner including, but not limited to the use of a suitable adhesive.

150 At first blush, it may appear that locating these three ICs in the Storage Element is readily accomplished. However, in the instance of channel IC 500, a number of complications, which are neither trivial nor obvious, must be overcome in order to locate it on the flexible circuit. Not the least of these compUcations relates to noise encountered on the flexible circuit. The various signals carried by the flexible circuit include, for example, control signals that are digitally generated with extremely fast rise and faU times; also refened to as "sharp edges". One of ordinary skiU in the art appreciates that the edges of such high level control signals produce considerable interference in the form of radiated energy. At the same time, raw data passes through pre-amp IC 502 enroute to channel IC 500 after having been read by sensor aπangement 346. The combined presence of the low-signal-level raw data and the control signals at the flexible circuit is of concern with regard to potential corruption of the low-level signals. Processing performed by channel IC 500 on the flexible circuit introduces stfll further concern.

151 StiU considering the location of channel IC 500, it is submitted mat one of ordinary skill in the art, in order to cope with this interference problem, would position the channel IC almost anywhere but the flexible circuit, for example, on a printed circuit board. As exempUfied by the IBM Microdrive, discussed above, the channel IC is part of the PCBA external to the HDA. The PCBA, in being isolated from and a separate part with respect to the HDA, is less subject to the interference that is present at the flexible circuit. Moreover, special interference provisions maybe built into the area of circuitry associated with the channel IC. Such provisions can be quite intricate, based on the relatively vast amount of space available on the PCBA. Alternatively, one of ordinary skiU in the art may place a separate PCB within the HDA assembly for mounting the channel IC. This latter aπangement is attractive to one of ordinary skUl in the art again for the reason that the PCB can isolate the channel IC from the interference. One appealing aspect, stemming from the prior art and which is appUcable to locating the channel IC on either form of printed circuit board, resides in the fact that locating components on printed circuit boards is far less expensive than locating such components on the flexible circuit.

1J152 The present invention resolves the foregoing interference problem by controlling signal characteristics using low level signaling (for example, 1-1.8 volts or less), as weU as signal routing on the flexible circuit and IC pin-out locations.

153 With continuing reference to Figure 2, the present invention recognizes a particular advantage that results from locating channel IC 500 on flexible circuit 330. In order to achieve optimized performance from a controller and particular HDA, the channel IC must be customized to the particular media and sensor combination of that HDA. That is, during normal production of a prior art hard drive, a programming step must be performed which controls the specific way in which the channel IC interacts with the HDA. Applicants are aware of no other way to achieve such optimized performance, short of programming yet another channel IC. Thus, in order to achieve optimum performance, the present invention recognizes that a "customized" channel IC must remain with its associated HDA after programming. In the prior art, programming functions directed to this customization or at least resources directed to executing them are generally permanently incorporated in memory associated with a hard drive controller on the PCBA of the hard drive. In the absence of channel customization, degraded or what may be refened to as "generic" performance is obtained from a particular channel and HDA combination.

f 154 Briefly considering the 751 patent, AppUcants find no teachings with regard to customizing a channel IC that remains permanently associated with a particular HDA without an associated control aπangement. While the patent suggests locating the channel IC in the HDA, in the host computer or distributed therebetween, the patent is devoid of teachings with regard to selecting any one of these locations as being advantageous. Thus, only generic performance appears to be available.

155 With the channel IC in a distributed configuration or wholly within the host computer, customizing the channel is still further compUcated. In particular, it should be understood that the 751 patent embraces a modular system approach wherein peripherals such as an HDA are provided separate from the host computer and typicaUy originate from different vendors. One advantage of such modular systems is seen in the abiUty of even an end user to initially assemble the system and to add components, as needed. Under these circumstances, with aU of the components coming together at the hands of the end user, there is no way in which a customized channel can be provided for any particular HDA and channel combination. In this regard, the present invention considers channel customization by an end user as impractical. The channel customization procedure, normally performed during manufacture, is generally time consuming. For example, customizing the channel for a 20 GB (capacity) hard drive may readUy require 60 to 90 minutes. An even more compelling reason for avoiding the idea of end user customization of the channel IC is evidenced by the fact that the channel programming and test process serves in a quaUty control sense during manufacture. That is, an HDA/channel combination may be rejected at manufacture by fafling to perform above a specified threshold.

f 156 The present invention considers dismissal of a quaUty control function, placed out of reach of the manufacturer, as unacceptable. Shifting such a manufacturing-oriented quaUty control function to the end user is likewise considered as virtually inconceivable. The alternative, inherently exhibited by the 751 patent, is to settle for generic performance levels. The present invention further rejects this latter alternative and provides a highly advantageous and heretofore unseen solution which is described hereinafter.

157 Referring to Figure 3, it is initially important to understand that channel IC 500 is customized to magnetic media 340 and sensor aπangement 344 of Storage Element 320. The ability to provide a customized channel is attributable, in part, to the recognition that the channel IC is only programmable, from any standard of practicality, by the manufacturer of Storage Element 320. In this way, a value-added reseller may provide a device such as, for example, device 300 including Storage Element 320 configured for optimized perfoπnance, including a customized channel.

158 Still referring to Figure 3, attention is turned to an additional advantage related to channel IC 500. SpecificaUy, the latter includes a channel characteristics section 510 comprising a nonvolatile area which contains certain information related to the configuration of the Storage Element. This infoπnation may include, for example, the storage capacity of the Storage Element, and the attributes of the section of the disk containing the system configuration. The purpose in providing channel characteristics section 510 resides in configuring the Storage Element such that anticipated and/or typical changes in the Storage Element do not necessitate changes in other portions of the Storage Element such as, for example, in processing aπangement 302. That is, the processing aπangement within an overaU host device may be configured to read the channel characteristics section, for example, during an initial boot-up sequence to provide for appropriately accessing the Storage Element. In this way, a single processing aπangement may access a variety of different Storage Element configurations with no attendant modification of the processing aπangement required.

159 Attention is now directed to a number of other highly advantageous features of the present invention which protect the Storage Element from the effects of mechanical shock and which generaUy enhance its reUability. As described above, HDD's are susceptible to failure when the head or heads contact the media, for example, as a result of reception of a mechanical shock which is sufficient to move the head aπangement. In the absence of rotation of the media, the failure is usually catastrophic since the heads wUl become stuck to the media; relative movement wiU thereafter tear the head(s) from the actuator arm. One aπangement for parking the head aπangement is described in U.S. patent number 4,933,785 issued to Morehouse et al (hereinafter Morehouse). The latter describes a ramp configuration wherein the head aπangement rides against the ramp to be received in its parked position by seating in some sort of detent formed in the ramp.

f 160 Once the head aπangement is in the parked position, latching aπangements are typically reUed on to restrain movement of the head aπangement as a result of mechanical shock. WMle prior art ramp parking aπangements and cooperating latching aπangements are generaUy suited to their intended appUcations, it is submitted that such aπangements remain susceptible to certain problems which, until now, remain unresolved. For example, a controUer may initiate parking of the head aπangement, however, the head aπangement may not fully transfer to its parked position. That is, the head aπangement may sUde only partially up the ramp, failing to reach the detent. Alternatively, the head aπangement may engage the ramp with too much momentum- sliding up the ramp only to hit and bounce off of a hard stop at the end of the ramp, stopping away from the detent and out of position. In either situation, it is quite likely that a latching aπangement wiU thereafter be incapable of restraining movement of the head aπangement since such latching aπangements are normally designed under the presumption that the head aπangement is at least initiaUy located in its parked position (i.e., seated in the detent). Moreover, particularly for shock forces which tend to move the head aπangement down the ramp and toward the magnetic media, the magnitude of force required to initiate movement is significantly reduced, as compared to starting with the head aπangement seated in the detent. At the same time, the controUer (processing aπangement) is unaware of this status which is likely to soon result in a catastrophic drive faflure.

161 The foregoing discussion evidences a void in the prior art with respect to recognizing a need for monitoring at least certain aspects or attributes which are related to the operational status of an environmentaUy sensitive electromechanical data storage aπangement. The present invention, in contrast, recognizes this need, particularly with regard to implementation in portable devices. Attributes of concern at the Storage Element of the present invention include, but are not limited to positional status of the head aπangement, rotational status of the spin motor, environmental temperature at the Storage Element and the shock environment being experienced. Once a view to these attributes is provided, appropriate responses may be formulated, as will be described in the context of a number of attributes immediately hereinafter.

162 Referring to Figures 3 and 6, attention is now directed to a highly advantageous actuator arm position sensor. These figures illustrate actuator arm 344 in the parked position. Consistent with terminology of the art, this position may be refened to as having the "heads unloaded". Conversely, the term having the "heads loaded" may refer to the position when die actuator arm or head/transducer aπangement is positioned for reading magnetic media 340. Figure 6 illustrates a portion of Storage Element 320 including actuator arm 344, portion 330b of flexible circuit 330 supported by flexible carrier platform 356 and ramp 360. It is noted again that the flexible circuit "sandwiches" flexible carrier platform 356. In the illustrated actuator arm position sensor implementation, a tab 510 is integrally formed using a portion of the flexible carrier platform, with the tab thereafter being bent upwardly. A tab portion 512 of the flexible circuit is formed integraUy with that portion of the flexible circuit which is beneath flexible carrier platform 356, as seen in Figure 6. Tab portion 512 of the flexible circuit may be attached to support tab 510 in any suitable manner such as, for example, using a suitable adhesive. A contact button 514 is aπanged on and supported by tab portion 512. A conductive trace, which is not visible in the present illustration, is integraUy formed with the flexible circuit and connects electricaUy with contact button 514. Electrical monitoring of the status of the contact button is thereby provided for any monitoring aπangement having access to the flexible circuit such as processing aπangement 302 shown in Figure 2. Contact button 514 may be formed using, for example, a solder bump, a dimple formed in the flex circuit, a protrusion in the underlying flexible canier platform which "outsets" the contact area or any suitable combination of such design concepts. It should be appreciated that the use of a flexible circuit and carrying platform is not a requirement. For example, a stationary contact configured to engage the actuator arm in the parked position may be supported in any suitable manner including directly by the housing of the Storage Element. Alternatively, a component carrying substrate may be used in place of the combination of the flexible circuit and carrying platform.

163 StiU refeπing to Figure 6, as previously described, a portion of the flexible circuit comprises flex actuator arm connection 330c. A portion of this latter element extends from the position at which it is received by the actuator arm along the length of the arm to an electrical contact area 516 supported by a contact support surface 518. The contact support surface may be integrally formed with the actuator arm or produced separately therefrom for suitable attachment to the actuator arm. Electrical contact area 516 may be fixedly attached to the contact support surface in any suitable manner such as, for example, by using an adhesive. Actuator arm 344 is shown in its parked position with lift tab 354 seated in a detent 520 formed in ramp 360. Contact button 514 and contact area 516 are aπanged such that electrical contact is maintained between these latter two elements when the actuator arm is in its parked position. In this regard, flex actuator arm connection 330c (see Figure 3) of the flexible circuit is used to apply a resiUent bias whereby to maintain such electrical contact in the absence of mechanical shock forces below a predetermined threshold value. The flex actuator arm connection arm or dynamic loop may be configured in any suitable manner to this end. While Figure 3 iUustrates a configuration having primarily one bend, an "S" curve, as shown in Figure 6, is considered as being particularly effective. It should be appreciated that this overaU contacting aπangement may be modified by one having ordinary skiU in the art in any number of alternative ways. For example, the actuator arm is generally at ground potential. Rather than button 514 contacting the flexible circuit, the button may contact the grounded body of the actuator arm so as to bring the button and flexible circuit trace in communication therewith to ground potential.

164 With continuing reference to Figure 6, another actuator arm position sensor implementation wiU be described. SpecificaUy, ramp 360 is formed having an electricaUy conductive volume 522 defined between a pair of dashed lines 524. Conductive volume 522 itself defines a landing surface 526 which contacts lift tab 354 in the parked position. Volume 522 extends to a lowermost surface of the ramp proximate to flexible circuit 330b. A contact pad (not shown) may be formed as part of the flexible circuit, having an associated trace for external communication, to maintain electrical contact between the ramp conductive volume and the flexible circuit contact pad. In accordance with this aπangement, ramp 360 may be formed, for example, by injection molding using Teflon® for non-conductive portions of the ramp and carbon fiUed Delrin® for electricaUy conductive volume 522. The lift tab is generally at ground potential by virtue of electrical communication with the actuator arm. When lift tab 354 contacts the landing surface, conductive volume 522 and the associated trace in the flexible circuit are brought to ground potential. Of course, as an alternative to a groimded lift tab, a separate, electricaUy isolated conductor [not shown] may be routed to the Uft tab along the length of the actuator arm for purposes of contacting landing surface 526 using an appropriate aπangement on lift tab 354.

165 With regard to both implementations of head aπangement/actuator arm position monitoring mechanisms, it should be appreciated that an unlimited number of modifications may be made by one having ordinary skiU in the art in view of this overaU disclosure. AU such modifications are considered to reside within the scope of the appended claims. Irrespective of the specific manner in which the actuator arm position monitoring aπangement is implemented, the advantages provided through its use are considered to provide sweeping and heretofore unavaUable improvements in a number of areas, as wiU be described at appropriate points hereinafter.

f 166 Turmng now to Figure 7, an actuator arm position monitoring circuit is generally indicated by the reference number 600, as shown within a dashed box. This latter circuit generaUy forms a portion of the Storage Element and cooperates with the actuator arm position monitoring sensor of the present invention, as diagrammatically iUusttated and indicated by the reference number 602 in the form of a switch within a dashed box. Any form of actuator arm position monitoring sensor may be used, as described above or with suitable modifications. Circuit 600 includes signal drivers 604 and 606, a flip-flop 608 and a data register 610 storing five bits of information denoted as bits t, z, c, x and y. Register 610 is, in turn, accessible to previously described processing aπangement 302. As mentioned above, in certain implementations where a transitional IC is used, register 610 may be accessed by the processing aπangement using one or more vendor unique commands. Alternatively, the register is read directly by the processing aπangement. A resistor Rl is connected to a V+ power supply so as to puU-up the output of driver 606 along with the line leading to the actuator arm positioning aπangement, as wi be described.

•J 167 Processing aπangement 302 reads the status of actuator arm position monitoring circuit 600 using bits x and y. Bit y indicates a cuπent status of the actuator arm position sensor. Signal driver 604 provides the cuπent status value both to the y register position and to a clock input of flip-flop 608. Other implementations may set D to a high logic level. In the present example, the D input of flip-flop 608 is grounded. The x register value comprises an output Q of flip-flop 608, as will be further described. It should be appreciated that high and low logic levels are not generally used in the present discussion with regard to state indication since the circuitry is readily adaptable to use either logic value as a "true" value. Accordingly, a value indicative of the actuator arm sensor being in its closed position is considered as true. The z register comprises an enable signal provided to an enable input of signal driver 606 which may be set by processing arangement 302, as desired. The t register position aUows processing aπangement 302 to provide a logical value that is driven onto the output of signal driver 606 when the latter is enabled by the appropriate value stored in the z register position. In this way, test functionality is provided whereby a selected value may be placed on the output of signal driver 606, iπespective of whether the actuator arm sensor switch is in' its open position. The test value is then available in register y via signal driver 604 for access by processing aπangement 302. The test value read from the y register location can then be compared by the processing arrangement with the expected value to confirm proper operation of the circuitry.

f 168 For purposes of monitoring the status of the actuator arm position sensor during operation of the Storage Element, flip-flop 608 may initiaUy be reset by processing aπangement 302 upon movement of the actuator arm away from the parked position. That is, the x register value is reset while the actuator arm position sensing switch is open (false) using the c register position. Accordingly, during ongoing access of media 340 (Figure 3) the x and y register locations both store a false value. The x and y register values will change, however, once the actuator arm returns even briefly to the parked position. InitiaUy, it is assumed that the actuator arm reaches the parked position so that lift tab 354 seats properly in detent 520. Once the actuator arm position sensor (in any of the aforedescribed implementations) switches to the true state, a true value is presented by signal driver 604. This value is stored in register location y. At the same time, the true value is presented to the clock input of flip-flop 608. Any voltage waveform edge provided to the clock input of the flip-flop will cause the output of the flip-flop to toggle to the true value which is then saved in register location x, as provided from the Q output of the flip-flop. Thus, both the x and y registers store a true value. Upon reading this condition, processing aπangement 302 is substantially assured that the actuator arm is in the parked position. The foregoing describes parking in a "normal" manner. That is, the actuator arm is moved away from accessing the magnetic media with just enough energy to slide lift tab 354 up the sloped face of ramp 360 to thereafter seat and be captured in detent 520. f 169 Having described the result that obtain* relative to monitoring circuit 600 when the actuator arm parks normaUy, various scenarios wUl now be considered in which the actuator arm fafls to reach the parked position in the normal manner. In a first scenario, the actuator arm is simply moved with an insufficient amount of energy such that lift tab 354 may engage the sloped face of ramp 360, but fails to reach detent 520. In this case, the x and y values will both remain false. Upon sensing this condition, processing aπangement 302 is substantially assured that the actuator arm is not parked or unloaded. One of ordinary skiU in the art will appreciate that the Storage Element or any HDD, for that matter, is in grave danger of catastrophic faϋure in this scenario. The present invention, by producing an unequivocal indication of this danger, provides that appropriate remedial actions may then be taken, as described at appropriate points below.

% 170 In a second scenario wherein the actuator arm fails to park normaUy, the actuator arm is moved away from a loaded position with excessive force appUed thereto by the voice coil motor. In this regard, it should be appreciated that the actuator arm is generally configured to encounter a stop (not shown) which prevents the actuator arm from overshooting ramp 360. Unfortunately, however, the actuator arm may bounce off of the stop. Actuator arm position sensor circuit 600 will initially toggle to true values for both the x and y registers. As a result of the bounce, however, the y register value then toggles to false. Processing aπangement 302 observes a true value for x and a false value for y. GeneraUy, this status seen in the x and y registers is indicative of a bounce. The Storage Element or HDD employing this aπangement is again in danger of catastrophic failure. Upon this observation, remedial measures may be taken by processing aπangement 302 including modification of the drive signal provided to the voice coil motor, as will be further described.

171 Attention is now directed to Figure 8 which is a partial cut-away view of voice coil motor end 346 of actuator arm 344. Voice cofl 350 is shown positioned between lower magnetic plate assembly 348 and an upper magnetic plate assembly 630. A magnet 632 forms part of the lower magnet assembly for producing a static magnetic field between the upper and lower assembhes. Actuator pivot 351 is also shown. Lines of magnetic flux are indicated by the reference number 634 extending between the lower and upper magnet plate assembhes, cutting through voice coil 350. Applicants have recognized that the voice cofl end of the actuator arm exhibits a resonant frequency in a direction indicated by a double-headed aπow 636. Applicants, more importantly, have recognized that, because the voice coU is positioned in a magnetic field, an opportunity is provided for a remarkably advantageous technique and aπangement directed to monitoring the shock environment of the Storage Element as an operational attribute in the context of operation of the Storage Element of the present invention.

172 Referring to Figure 9 in conjunction with Figure 8, details with regard to monitoring the shock environment of Storage Element 320 will be described. In view of the foregoing discussion, it should be appreciated that the voice coil motor end of actuator arm 344 vibrates normal to its plane of motion for data access at its resonant frequency responsive to the Storage Element being subjected to external shock forces having a component that is normal to the plane of the actuator arm. Accordingly, voice coU 350 wiU move consistent with the direction Ulustrated by anow 636. Since the voice cofl is exposed to magnetic flux lines 634, a voltage is generated by the voice coU responsive to this motion. Generation of this voltage has been empirically verified by Applicants. Figure 9 illustrates one possible mechanical shock monitoring circuit, generally indicated by the reference number 700, for utilizing the shock voltage. Voice coil 350 is diagrammaticaUy shown. The voice coU is electricaUy connected to a pair of drivers 702 and 704 that are themselves driven by control circuitry which has not been Ulusfrated for purposes of simpUcity. A conditioning circuit 706 includes high impedance inputs connected across voice coU 350 to pick up the shock voltage signal induced in the voice coil. Conditioning circuit 706 may include any necessary functions such as, for example, amplification and filtering. It should be appreciated that the signal level of the induced shock voltage may be quite smaU such that significant gain is required in order to increase the signal to a useful level dependent, of course, on the specific configuration of the voice coU motor aπangement and the level of shock to be detected.

173 Continuing with a description of the circuitry of Figure 9, a comparator 708 compares the output of signal conditioner 395a to a set point input of the comparator provided on a line indicated as "sens". This latter line serves as a sensitivity adjustment which may be under the control of processing aπangement 302. Moreover, the processing aπangement may vary the sensitivity adjustment in accordance with various operational circumstances. Alternatively, the sensitivity may be set during factory calibration procedures. In the event that shock voltages are presented to the comparator which exceed the cuπent sensitivity setting, comparator 708 produces a square wave output that is received by a clock input of a D type flip-flop 710. The D input of flip-flop 710 may be set to either a high or low logic level with the latter being Ulusfrated. Upon receipt of an input edge from comparator 708, flip-flop 710 toggles output Q which then is loaded into a register 712 as a bit "s". Like previously described register 610, register 712 may be located within the Storage Element or on the host side proximate to processing aπangement 302. Any location is suitable so long as it is readable by processing aπangement 302. FUp-flop 710 is reset using its clear input connected to a line that is controUed by processing aπangement 302. The flip-flop may be reset immediately after reading the s bit or within the context of ongoing processing operations. Upon detecting that the s bit is set, processing aπangement 302 may respond in a number of alternative ways, as will be described below.

174 Referring to Figure 2, as described above, entering the shock safe state of the Storage Element requires parking or unloading sensor/head aπangement 344. In this regard, the present invention recognizes that an awareness of the position of the head aπangement is critical to ensuring the reUabUity of Storage Element 320. Having described several implementations of the head aπangement sensing feature of the present invention, attention will now be directed to using this feature in the context of a number of highly advantageous techniques.

l75 The shock environment sensing aπangement of the present invention is considere as being highly advantageous, particularly with regard to devices such as Storage Element 302 that are intended for use in portable applications. As described previously, the shock monitoring feature of the present invention aUows the processing aπangement to gauge the shock environment of device 300 prior to initiating data storage or retrieval using the Storage Element. This feature is readily combined with any other provision described herein for the purpose of mitigation of mechanical shock effects on the operation of the Storage Element. Moreover, the shock environment is sensed within the Storage Element itself so as to account for attenuation of shock forces resulting from shock mounting the Storage Element within a portable device. Shock monitoring capability is also highly advantageous during test and development of the Storage Element and is readUy suited to any form of device, including an HDD, which utilizes a voice coU motor.

f 176 InitiaUy, it is noted that a number of prior art algorithms have been developed for the specific purpose of parking the head aπangement. Such an algorithm may be implemented in a variety of different ways for this intended purpose. Each individual algorithm may therefore operate incorporating one or more parameters, each of which influences the reUabUity or probability that the head arrangement wUl, in fact, properly reach the parked position. Such parameters may include, for example, the magnitude of a drive cuπent which is used to drive the voice coil motor in moving to the parked position, a specified position of the head aπangement from which movement to the parked position is initiated and the velocity of the head aπangement. Accordingly, the focus of (he present invention considers adjustment of any parameters that are in use within a particular algorithm in order to improve parking reUability. That is, tiie effect of adjusting any one parameter or parameter combination is discernible through the teachings herein.

177 Turning now to Figure 10, a parking caUbration method performed in accordance with the present invention is generaUy indicated by the reference number 800. CaUbration method 800 begins with a step 802 in which initial values of the parameters are set within the particular parking sequence or algorithm to be appUed. Thus, the initial values may represent values which have been developed in any suitable manner. Step 804 then proceeds by using the initial values of the parameters to actuaUy execute the parking sequence. A read of the head position indicator of the present invention is subsequently performed by step 806. Step 808 then saves the result of this particular parking sequence execution, indexed against the specific values of parameters which were employed. FoUowing step 808, step 810 tests the result of the cuπent parking sequence. In the event that this sequence fafled, execution moves to step 812 in which one or more parameters are modified, as desired. As described above, one significant parameter is the magnitude or duration of the signal used as a drive signal to drive the voice coU motor aπangement in order to move the head aπangement to the parked position. For iUusfrative convenience, parameter changes may be described with regard to modifying this voice coil motor drive signal. It is to be understood that this technique is equally applicable to virtuaUy any parameter and, hence, is in no way Unύted to the voice cofl motor drive signal.

178 For the voice coil motor drive signal, the initial parameter setting may use a particular magnitude that is changed by some predetermined increment with each successive repetition of the parking sequence. It is to be understood, in this regard, that a faUure condition is typically encountered by both increasing and decreasing the voice coU motor drive from the particular magnitude. In one instance, increasing the drive cuπent sufficiently results in the head aπangement bouncing off of the parking aπangement; the head aπangement passes through the parked position twice. In the other instance, decreasing the drive cuπent sufficiently results in the head aπangement having insufficient momentum to fu y reach the parked position. Therefore, the voice cofl motor drive cuπent exemplifies a parameter which exhibits both upper and lower failure values or thresholds. That is, this parameter is adjustable both up and down in order to find an optimum value. In one feature, the optimum value may be selected as that value which is approximately half-way in magnitude between the upper and lower magnitudes at which faUure occurs. Other parameters likewise exhibit upper and lower faUure values such that this precept remains equally applicable thereto. When performing calibration sequences relating to parameters having both upper and lower faUure limits, it may be advantageous to vary the parameter from a higher or low magnitude which is almost certainly outside of the operational range that is defined between the upper and lower faUure limits. In this way, the caUbration procedure sweeps or passes through the entire operational range between the limits such that both the upper and lower limits can be found in one pass through the entire range of potential magnitude of that parameter. FoUowing parameter modification, execution moves back to step 404 to begin the parking sequence with the modified parameters. 179 Still referring to Figure 10, if step 810 does not detect a failure in the parking sequence, step 814 is entered. This latter step monitors the overall number of times that the parking sequence has been repeated for a particular configuration of the parameters. If the cuπent configuration of parameter settings has not been repeated N times, execution is returned to step 804. The parking sequence wUl generaUy be repeated a statisticaUy significant number of times, indicated here as N, for each configuration of the parameters so as to establish a probabiUty of the head aπangement reaching the parked position for that particular configuration. For example, N might be equal to 100. A single faUure in attempting to reach the parked position out of 100 tries wUl generally be considered as unacceptable, indicating a faUure threshold.

180 If, on the other hand, the cuπent parameter configuration has been successfuUy repeated N times, step 816 is entered. In step 816, a decision is made as to whether the parking sequence is to be repeated with a different configuration of the parameter settings. If that is the case, step 812 is executed whereby to modify the parameters foUowed again by step 804. It should be appreciated that the specific implementation of step 816 is dependent upon the particular algorithm that is employed by the parking sequence. Therefore, the parameter set may be modified in a manner that is suited to the particular algorithm. In this regard, it is considered that one having ordinary skiU in the art is capable of modifying any known algorithm parameter set either cuπently known or yet to be developed in view of this overall disclosure. One possible implementation might optimize one of the parameters which is initiaUy considered to be the most critical. Thereafter, other parameters within the group of parameters defined by the particular algorithm may be modified on an individual basis. Still further modifications may include changes made to more than one parameter at a time.

181 Different calibration procedures may be employed dependent upon the state of product development. For example, a rather exhaustive search for an optimum set of parameters may be performed using a relatively great number of parameter configurations on a certain number of units produced in an initial production run. Having found that initial set of optimum parameters, the parameter calibration process may thereafter be relaxed somewhat, using a lesser number of parameter configurations.

f 182 Once step 816 determines that aU of the parameter modifications targeted for execution have been completed, a probabiUty set comprising all of the values used in the parameter configurations is avaUable. Step 818 is performed whereby to choose the set of parameters to be employed for operational purposes using the probabiUty set. A number of different objectives may be brought to bear in selecting the optimized set of parameters. As mentioned above, one possible selection resides, for "two-valued" parameters, in choosing a midpoint between upper and lower failure values. It is to be understood, however, that other objectives may also be considered. In the example of the voice coU motor drive cuπent parameter, a magnitude may be selected that is somewhat closer to the lower failure limit for purposes of power conservation. This objective is particularly applicable in the instance of portable devices which operate on battery power.

183 In one highly advantageous feature, step 820 saves the optimized parameters on the magnetic media using the head aπangement. During operation of the Storage Element, these arameters are retrieved and employed by the processing aπangement, as will be further described at an appropriate point below. Therefore, each and every unit produced may operate with a customized set of parameters in terms of parking calibration as weU as other aspects of operation, as will be further described.

184 Referring now to Figure 11, a highly advantageous parameter tracking method is generaUy indicated by the reference number 900. It is noted that this tracking method may be performed as an adjunct to the foregoing calibration procedure, as wiU be further described. A production line is generaUy indicated by the reference number 902 having a plurality of Storage Elements 320 coming off of the line for entry into method 900. Initially, it should be understood that this method is advantageous in tracking changes that are occurring in the Storage Element, but which nonetheless might otherwise go unnoticed, at least until these changes reach critical levels. Since different components which make up the Storage Element are likely to be sourced from different vendors, it is possible that sufficient changes in one of these components, even where the vendor is unaware of drifting tolerance or composition changes, could ultimately produce fatal problems during operation. The present invention, through the use of its head sensor position indication aπangemenf, contemplates tracking perfoπnance drift in relation to certain characterizable aspects of performance. This overaU technique may be refened to hereinafter as "trend characterization" or "parameter tracking".

% 185 StiU referring to Figure 11, method 900 begins by initiaUy establishing start parameters in step 904. It should be appreciated that several different approaches may be employed with regard to setting the start parameters. In one approach, the parameters may be set so that faUure to reach the parked position is virtually assured. The parameters may then be adjusted in a direction toward what is known to be an operational value or range of operational values, in the case of a parameter having both upper and lower failure limits. In this manner, the faUure threshold(s) for each individual parameter and for subsets and/or the overaU set of parameters may be established, as desired. In another approach, the parameters are initialized in what is thought to be an optimized or at least operational state. The parameters are then adjusted in one or both directions toward the faUure threshold(s). Again, individual parameters may be adjusted so as to find the faUure threshold(s) of each parameter as well as finding associated faUure thresholds for subsets of parameters and the overaU coUection of parameters. Any set of values for the parameters at which a faUure threshold is present may be refened to as a faUure configuration.

186 Step 906 executes the parking sequence using the initial set of starting parameters. It is noted that execution of the parking sequence throughout this overaU disclosure is assumed to begin from having the head aπangement positioned for reading from the magnetic media or from some defined, but unparked position from which the parking sequence algorithm is designed to start. In fact, this starting position may comprise one of the parameters of the parking sequence algorithm. The starting position may define a lower failure limit or threshold nearest the parking aπangement and an upper failure, limit somewhat further away from the parking aπangement.

1(187 Step 908 then reads the head position to estabUsh whether or not the head aπangement reached the parked position. In step 910, the result of step 908 is recorded for subsequent use. Step 912 then tests the number of times that the parking sequence has been repeated, In this regard, the parking sequence may be repeated any number of times for a particular set-up of parameters so as to assure a sufficiently accurate determination of the probability of parking at those settings. As one alternative, during this repetition of the parking sequence, the incidence of one faUure may immediately move the procedure to modification of the parking parameters. 1(188 Having repeated the parking sequfence for" a particular setting of the parameters N number of times, step 914 establishes whether or not a faUure threshold was found in view of the results stored in step 910. If a faUure threshold was not found, step 916 modifies the parameter settings in a manner that is consistent with the parking algorithm being employed. Thereafter, step 906 re-executes the parking sequence. Operation continues to estabUsh whether or not a faUure threshold is found for the new settings of the parameters. When a failure threshold is found for a particular configuration of the parking parameters, step 918 saves the faUure configuration and determines whether the method is to be applied to a different parameter, subset or the overaU group of parameters. If so, the foregoing process is repeated. Otherwise, step 920 records the results for the particular unit having just been tested in the form of aU of its faUure configurations of interest. Step 922 then checks for another unit to be tested. Accordingly, any number of units may be tested from an individual production run. More importantly, this overaU process is applicable over long-term periods of time. For example, across the entire number of Storage Elements produced having a particular model number. From time to time, step 924 is employed whereby to compare the recorded faUure configurations and specific values across all of these units. Step 925 is then used to estabUsh trends in faUure values with continued production of the unit. Thus, impending problems may be averted. As an example, if frictional coefficients are trending upward as a result of changes in the composition from which ramp 360 (see Figure 3) is formed, the lower recorded faUure threshold value for the drive cuπent required to park the head aπangement will be observed to be trending upward. With this trend information in hand, an investigation may be undertaken to ascertain what is causing the increase in the required magnitude of cuπent. In this manner, any number of developing problems may be identified. AppUcants consider this process as being highly advantageous, since operational conditions are maintainable weU separated from ascertained faUure thresholds.

1(189 Although methods 800 and 900, Ulusfrated in Figures 10 and 11 respectively, are described separately for purposes of clarity, it should be appreciated that these methods are cotribinable in view of this overaU disclosure. That is, essentiaUy all of the foregoing calibration and trend tracking information maybe determined once threshold value limits embraced by failure configurations for the parameters in any particular parking algorithm have been established. In this regard, the steps of the described methods may be changed in sequence and/or modified in any suitable manner so long as the teachings herein are applied. Moreover, these methods are considered to be appUcable to the production of virtuaUy any hard disk drive. The benefit of an optimized parking algorithm wiU significantly enhance reUabUity of any hard disk drive through appUcation of the teachings herein.

1(190 Having described the use of the head aπangement sensing feature of the present invention for the purpose of calibration and trend tracking, attention is now directed to certain aspects of the use of this feature during operation of the Storage Element or, of course, during the operation of any hard disk drive produced having the head aπangement sensing feature of the present invention. As mentioned above, an awareness of the position of the head aπangement is critical to reliable operation of any hard disk type storage aπangement, particularly when the head aπangement is supposed to be parked. That is, if the head aπangement is inadvertently moved away from its parked position, for example, due to the receipt of an external shock force, its transducer is likely to be torn lose as a result of non-rotational contact with the magnetic media disk. The head aπangement sensing feature of the present invention is highly advantageous, in the first instance, by providing the abflity to actuaUy confirm that the head aπangement has been received in the parked or unloaded position. Moreover, having initially confirmed that the head aπangement is received in the parked position, its status may readily be re-confirmed, as desired. One particular application for the use of head aπangement sensing feature of the present invention wiU be described immediately hereinafter.

1(191 Turning now to Figure 12, an advanced parking control and monitoring sequence, performed in accordance with the present invention, is generaUy indicated by the reference number 1000. Method 1000 is performed by processing anangement 302 within device 300. It should be appreciated, however, that the method is readUy adapted for use in any form of hard disk drive aπangement. Method 1000 begins with step 1002 in which a parking sequence is initiated. The parking sequence employed may utilize parameters having values identified and selected, for example, using highly advantageous caUbration procedure 800 described above. Again, any suitable parking algorithm may be employed within the overall context of this method. FoUowing step 1002, in step 1004, the processing anangement reads the positional status of the head aπangement. Step 1006 then produces an indication based on this read. The indication may be provided in a wide variety of different ways. In one feature, an interrupt may be generated for receipt by the processing aπangement. In another highly advantageous feature, the indication is produced and stored in a register. The latter may be located within the Storage Element itself for subsequent access by the processing aπangement. Alternatively, the register may be located at any suitable location within the overall device so long as the processing aπangement has access thereto. This read may be performed in any suitable manner. For example, the processing aπangement may directly read the head position sensing aπangement. As an alternative, register 610 described with respect to Figure 3 may be read. If the indication, for example, per the x and y bits of register 610, shows the head aπangement to be properly parked, stop step 1008 is executed.

1(192 If, on the other hand, the bits indicate that the head anangement is not parked, step 1010 is performed in which an additional parking sequence is executed using the same parameter settings. Thereafter, step 1012 increments a recovery sequence counter (not shown). As wiU be seen, the recovery sequence counter counts the number of times that the parking sequence is repeated using its initial set of parameters. Step 1014 then tests the number of times which the parking sequence has been repeated. This sequence continues until the limit is encountered. The limit may be set, for example, in the range from 1 to any useful number of attempts.

1(193 Once the limit has been encountered, step 1016 performs a terminating parking sequence which is different from the parking sequence that is employed in the initial part of the method. The terminating parking sequence may be developed in view of a number of different considerations. For example, terminating parking sequence may vary the parameter settings in view of the bit settings in register 610. SpecificaUy, as mentioned above, if one of the bits is set, while the other bit is not set, the head aπangement has most likely bounced off of the parking aπangement. Accordingly, the parameter coπesponding to the voice coU motor drive cuπent may be reduced in magnitude for purposes of the terminating parking sequence. On the other hand, if both of the bits are not set, the head anangement has most likely not reached the parked position by virtue of lack of momentum. Therefore, the parameter coπesponding to the voice coU motor drive cuπent may be increased in magnitude for use in the terminating parking sequence. FoUowing step 1016, step 1018 again tests the status of the head aπangement's position.

1(194 While steps 1016 and 1018, in combination, Ulustrate the terminating parking sequence as a one pass-through procedure for purposes of clarity and for facUitating brevity of this discussion, it is to be understood that this terminating parking sequence may encompass a repetitive process which bears some relationship to the calibration procedure of method 400 described above. That is, p&ameter inagnitudes may be varied in incremental steps with repetition of the parking sequence, accompanied by testing the result of each variation.

K195 Step 1020 performs a final check of the head aπangement position. If a parked indication is obtained, the procedure may terminate at stop step 1008. If the indication continues to show that the head aπangement is not parked, step 1022 generates a notification indicating to the device user that a problem has been encountered which is apparently unrecoverable. The notification may be provided in any suitable form such as, for example, in an audio and/or visual form. The foregoing procedure may be modified to suit any number of operational considerations. For example, the number of times that the parking sequence is repeated with any configuration of its parameters may be controUed, at least in part, by time constraints imposed through the overall operation of the device. StUl further steps may be added to the overall process with the intent of enhancing the probability of survival of the Storage Element or other such hard disk drive type device. For example, foUowing failure of the terminating parking sequence to achieve an indication that the head aπangement is parked, the voice coU motor drive signal may be issued at a level which is intended to hold the transducers) of the head aπangement just outside the outer diameter of the magnetic media.

1(196 Having described the head position sensing aπangement of the present invention and its use in a number of highly advantageous processes, it wiU be appreciated that the present invention provides sweeping advantages over the state-of-the-art. As is the case with any of the methods described herein, the ordered sequence of steps and specific design of individual steps and/or combinations thereof which make up method 1000 are considered to be within the scope of the present invention, as modified by one having ordinary skiU in the art in view of this disclosure.

1(197 Referring to Figure 13 in conjunction with Figure 2, attention is now directed to a highly advantageous test programming board, generally indicated by the reference number 1100. Board 1100 includes a processor 1102, a controUer 1104, a channel programming routines section 1106 and a connector 1108 configured for temporarily accepting the free end of flexible circuit 330 (partially shown) during the manufacturing process. Previously described connector 332 may be used as connector 1108, provided that it will accommodate repeated connect and disconnect cycles. In this regard, board 1100 is physicaUy configured for temporary mating with Storage Element 320 during manufacturing for the purpose of customizing channel IC 500. This physical connection may be accompUshed, for example, using plastic clips. Because the physical aπangement of board 1100 and Storage Element 320 may be accomplished in an unlimited number of ways, within the capabUity of one having ordinary skiU in the art, a particular physical aπangement has not been Ulusfrated. For example, an electrical interconnection aπangement may include a first portion forming one part of the Storage Element and having a second portion forming another part of the test/programming board for detachably electrically connecting the digital storage aπangement to the programming aπangement. In one embodiment, one of the first and second portions of the said interconnection aπangement may include a set of resiUent contact members and the other one of the first and second portions may include a set of contact pads electrically connectable with the resiUent contact members for use in programming the channel.

1(198 Channel programming routines section 1106 comprises an appropriate form of memory (e.g., ROM in combination with RAM) loaded with programming for execution by processor 1102 to issue native code instructions to controller 1104. The latter is configured in essentially the same manner as a prior art hard drive controUer. That is, confroUer 1100 is configured to execute thg native code of Storage Element 320 as a requirement to customizing channel IC 320. It should be appreciated that board 1100 is configured to complete its customization and test functions in an automated manner, thereafter, to provide a result from processor 1104 using an indication section 1110. As an example, a green light 1112 and a red hght 1114 may give a pass/faU indication as to the status of the particular Storage Element. More detaUed infoπnation may be provided, as desired, by using an LCD display (not shown), for example, to isolate problematic manufacturing concerns.

f 199 Still referring to Figures 2 and 13, having described test board 1100 and its general use with Storage Element 320, a number of associated advantages and features wfll now be described. It is important to appreciate that the functionality required to customize channel IC 500 is not required in device 300. The customization process need only be performed one time during manufacturing since the customized channel, in accordance with the present invention, remains with the Storage Element. This feature results in savings with regard to manufacturing costs associated with device 300. Moreover, any functionaUty of confroUer 1104 directed to the customization and testing process are not needed in device 300. The reader wiU recall that processing aπangement 320 of device 300 executes the native code of the Storage Element. EssentiaUy, processing aπangement 302 serves in one role as a controller, without the need for test functionaUty which is needed in confroUer 1104. In this regard, any requirements for an upgraded processor in the end device, in order to execute channel programming, are avoided. It should be appreciated that the present invention contemplates a pre-existing compatibiUty between prior art devices and the Storage Element of the present invention. That is, as described above, processing power dedicated to the operation of the Storage Element may be deliberately limited to unused capabUities of processors aheady present in the architecture of a particular device. At the same time, the teachings of the present invention are readily practiced in "upgraded" devices, yet to be developed, in a way which provides even further performance enhancements in these devices.

K200 Another advantage, with regard to test board 1100 and which is directly appUcable to consideration of cost- reduction, is found on the basis that a limited number of test boards are needed within the context of any one overaU manufacturing process. That is, the required number of test boards is limited by the number of Storage Elements avaUable for channel programming at any one point in time. In this way, a single test board may be used over time to channel program and test a great number of Storage Elements. It should be appreciated that, in the absence of this aπangement, savings attendant to etimination of the need for a controUer in Storage Element 320 would be offset wherein a test board was usable on only a single or very limited number of occasions.

1(201 A further advantage is provided by the present invention due to its compatibiUty with traditional manufacturing and test procedures. In particular, only two, almost insignificant steps are added to the manufacturing process in which test board 1100 is first physicaUy connected with a Storage Element and then, after channel programming and testing, disconnected from that Storage Element. In this regard, it should be appreciated that cost savings provided in an end use device can be far outweighed where a sufficiently significant revamping of the manufacturing process is needed to produce that cost savings.

1(202 Turning now to Figure 14, attention is now directed to another embodiment of the digital Storage Element of the present invention which is generally indicated by the reference number 1200. It is to be understood that the various figures are drawn in a way that is intended' to enhance understanding and, hence, are not to scale. Moreover, descriptive positional terminology such as "upper", "lower" and "bottom" is founded only on the views seen in the various figures and in no way imposes restrictions as to actual orientations of the structures refened to either in this description or in the appended claims. To the extent that Storage Element 1200 includes components that resemble those described above, at least from a functional standpoint, such descriptions wiU not be repeated. Similar components may be refened to using like reference numbers or using identical nomenclature. While Figure 14 iUustrates the addition of a latching aπangement 1201, Storage Element 1200 differs from previously described Storage Element 320 primarily with respect to abase supported flexible circuit aπangement 1202 which itself supports a "floating", ramp aπangement 1220 that is nevertheless positioned with highly controUed tolerances with respect to other components, as wiU be described in detail immediately hereinafter.

1(203 Referring to Figure 15 in conjunction with Figure 14, the former is an exploded, perspective view selectively iUustrating components of Storage Element 1200 including a base plate 1222, a flexible circuit stiffener 1224, forming part of flexible circuit aπangement 1202 and ramp aπangement 1220 in a spaced apart relationship in order to show details with regard to these particular components that are not readUy observable in the assembly view of Figure 14. As is visible in Figure 14, flexible circuit stiffener 1224 supports a flexible circuit 1226 which, among other functions, extends to form dynamic loop 330c and to form an external connector 1228 (only partiaUy visible) aπanged along a side margin of the Storage Element.

f204 Referring to Figures 14-16, flexible circuit stiffener 1224 is fixedly attached to base plate 1222 by initiaUy inserting a pair of bendable fastening tabs 1230 through coπesponding tab openings 1232 that are defined in flexible circuit stiffener 1224 such that the lower surface of the stiffener rests against a number of support surfaces 1240 (Figure 15) that are integrally formed as portions of base plate 1222. Tabs 1230 are shown in an inserted, pre-bent condition in Figures 14 and 16. Figure 14 further iUustrates a fastener aπangement 1247 that is inserted in a through hole 1248, seen in Figure 16 defined by stiffener 1224 at one end thereof. Fastener aπangement 1247 extends into a fastener opening 1249 (Figure 15), which is threaded in the present example, so as to fixedly support the associated end of the stiffener and which further serves as a ground connection to the base plate from flexible circuit 1226.

K 05 Turning to Figure 17, tabs 1230 (one of which is shown) are bent so as to capture flexible circuit 1226 and flexible circuit stiffener 1224 between an end portion of each bendable tab and support surfaces 1240 (Figure 15) therebeneath. It should be appreciated that this aπangement is not intended to eliminate movement of the flexible circuit in a way which sets any critical tolerances with respect to ramp aπangement 1220, even though the ramp aπangement is directly supported by flexible circuit stiffener 1224 and only indirectly supported by base plate 1222. That is, ramp anangement 1220 is permitted to float or move with a relatively low degree of tolerance control with respect to flexible circuit stiffener 1224, w le the position of the ramp relative to the base plate is maintained using significantly tighter and acceptable tolerances that are controlled in other highly advantageous ways. It should be appreciated that the tolerance control available with respect to controlling the position of the flexible circuit stiffener would result in a unacceptably loose level of tolerance control if the ramp aπangement was immovably fixed onto the flexible circuit stiffener. In this regard, it is submitted that the floating ramp aπangement of the present invention may be physicaUy implemented in an unlimited number of ways while remaining within the purview of these broad teachings. Accordingly, aU of such alternative implementations are considered as being at least equivalent with respect to the appended claims. 6

f 206 With collective reference to Figures 14-19, attention is now directed to detaUs with regard to ramp aπangement 1220. Figures 15 and 16, Ulustrate ramp aπangement 1220 prior to instaUation, Figure 17 iUustrates an intermediate step in the instaUation of the ramp, and Figures 14, 18, 19 and 20 show the ramp aπangement instaUed at least in the flexible circuit aπangement. As best illustrated by Figures 17-19, ramp aπangement 1220 is formed primarily of two portions including an attachment and indexing aπangement made up of a T-lock configuration 1250 and a locking arm 1252, cooperating to attach and hold the ramp in its intended operational position on the flexible circuit stiffener, and a ramp portion 1254. The indexing aπangement includes an indexing pin 1256, seen in detaU in Figure 19, which will be described in further detaU below.

1(207 Referring to Figures 15, 17, 19 and 20, flexible circuit stiffener 1224 defines a T-lock through hole 1260 that is configured for receiving T-lock configuration 1250 of the ramp aπangement. Figure 17 Ulusfrates the ramp aπangement initially inserted into T-lock through hole 1260. This insertion simultaneously causes indexing pin 1256 of the ramp aπangement to be inserted into an indexing recess 1262 (Figures 15 and 20) that is defined by base plate 1222 having an indexing through hole 1263 defined therein. It should be appreciated that a high level of tolerance control is generally available with respect to the dimensions seen in base plate 1222 whether formed as a casting or, as seen here, by stamping. Accordingly, indexing recess 1262 and indexing through hole 1263 are precisely located not only in the major plane of the base plate, but the dimensions of the indexing recess, including the depth of its floor 1264 (Figure 20), are precisely controUable.

K208 FoUowing the initial engagement between ramp aπangement 1220 and flexible circuit stiffener 1224, as depicted in Figure 17, the ramp aπangement is rotated in a direction that is indicated by an aπow (adjacent to the ramp aπangement in Figure 17) to the locked position shown in Figures 14 and 18 as well as shown in the bottom, perspective view of Figure 19. Ramp aπangement 1220 is formed from a material having resiUent characteristics such as, for example, liquid crystal polymer (LCP) and acetal impregnated with PTFE. Rotation is terminated when a support slot 1265 (best seen in Figure 19) engages a side margin 1266 (shown as a dashed line) of the flexible circuit stiffener. Concuπently, a locking pin 1268, which is formed on a distal end of locking arm 1252 snaps into a locking aperture 1270 that is defined by flexible circuit stiffener 1224. Prior to snapping into the locking aperture and at least during initial engagement between slot 1265 of the ramp aπangement and side margin 1266 of the stiffener, locking pin 1268 is resiliently biased against the major surface of the flexible circuit stiffener proximate to locking aperture 1270 as a result of resilient deformation of locking arm 1252. Once in the locked position, locking pin 1268, locking arm 1252 and the flexible circuit stiffener are cooperatively configured such that slot 1265 is resiliently and rotationally biased into side margin 1266 of the flexible circuit stiffener. At the same time, slot 1265, like T-lock configuration 1250, serves to limit movement of the ramp aπangement in directions having a component of motion that is normal to the plane of the flexible circuit stiffener. It should be appreciated that slot 1265 is optional, as one potential modification. Moreover, any number of alternative structural expedients may be employed to floatingly lock the ramp aπangement in place so long as the broad teachings herein are reUed upon. For example, the T-lock configuration may be replaced with any suitable slot and groove aπangement. It is worthwhile to note, however, that the described locking arrangement is considered as being highly advantageous at least for the reason that it is fastenerless, as wUl be further described, although this is not a requirement since many techniques may rέly on fasteners, such as threaded fasteners, to provide for relative movement between two attached components.

K209 In one alternative method of assembly, with reference to Figures 14-19, T-lock configuration 1250 of the ramp aπangement is initially inserted into T-lock through hole 1260 in stiffener 1224. The ramp is then rotated (Figure 19) about indexing pin 1256 such that slot 1265 engages side margin 1266 as locking pin 1268 snaps into locking pin aperture 1270. Thereafter, indexing pin 1256 engages indexing ramp indexing through hole 1263 in indexing recess 1262 as flexible circuit aπangement 1202 is positioned onto bendable tabs 1230. The latter are then bent to hold the flexible circuit assembly in position.

1(210 Referring to Figure 20, attention is now directed to this greatly enlarged cross-sectional view for purposes of describing details relating to positioning tolerances that are controUed. Specifically, the opposing arms of T-lock configuration 1250 include opposing upper and lower surfaces 1270 and 1272, respectively. A first distance or thickness A, of the T-lock arms, between the upper and lower surfaces thereof, is greater than a second distance between floor 1264 of indexing recess 1262 and a lower surface 1274 of flexible circuit 1226, prior to instaUation of ramp anangement 1220. That is, distance B is established with flexible circuit aπangement 1202 held against support surfaces 1240 (Figure 15) by bendable tabs 1230 and fastener aπangement 1248. Because flexible circuit stiffener 1224 is formed from a resiUent material such as, for example, stainless steel and flexible circuit 1226 is extremely flexible relative to the stiffener, rotating ramp aπangement 1220 to its locked position applies a resultant force in a direction that is indicated by an aπow 1280 so as to resiliently bias lower surfaces 1272 of the T-lock arms against floor 1264 of indexing recess 1262. At the same time, tolerance control is estabUshed lateraUy between the sidewall of ramp indexing through hole 1263 and the sidewaU of ramp indexing pin 1256. Accordingly, a first controUed tolerance, relative to the housing and actuator arm pivot, is achieved in the plane of the flexible circuit stiffener for an axis of rotation 1282 of the ramp anangement. Moreover, a second controUed tolerance is achieved normal to the stiffener plane, relative to the housing and actuator arm pivot, so as to control distance of tamp 1254 from base plate 1222 with no direct attachment between the two. The fastenerless attachment of ramp aπangement 1220 to flexible circuit stiffener 1224 is highly advantageous in providing the desired floating response as weU as reduction of production costs and in eliminating contamination problems such as are inherent in the use of threaded fasteners. Control of rotational tolerance about axis 1282 wUl be described immediately hereinafter. In a sense, the floating ramp positioning aπangement of the present invention can be considered as automaticaUy positioning the ramp aπangement since tolerance control is exclusively based on the dimensions of the base plate and ramp aπangement. No ramp aUgnment instaUation procedure is needed.

1(211 Turning to Figure 18, ramp anangement 1220 is shown rotated into its aforedescribed locked position. Actuator arm 344 is shown in its parked position having a load tip 1290 located approximately along axis of rotation 1282. Ramp 1254 is designed having an intended contact point 1292 at which load tip 1290 is intended to initiaUy contact the ramp when moving to the parked position and intended to lose contact when moving away from the parked position. Intended contact point 1292 is shown aπanged along a centerline 1294 of ramp 1254. Tolerances with respect to movement of an actual contact point along the sloped surface of ramp 1254 towards and away from axis 1282 are controUed directly by the aforementioned first and second- control tolerances that are described with respect to Figure 20 above. Rotational tolerance of ramp aπangement 1220 about axis 1282, however, primarily controls side to side positioning of the actual contact point on the ramp in a directiori that is 'normal to centerline 1294 in the plane of the ramp surface. An exaggerated angle of rotation, θ, iUustrates an arbitrary rotation of the ramp aπangement about axis 1282 such that actual contact point 1296 is at the edge of the ramp surface. In this regard, because the contemplated rotational movement of the actual contact point is in a direction that is at least generaUy normal to centerline 1294, the rotational tolerance for the actual contact point about axis 1282 is responsive to the cosine of θ. This aπangement is considered as being highly advantageous in providing for a third controlled tolerance of the actual contact point that is dramatically reduced for a given rotational positioning eπor. For example, a large value of rotational positioning eπor, such as 15 degrees, yields a positional eπor of only 0.034 multiplied by the radial distance between the target point and axis 1282.

1(212 Having described the floating ramp embodiment of the present invention in detail, it is worthwhile to now briefly consider the prior art. In this regard, AppUcants are unaware of any similar ramp type structure. For example, the aforedescribed Morehouse patent describes a ramp that is fixedly, directly attached to the housing. It is submitted that prior art ramp aπangements, as exempUfied by Morehouse, are directly and rigidly attached to an associated base plate as a result of a perception that such an attachment provides the only suitable mechanism for the required tolerance control. Particularly in view of such a perception, it is readily apparent that the original implementation of the floating ramp anangement of the present invention, as weU as the recognition of its attendant advantages, is neither trivial nor obvious.

1(213 Attention is now directed to Figure 22 which Ulusttates Storage Element 320 electrically connected to a host computer or device 300' in accordance with the present invention. In particular, this embodiment of the host device includes a processing anangement 302' that is connected with a transitional IC 1300, which may be refened to hereinafter as a TIC. Processing aπangement 302' may be connected to TIC 1300 using any suitable interface 1302 such as, for example, a CompactFlash interface. It is to be understood that any implementation described as utilizing a TIC is functionaUy equivalent to a host processing aπangement which is configured for executing the native code of the Storage Element. The TIC, in essence, becomes an integral part of the host processing aπangement. In the present example, a modified form of the CompactFlash interface is used between the Storage Element and TIC, as described in detail below. The TIC, in turn, is connected to interface 322 of the Storage Element. In one embodiment, free end 330a of a flexible cable provides for connection to connector a 332 (see also Figure 2) to place TIC 1300 in electrical data communication with Storage Element interface 322, although any suitable connection scheme may be used.

1(214 StiU referring to Figure 22, Storage Element 320 includes a read write or channel section 500' and a pre-amp section 502', either of which may be provided as discrete integrated circuits. Read write section 500' serves to transfer data to and from transducers or heads 352 in cooperation with preamp section 502'. Storage Element 320 further includes a highly advantageous servo/control IC 1304 which is made up of a management section 1306 and a servo section 1308. Servo section 1308 is in electrical coinmunication with VCM 346 (see also Figure 4) and spindle motor 342 in order to actuate both of these motors in a way that is known in the art. In this regard, it is appropriate to note that read/write IC 500' and preamp IC 502' may comprise conventional ICs. Moreover, servo section 1308 of IC 1304 may, Ukewise, be provided in the form of a separate, conventional servo IC. It is important to understand that each of these ICs or functional blocks is configured for sending and receiving control-related data using a dedicated serial interface such as those serial interfaces shown and described above with regard to Figure 21. In the present example, servo section 1308 is controlled using a serial servo interface 1310, read write (R/W) IC 500' is controUed using a serial R/W interface 1312 and preamp IC 502' is controUed using a serial preamp interface 1314. Thus, a pluraUty of device serial interfaces require bi-directional serial data control. To that end, management section 1306 includes a highly advantageous serial data router 1320 which may selectively connect with any of the serial interfaces for switching multiple conductor connections between the various device serial interfaces 1310, 1312 and 1314. In the instance of a device serial interface, these conductors generaUy include at least a serial clock line, an enable line and a serial data line (see Figure 21). Serial router 1320 is switched under control of a control block 1322, as wUl be further described. In this regard, it should be appreciated that serial router 1320 and control block 1322 have been diagrammatically Ulusfrated since there are essentiaUy any number of functional equivalents. A specific implementation wUl be described at an appropriate point below.

1(215 Turning to Figure 23a in conjunction with Figure 22, attention is now directed to interface 322 which electrically connects Storage Element 320 with host device 300' via TIC 1300. Figure 23a diagrammaticaUy Ulusttates free end 330a of Storage Element flexible cable 330. Power and ground lines are not shown, but are understood to form a portion of the interface. Initially, it is noted that the present invention provides a "pin-flip" feature whereby the order of the output signals in the interface can readily be reversed, as described in detaU at an appropriate point below. The signals within the interface aπangement of the present invention are divided among three functional groups including a set of control lines 1340, a serial gateway 1350 and a data gateway 1360. Data gateway 1360 is connected by management section 1306 to R W section 500'. In the present example, control lines 1340 include a read gate/write gate (RG/WG) line 1362, a servo gate (SG) line 1364 and a servo sync mark enor (SSM/ERR) line 1366. WhUe the individual signals which make up the composite signals on RG/WG line 1362 and SSM/ERR are not new, in and of themselves, it is submitted that multiplexing read gate with write gate and servo sync mark with an eπor signal has not been seen in the prior art and is highly advantageous at least for the reasons to be described below. Moreover, after having accompUshed this multiplexed configuration, it is clear to Applicants that this task is neither trivial nor obvious. Control block 1322 selectively interfaces control Une group 1340, via interconnections 1367, indicated as an interface line, to a discrete read gate (RG) line, a discrete write gate (WG) line, a delayed write gate line (DWG), a discrete servo sync mark (SSM) line and a discrete eπor (ERR) line, as wiU be described in detail at appropriate points below with reference to subsequent ones of the figures.

1(216 Continuing with a description of Figures 22 and 23a, with particular emphasis on the component signals of interface 322, serial gateway 1350 includes a serial data line (SDATA) 1370 and a serial clock (CLK.) 1372. Note that serial gateway 1350 does not include a serial enable line. It is important to understand that the SDATA signal travels bi- directionally between serial router 1320 and TIC 1300, carrying aU serial control-related data which is required to support the serial ports of aU of the device sections in the Storage Element. In the present example, these device serial interface ports coπespond to servo section 1308, preamp section 502' and read/write section 500', although other specific implementations may be provided so as to serve fewer or greater numbers of device serial interfaces. As wiU be further described below, control block 1322, in cooperation with an operations definitions section 1380, provides for highly advantageous customization of the operation of serial router 1320 for any particular device serial interface that is employed. In this regard, it is important to remember that preamp section 502' and read/write section 500' comprise essentiaUy off-the-shelf ICs. Moreover, servo section 1308 essentially comprises an off-the-shelf part including its standard serial port, but for its co-integratibn with management section 1306, which is not a requirement.

K217 Data gateway 1360 includes a reference clock (REFCLOCK) line 1382 for use as a time base at least in writing data. An NRZDC line 1384 carries an NRZ data clock signal which is produced by a phase locked loop in Read Write section 500". At least one data line 1386 is provided for use in bi-directional transfer of data between media disk 340 (Figure 3) and host device 300'. In the present example, eight pataUel NRZ data lines have been employed, which may be individuaUy indicated using the nomenclature NRZ <x>, where the value of x ranges from 0-7. Any suitable number of data lines may be utilized, including a single one, in order to implement the highly advantageous interface aπangement of the present invention. As an example, the number of NRZ lines may be selected based on the capabUities of a particular read/write IC (i.e., channel IC) that is to be used. Further, the use of differential NRZ lines is contemplated in a way which provides for reducing radiated emissions. In such an implementation, a Read/Write IC may be configured for using two conductors for serial data transfer in a single bit differential interface configuration.

1(218 In one modification, REFCLK 1382 may be eliminated from data gateway 1360 so as to reduce the size of interface 322 by one Une. In place of REFCLK, serial clock (CLK) signal 1372 may be used by Read/Write section 500'. In order to provide for this modification, the CLK signal must be sufficiently stable and sufficiently jitter-free for use by the Read/Write section. In this regard, it is noted that many host devices, particularly portable devices, include a USB port having a USB clock signal that is generaUy crystal controlled. It has been found that this USB clock signal is suited to the contemplated purpose. Accordingly, CLK signal 1372 serves as a timebase reference for the operation of the Storage Element, including write operations. A timebase reference clock may be refened to hereinafter as SE Clock.

1(219 Turning to Figure 23b, in another modification, a highly advantageous differential-like clock signal may be provided, for example, serving as the timebase reference just described. To that end, portions of Storage Element 320 and TIC 1300 are iUusttated. SE Clock is typically generated on the host side. In the present figure, SE Clock is placed directly onto a first line 1372a whUe being provided to an inverter/driver 1388. The latter drives a second line 1372b such that complementary signals 1389a and 1389b are present on lines 1372a and 1372b, respectively. Lines 1372 should be elecfromagneticaUy coupled as closely as possible, at least from a practical standpoint, so as to eliminate electromagnetic radiation of the clock signal. For example, referring to Figure 23a, Serial Clock line 1372 can be replaced by lines 1372a and 1372b directly adjacent to one another. One of the lines received by operational section 1306 in the Storage' Element, line 1372a in this example, serves as the timebase reference. The other line, 1372b, is unused. It is recognized that a true differential drive aπangement has not been provided. In this regard, however, such an anangement is relatively demanding in terms of implementation and cost, requiring a differential amplifier and typicaUy requires a dual-ended power supply. The differential-like aπangement practiced by the present invention is submitted to provide a majority of the benefits of a true differential-drive clock configuration with a fraction of its cost and complexity. It should be appreciated that a differential-like drive may be used with any of the NRZ lines and is certainly contemplated for use in providing a single-bit NRZ implementation.

1(220 Having described the components and architecture which provide for implementation of the Storage Element serial router of the present invention, it is worfhwhUe to now discuss certain aspects of its operation. In particular, a highly advantageous serial protocol is employed for the bi-directional transfer of serial control-related data on serial gateway 1350. To that end, a system-level device ΪD is appUed to each device within the Storage Element having an associated serial port. In the present example, as wiU be further described, a two-bit device ID is utilized. While device ID's may be appUed in a flexible manner, it may be advantageous to assign a fixed device ID to one or more devices in order to avoid the need for dedicated address pins on an IC which embodies operational section 1306. Alternatively, dedicated pins may be provided for use in setting device addresses. For example, a pair of pins would be provided for each device in order to implement a two bit addressing scheme. The pins are then set to high and low states so as to uniquely identify each device. When control block 1322 receives an address responsive to an incoming command, the control block compares the address specified by the command to the address specified by the pair of pins associated with each device, until the coπect device is found. An interaction is then initiated with that device. As another example, device addresses may be specified using register locations in operations definitions section 1380 for use by control block 1322.

1(221 During operation, TIC 1300 receives commands from host processing anangement 302'. These commands are generally in the form of a read command or a write command. Specific examples of commands include data commands, non-data commands and vendor unique commands. One example of a vendor unique command would be a command that reads the internal temperature of the Storage Element- one form of a read command. The TIC then processes each command in accordance with the serial protocol of interface 322. In particular, the TIC applies the device ID to the command. Additionally, information is added including a Mark bit, which initiates the transaction. The Mark bit is followed by the device ID which is then foUowed by a bit which indicates whether the transaction is a read or a write. Subsequent to these items is a Packet Field, all of which wUl be further described. The TIC then transfers these commands to the Storage Element. Upon receipt by the Storage Element, control block 1322 recognizes the device ID for use in setting serial router 1320 to appropriately route the command to a selected one of the devices. The serial router, however, does not send the system-level device ID to the selected device, since such an identification would not be recognized by the selected device. Again, it is emphasized that each serial device can be an unaltered part, continuing to be responsive only to its particular customized command set. Not only does the serial router remove the device ID prior to sending a command to a targeted device, but it further cooperates with control block 1322 and operation definitions section 1380 so as to implement the customized command set for each device. From the viewpoint of each device, at least insofar as its serial interface is concerned, it appears to be connected to a standard confroUer using a dedicated serial port. In accordance with the present invention, however, control of aU of the device serial ports is being performed by the TTC. Further details with regard to the way in which the command set of each device is implemented will be provided immediately hereinafter.

1(222 Referring to Figure 22, aU data, in the form of commands, traveling on serial gateway 1350 outgoing from TIC 1300 is associated with system-level device ID's, which may be refened to as Device Select in subsequent discussions. The device ID is then recognized by control block 1322 in order to configure serial router 1320. In the instance of a write command, the device ID is provided along with an address field and a data field. These latter two fields include information that is intended for direct receipt by the selected/targeted device. For example, the address field is used by the targeted device to identify a particular internal register, whUe the data field comprises the data that is to be written into that register. Because a write command may vary from device to device within the Storage Element, in terms of both length of the address field and length of the data field, operation definitions section 1380 serves in a highly advantageous way, by storing the particular address¹ field and data field lengths that are associated with an access (in this case, the write command) for each targetable device. Accordingly, the write command can be customized using operation definitions section 1380, in view of a particular device that is to be written to. Since data travels from the host device to ihe Storage Element during a write command, upon verifying that the conect data field length has been transfeπed, control block 1332 may release the serial gateway for another transaction. Until that time, however, the serial gateway is "captured" by the cuπent data interchange transaction, as wUl be further described with regard to a read transaction. In subsequent discussions, the address field and data field, for any command, may be refened to coUectively as the Packet Field while the address and data fields may be refened to individually as Header and Data portions of the Packet Field, respectively. During a write command, the entire Packet Field is sent to the targeted device. For purposes of defining a customized write command, operation definitions section 1380 includes Packet Field Duration and Header Length Registers for each targetable device. It should be appreciated that there may be address information within the Header that is internally used by a targeted device, for exaπφle, to identify a register location. In this regard, control block 1322 is under no requirement to identify or even be aware of such address information. The need for such awareness is eliminated by the customized definitions that are present in operations definitions section 1380. Once the control block determines the length of the Header, the control block need only count the number of bits that are specified for transfer. The specific purpose of those bits is iπelevant, insofar as control block 1322 directing the setting of router section 1320 to the targeted device. Similarly, if one device requires a Header having an initial read write bit, while another, functionaUy equivalent device is identical in aU respects, but for the fact that its Header requires a terminating read/write bit, either device is readily accommodated through the capability to specify different customized command sets for either device.

1(223 With regard to the implementation of read commands on serial gateway 1350, the command is issued in the same manner as a write command, including a device ID for the targeted device. Moreover, the address and data fields have lengths that are defined in operation definitions section 1380 to customize the command for a particular device. In a read command, however, serial control-related data traveling from Storage Element 320 to host device 300' (that is, the data that is actuaUy read) does not carry a device ED. The present invention recognizes that all of the serial control- related data traveling in this direction is responsive to read commands that are issued by the host device. A read command, like a write command, captures serial gateway 1350 until that command has been completed. In the case of a read command, the anticipated response of the targeted device is defined within operation definitions section 1380, using Packet Field Duration and Header Length Registers for each selectable device, such that the control block and serial router wait or listen for the response of a specified length from the targeted device before releasing the serial gateway to a subsequent command initiated transaction. During a read command, only the Header portion of the Packet Field is sent to the targeted device. The targeted device then fills in the Data portion, as its response. That is, the response to a read command returns an identical Header portion with the Data portion being the read response.

1(224 Refeπing to Figure 24 in conjunction with Figures 22 and 23a, as mentioned above, one of the signals within control line group 1340 comprises a composite RG/WG signal which is thought to be novel, in and by itself. Figure 24 illustrates one embodiment for distinguishing within the Storage Element whether Read Gate or Write Gate is being asserted and for routing a discrete signal to R W section 500', n the instance of RG, and for routing a discrete WG signal to R W section 500', while the DWG signal is provided to preamp section 502' responsive to assertion of WG by RG/WG Une 1362. This function is accompUshed by using a 1x2 demultiplexer 1390 having a selection Une 1392 which is responsive to bit eleven (bl 1) of a gate control register 1394 which forms one portion of confrol block 1322. It is noted that all of the registers within management section 1306 are subject to reads and writes using the addressing protocol described herein, having the device ID set to the fixed device ID of servo section 1308, since these sections are co- integrated. The delayed write gate DWG Une is produced using a programmable delay 1396 which may be set to zero (no delay) or to provide a predetermined delay value in relation to WG, based on a specified clock signal, as described in further detail below.

1(225 Turning to Figure 25 in conjunction with Figures 22 and 23a, another one of the signals within confrol line group 1340 comprises a composite SMM/ERR signal 1366, which, like the RG/WG signal, is submitted to be novel, in and by itself. Figure 25 Ulusfrates one possible embodiment for generating the SMM/ERR signal within control block 1322. Discrete SSM and ERR signals are seen to flow from Read Write section to operations section 1306, which are used to make up the composite signal. It is submitted that this combination has not been seen in the prior art at least for the reason that these two signals are not necessarily mutuaUy exclusive. That is, whUe SSM is always asserted responsive to servo data (during assertion of SG), ERR, as implemented by the present invention, can nonetheless occur during SSM. The present invention recognizes, however, that, when ERR does occur during SSM, a certain level of latency is generaUy acceptable in servicing the ERR signal. This latency provides for the combination of these discrete signals into one composite signal on interface 322. In this way, ERR can be asserted mutually exclusive to SSM as part of the composite signal. As inputs for producing ERR in Figure 25, Read Write section 500' provides a RW_ERR signal on a Une 1400, whUe a Servo Eπor signal is provided from servo section 1308 on a line 1402. In this regard, it is to be understood that many different forms of eπor signals may be generated, in particular, by the servo section. Accordingly, servo eπor line 1402 is considered to represent aU of these potential signals, whether multiplexed or provided using individual conductors. As examples, servo eπor signals may include POK (Power OK) false, detection of loss of clock, an excessive shock indication, a preamp fault and thermal asperity detection, as further described below. It is noted that the POK and excessive shock indication eπors are particularly representative of situations in which the discrete ERR signal may be asserted during assertion of the discrete SSM signal, since associated events which trigger these eπors are completely independent of SSM. Accordingly, the present invention receives aU of these various eπor signals using a logic block 1404 in order to provide a great degree of flexibUity with respect to which eπor signals are reUed on as input. To that end, an eπor control register 1406 is used to enable no less than twelve different eπor modes of logic block 1404. The output of logic block 1404 comprises the discrete ERR signal which is passed to one input of a 2x1 multiplexer 1410. The other input of multiplexer 1410 is the discrete SSM signal, as produced in a conventional manner by Read/Write section 500'. The servo gate signal, SG 1364, from the host device, or TIC therein, serves as a select enable signal for multiplexer 1410. The output of multiplexer 1410 is the composite SSM/ERR signal 1366 which is fed directly into control line group 1340 of interface 322. When multiple eπor modes are enabled, a query is generated by TIC 1300 responsive to assertion of ERR. This query generaUy reads register locations that are associated with the particular eπor mode which originated the assertion as defined in operations definitions section 1380.

1(226 StiU considering the treatment of eπor modes, the present invention provides for freatment of different modes with different latency. As an example, the detection of a thermal asperity is a time sensitive event in order to ascertain the particular location on the media disk at which the thermal asperity was produced. Accordingly, such a signal may be immediately directed, in real time, to associated eπor coπecting logic within TIC 1300.

1(227 Refeπing to Figure 26, a flow diagram, generally indicated by the reference number 1440, iUusttates the highly advantageous serial protocol of the present invention for purposes of controlling serial router 1320 (Figure 22) as interfaced to TIC 1300 through Serial Gateway 1350. The method is initiated with a power-on reset at step 1442. Execution then moves to step 1444 which serves to reset control logic that is related to the Serial Gateway. At this point serial router 1320 listens for the aforementioned Mark bit (as a data high or "1" bit) to be asserted by looping through step 1446. Once the Mark bit is detected, operation moves to step 1448 wherein the system defines the detected bit as a Mark bit. Consequently, step 1450 decodes the two bits which immediately foUow the Mark bit as device ID bits. Step 1452 then acts on the device ID to set up the serial router via confrol block 1322 (Figure 22) to enable a channel or data path for routing data therealong, accompanied by setting drivers along this data path for transferring data from the TIC to a targeted device, consistent with the device ID.

1(228 In step 1454, the next bit to be decoded comprises the Read/Write bit wherein a high or "1" data state arbitrarily designates a read command. In this event, execution moves to step 1456 wherein the command is defined as a read transfer. Step 1458 then transfers the number of bits which comprise the Header portion of the Packet Field, consistent with appropriate Packet Field Duration and Header Length Registers for the targeted device. Once the Header bits are transfeπed, step 1460 reverses the data flow direction of the defined channel by reversing aU driver circuitry therein for moving data from the targeted device to TIC 1300. Step 1462 then counts the appropriate number of bits for the Data portion (this number is equal to the Packet Field Duration minus the Header Length Register). Following step 1462, the data flow direction is again reversed, by step 1464, to its original direction from the TIC to the Storage Element in anticipation of the next command. Again, it is emphasized that the specific internal use of the counted bits by the targeted device is immaterial. What is important is that the command length is properly defined in terms of the length of its Header portion and Data portion such that coπect numbers of bits are counted in both directions.

1(229 Returning again to step 1454, if the command is determined to be a write command, the command is defined as such at step 1468. Step 1470 then counts a specified number of bits which coπesponds to fhat number of bits recorded in an appropriate Packet Field Duration register. That is, the Header portion and Data portion are both fransfeπed, as described above. Bit counting is somewhat simplified, compared to a read transaction, since die write transfer flows in one data direction.

1(230 Refeπing to Figure 27, one embodiment of the present invention, generally indicated by the reference number 1500, including Storage Element 320 and TIC 1300, interfaced with a host processing anangement (or a host device, where a TIC is not used), may utilize NRZ lines within interface 322 in a highly advantageous way. Specifically, it is recognized that one or more of NRZ lines 1386 may be used for alternative purposes at times when data transfers are precluded. As an example, such times include a start-up time period of the Storage Element, at least until its media disk is up to speed and the actuator is ready to access the media disk. Figure 27 illustrates a configuration for using NRZ <0>, during this start-up period for the purpose of transferring a Zero Crossing (Zero-Xing or ZCross) signal that is produced by servo section 1308 (Figure 22) responsive to spinning of spindle motor 342.

1(231 Refeπing again to Figure 21, it should be appreciated that the ZCross signal is utilized in the spindle motor control system as follows: Disk drives typϊcaUy employ brushless spindle motors to minimize particles/contamination (which would be caused by brush designs). Brushless motors require that the driver circuitry (typically implemented in a single IC) switch driving cuπents through the motor coils in a manner that produces torque in the desired direction of rotation. The cuπent must be switched synchronously with the rotation of the spin motor and, therefore, some form of rotational position sensing must be employed on the spindle motor. One weU-known technology consists of BEMF (Back EMF) detection circuitry in the driver circuitry which senses BEMF zero-crossings in an un-driven phase of the motor, producing the ZCross signal responsive thereto. However, the BEMF zero-crossings do not represent an optimum rotational position for switching the motor coil-driving cuπent in terms of providing maximum torque and electrical efficiency. In order to obtain optimum efficiency, cuπent switching must take place at some delayed time from the BEMF zero-crossing detect. The amount of delay depends on how fast the motor is spinning and, thus, during an initial spin-up operation, where the motor speed is constantly increasing, the delay must be changed as the speed increases. Calculation and adjustment of this delay is typically implemented, in a conventional hard drive, as an algorithm in the disk drive controUer (item 64 in Figure 21), and this is why the ZCross signal is generally connected/provided between the Spin/Servo Driver and the controller: it provides the input to the delay calculation algorithm. Another well-known functional use for the ZCross signal resides in sensing the rotational speed of the spindle motor: The speed is directly proportional to the frequency of the ZCross signal. The controUer calculates (he rotational spin speed and uses the result to calculate the appropriate delay mentioned above. Details of how to calculate the appropriate delay are weU known. Once the spin motor has reached the target rotational speed, this speed measurement is also used in well known methods to control the speed to within acceptable tolerance.

1(232 Turning again to Figure 27, system 1500 is exeπφlary of one embodiment, for using NRZ <0> (as part of interface 322), whereby this data gateway line can be used for other purposes when NRZ data transfer is not required. In particular, the ZCross signal is provided on a line 1502 to a tri-state driver 1504. An enable input 1506 of the tri-state driver is controUed responsive to a register setting. In the present example, bit 5 of a General Purpose VO register 1508 is used, as wiU be further described. The output of tri-state driver 1504 is connected to the NRZ <0> line in operations section 1306. In Read Write section 500', the NRZ <0> line is connected to a tri-state bi-directional driver (or receiver/driver) 1510 which is indicated within a dashed line. An enable input 1512 of bi-directional driver 1510 is connected to the discrete RG signal. In TIC 1300, an opposing end of NRZ <0> is connected to another bi-directional driver 1514. TIC 1300 includes a Digital Signal Processing Aπangement (DSP) 1516, which is programmed to control the Storage Element responsive to Host Processing Aπangement 302' (Figure 22). DSP 1516, as one of its functions, controls a Multiplexer (MUX) Logic section 1518 which is used to implement control of an enable line 1520 that is connected to bi-directional driver 1514. MUX Logic section 1518 also controls an enable line 1522 of a bi-directional multiplexer 1524. It should be appreciated that the detafled schematic presented here should be considered as a functional, diagrammatic iUustration for which there are any number of alternative equivalents that could be realized by one having ordinary skUl in the art in view of this overaU disclosure. As wiU be further described, DSP aπangement 1516 is able to selectively connect one of internal NRZ <0> Data and ZCross to the NRZ <0> line. In this regard, NRZ <0> Data is bi-directional while Zcross is unidirectional, originating in servo section 1308 (Figure 22).

233 Referring to Figure 28, system 1500 is iUusttated with respect to using another NRZ line, within the data gateway of interface 322 for an alternative purpose, at a time when the transfer of NRZ data is not required. In this regard, a commutation signal, that is designated as FCOM, is produced by DSP anangement 1516 in TIC 1300. The FCOM signal is a unidirectional digital logic signal that travels from the Host side to Spin/Servo section 1308. This signal is typical of weU-known spindle motor control systems in disk drives and is utilized to command Spin/Servo section 1308 to switch cuπents in the spindle motor coUs. Each pulse in the FCOM signal (or in alternate implementations, each edge) indicates that the Spin Servo Driver should switch cuπent to the next valid state. Here, the term "state" refers to a particular combination of cuπents through the spindle motor coils, as is known in the art. WhUe the present invention can implement transfer of the FCOM signal in a number of ways such as, for example, by using serial gateway 1350 of Figure 22, one highly advantageous implementation resides in using a selected NRZ line, in this instance NRZ <1>, to transfer FCOM at times when NRZ<1> is not in use; that is, when normal data transfers are invoked which utilize aU eight of the NRZ lines in concert.

1(234 FCOM is generated, in the present implementation, by DSP aπangement 1516 and is provided to a bidirectional multiplexer 1530. At the same time, multiplexer 1530 receives internal NRZ <1> data. An enable line 1532 of multiplexer 1530 is controUed by the DSP aπangement, for selection of one of NRZ data <1> and FCOM, via MUX Logic section 1518. The latter is also used by the DSP aπangement to control an enable fine 1534 of a bi-directional tri- state driver 1536, shown within a dashed line. Accordingly, the NRZ data <1> signal or the FCOM signal can be placed on the NRZ <1> line of Data Gateway 1360. The NRZ <1> line is routed to Read/Write section 500' as weU as to Control block 1322, in the Storage Element. In particular, a tri-state multiplexer 1540 receives the NRZ <l>/FCOM line as one. of its inputs. In an actual implementation, the FCOM input to multiplexer 1540 comprises a GPIO (General Purpose Input Output) pin on Servo/Control IC 1304, as will be further described. Two remaining inputs are provided to multiplexer 1540 on lines 1541 and 1542 comprising an automatic mode commutation input and a manual mode commutation input. DetaUs with respect to these latter two signals wiU be provided below. For the moment, it is sufficient to note that the multiplexer is used to select these various commutation signals during a start-up or spin-up procedure. To that end, an enable input 1543 of the tri-state driver is controlled responsive to register bits 6 and 7 of a Spin Configuration register 1544. The output of tri-state multiplexer 1540 comprises a commutation signal (COM SIGNAL) that is connected to circuitry (not shown) in servo section 1308. In Read/Write section 500', NRZ <1> Data is interfaced to the NRZ <1> Une using a tri-state bi-directional driver 1545, shown within a dashed line.

1(235 Having provided details with regard to specific design configurations for permitting the NRZ <0> Une and the NRZ <1> line to carry ZCross and FCOM, respectively, at times when these lines are not in use as part of the overall Data Gateway, specific operational details wiU now be provided with respect to one highly advantageous manner in which these design configurations are employed, during startup of the Storage Element.

236 InitiaUy referring to Figure 29, a system 1600 is shown, configured in accordance with the present invention, including a host system 1602 connected with Storage Element 320. The system is shown in the form of a functionally partitioned block diagram, including only those portions of the host system and Storage Element that are pertinent to the present discussion, for purposes of clarity. In the present example, the operational section (item 1306, Figure 22) and servo section (item 1308, Figure 22) of the Storage Element are shown co-integrated, in the form of a Spin Servo IC 1604. The latter includes a Serial Port Logic section 1606 interfaced with a Spin Control Logic section 1608, and a Read Channel IC 1610. Host system 1602 includes a Controller/Processor IC 1614, which comprises an overall processing aπangement for confrolling the Storage Element as well as aU other host functions; a TIC is not used in this example. Controller Processor IC 1614 includes Processor Logic 1616, comprising a microprocessor or Digital Signal Processor (DSP) connected to an internal control bus 1618. The latter is, in turn, interfaced to Data Path Logic 1620, Serial Port Logic 1622, Spin Control Logic 1624 and Multiplexing Logic 1626. Discrete ZCross and FCOM signal lines extend between Multiplexing Logic 1626 and Spin Control Logic 1624. Data Path Logic 1620 handles data fransfers between the host and Storage Element during read and write operations. Spin Confrol Logic 1622 assists Processor 1616 with respect to the ZCross and FCOM signals. Multiplexing Logic 1626 is used to confrol signal routing between the Data Gateway NRZ <0,1> signals and the described internal connections (Figures 27 and 28) within the Controller/Processor IC.

1(237 Serial Port Logic 1622, within host 1602, cooperates with Serial Port Logic 1606, in the Storage Element, to implement a Serial Port Logic System which utilizes the highly advantageous serial protocol of the present invention, as described herein. Spin Control Logic 1608, within the Storage Element, is used by Processor Logic 1616, through the serial protocol and Serial Port Logic of the present invention, in confrolling ZCross and FCOM. It is noted that implementations have been described above with respect to spin control and multiplexing logic, within the Storage Element, associated with each of ZCross and FCOM (see, for example, Figures 27 and 28).

238 Still referring to Figure 29, as also described with respect to other figures, NRZ <0-7> extend between host system 1602 and Storage Element 320. In this regard, it is emphasized that the NRZ <0,1> lines can alternatively carry the ZCross and FCOM signals, respectively, notwithstanding their nominal NRZ designations within Data Gateway 1360. That is, the shared ZCross and NRZ <0> signals/functions are multiplexed as a single interface signal which retains the name NRZ <0> in the Storage Element design (the choice of naming convention is unimportant). Similarly, the shared FCOM and NRZ <1> signals/functions are multiplexed as a single interface signal which retains the name NRZ <1>. Within Controller/Processor IC 1614, NRZ <2-7> are routed directly to Data Path Logic 1620, as part of the Data Gateway from Storage Element 320. Dedicated NRZ <0,1> lines 1630 are routed, apart from the Data Gateway, from Data Path Logic 1620 to Multiplexing Logic 1626. The NRZ <0>/ZCross line and die NRZ <l>/FCOM line emerge from Multiplexing Logic 1626 on a data path 1632 which then merges with NRZ <2-7> enroute to the Storage Element. In Storage Element 320, it can be observed that the NRZ <0,1> lines are provided to Spin/Servo IC 1604 for purposes of carrying ZCross and FCOM. It is noted that the six other NRZ signals are not shared with any other signals/functions at present, but in accordance with the present invention, they could be shared, for example, to accomplish a further reduction in the number of interface Unes present between the Storage Element and Host device (or TIC).

1(239 Refeπing to Figure 30, in conjunction with Figure 29, a flow diagram, generally indicated by the reference number 1700 Ulusfrates a highly advantageous startup procedure which utilizes the dual purpose capabiUties of the NRZ <0> and NRZ <1> lines. Beginning at step 1702 Processor Logic 1616 accesses control registers in Spin Confrol Logic 1624 so that ZCross can be used as an input to certain control algorithms via an interrupt to Processor Logic 161 in a manner that is known in the art. In this regard, it is noted that the ZCross signal is needed in order to begin and complete a spin-up operation (bringing the rotational speed from a starting condition of zero up to a desired/target speed). The rotational position must be sensed in real-time in order to conectly control/switch the cuπent through the brushless spindle motor coils, one alternative resides in the use of older and more expensive technology which employs separate positional sensor devices within the spindle motor.

f240 In step 1704, Processor Logic 1616 accesses control registers in Multiplexing Logic 1626 to disconnect the internal, dedicated NRZ <0> and NRZ <1> signals from the external NRZ <0> and NRZ <1> Data Gateway signals, and to connect the internal ZCROSS and FCOM signals within Controller/Processor IC 1614 to NRZ <0> and NRZ <1>, respectively.

241 Processor Logic 1616 accesses confrol registers in Read Channel IC 1610 during step 1706, utilizing Serial Port Logic 1622 and 1606 on the Host and Storage Element sides, respectively, to place all of the Read Channel NRZ lines (NRZ-0 through NRZ-7) in a tri-state mode (no connection to internal Read Channel Circuitry) within Read Channel 1610. It is noted that on some read channels, tri-state may be the default operating condition for these signals when data transfers are not active and, thus, for these particular read channels, no additional access to any control registers in the Read Channel IC is required for this step.

1(242 Step 1708 causes Processor Logic 1616 to access control registers in Spin Servo IC 1604, utilizing the Host side and Storage Element side Serial Port Logic, to connect the ZCross and FCOM signals to NRZ <0> and NRZ <1>, respectively, within the Spin/Servo IC. Further, multiplexer 1540 in Figure 28, is set to select FCOM using register 1544.

1(243 At step 1710, Processor Logic 1610 executes a procedure, that is known in the art, to start the spindle motor spinning utilizing the FCOM signal. In accordance with the present invention, this procedure is implemented by sending FCOM on the NRZ <1> interface line. In an alternative implementation, FCOM can be provided through the Serial Port logic on the Host side and in the Storage Element.

1(244 In step 1712, at a point in the procedure initiated by step 1710, Processor Logic 1616 begins to utilize the ZCross signal (which originates in the Spin Servo IC) for purposes which are known in the art including: (1) Measurement of rotational position of the spindle motor by using pulses or edges on the ZCross signal and providing this as an input to a delay procedure. This delay procedure results in subsequently producing a pulse or edge on the FCOM signal which then is used by the Spin/Servo IC to change the state of the spin cuπent through the various spindle motor coUs at optimum times, and (2) measurement of rotational speed by measuring the frequency of the pulses or edges on the ZCROSS signal.

245 The use of ZCross and FCOM signals in step 17l2 is repeated, as described above, until the spin speed measurement indicates the speed has reached a value near to the final/target operating spin speed (for example: 98% of final/target speed) so as to satisfy the test of step 1714.

1(246 At this point, step 1716 is entered in which Processor Logic 1616, via a Serial Port Logic operation, enables circuitry internal to the Spin/Servo IC which utilizes the ZCross signal and a constant delay circuit to change the state of the spin cuπent through the various spindle motor coUs at optimum times. It should be appreciated that, once the spindle motor has reached target operating speed, there is no longer a need to recalculate or adjust the delay time based on the changing time between BEMF zero cross detections (on the ZCross signal) for switching the cuπent through the motor coils. At the same time, the FCOM signal'is no longer used as an input for these state changes by the Spin/Servo IC. That is, these state changes become automatic within the Spin/Servo IC and the FCOM function is no longer required such that confrol of the spindle motor can be more optimaUy shifted to a programmable fixed-delay circuit which may be refened to as an automatic mode. Accordingly, register 1544 of Figure 28 is set to select the automatic commutation signal on Une 1541. While the prior art implements this programmable fixed-delay in a conventional confrol IC such as ControUer IC 64 of Figure 21, the present invention advantageously implements the programmable fixed-delay function in Spin/Servo Driver IC 1604.

1(247 In step 1718, the Processor Logic continues using the ZCROSS signal to test spin speed. This measurement provides feedback to a spin speed feedback control system, in a way that is known in the art, to achieve and maintain the final target operating rotational speed. Once the measured spin speed meets some pre-determined tolerance requirements, operation passes to step 1720.

1(248 Step 1720 causes actuator arm 344 to position transducer aπangement 352 over media disk 340 (see Figure 3). Servo data is then read from the disk and used to initiate and, subsequently, operate the servo position control system.

1(249 Once the embedded servo position confrol system is fiiUy functional, embedded Processor Logic 1616 executes a procedure, in step 1722, which switches the spin speed measurement feedback used to control/maintain the spin speed, from using (he ZCROSS signal to using the rotational timing speed infoπnation provided by the embedded servo position control system, which may be refened to as the aforementioned manual commutation mode. In Figure 28, register 1544 is set so as to select the manual commutation signal on line 1542. Such use of the embedded servo position circuitry is known in the art.

1(250 In step 1724, Processor Logic 1616 accesses confrol registers in Spin/Servo IC 1604, utilizing the Serial Port Logic system, to tri-state the ZCross output, connected to NRZ <0>. Also, Processor 1616 accesses control registers in Multiplexing Logic 1626 to disconnect the internal ZCROSS and FCOM signals, on the Host side, from the external NRZ-0 and NRZ-1 Data Gateway Unes.

1(251 In Controller/Processor IC 1614, internal NRZ <0> and NRZ <1> signals are connected by step 1726 to the Data Gateway external NRZ <0> and NRZ <1> lines, respectively.

1(252 Step 1728 causes Processor Logic 1616 to access control registers in Read Channel IC 1610, utilizing the Serial Port Logic system, to place all of the Read Channel NRZ VOs (NRZ-0 through NRZ-7) in a normal operating mode for write and read operations. It is noted that, for some read channels, this step may not be necessary if in previous steps no special actions were required to tri-state the read channel's NRZ signals. The system is now ready for normal write or read data access using the NRZ <0> through NRZ <7> signals to transfer data.

1(253 The Spin Down Operation is an open-loop operation which does not require either the ZCROSS or FCOM signals, therefore no special manipulation of the control registers for these signals is necessary.

1(254 It is noted that the use of NRZ lines, in the described manner, is considered to be highly advantageous by providing the opportunity to transfer ZCross and FCOM in a way that avoids signal delays. Accordingly, commutation signals responsive to ZCross will be more precise, ύuring start-up, this accuracy is particularly important since the time between zero crossings changes rapidly during startup. At the same time, the number of interface lines is held to a minimum. AU of tins is in view of minimizing the number of interface lines. In and by itself, a reduced number of interface lines and associated electrical connections wiU enhance reUab ity.

255 Attention is again directed to Figure 22 for purposes of describing a highly advantageous firmware management system that is implemented in accordance with the present invention. To that end, Storage Element 320 of Figure 22 includes a static memory section 1740. In the present example, a MICROCHIP 24AA64 SEEPROM (Serial ElectricaUy Erasable Programmable Read Only Memory) is used, although it is to be understood that any suitable form of static memory device may be employed. The SEEPROM (or serial ROM) utilizes a 2-wire digital serial connection/communication scheme. Therefore, two signals are required: one signal comprises a serial PROM clock Une 1742 and the other signal comprises a serial PROM data line 1744. In an actual implementation, a pair of GPIO pins on Servo/Control IC 1304 are used to implement both signals, although any number of alternative configurations are possible. This pair of GPIO pins is under the control of host device 300' by way of TIC 1300. The GPIO pin that is used to provide serial PROM data Une 1744 can be set by TIC 1300 to serve as either a data input, for reading SEEPROM 1740, or a data output, for programming SEEPROM 1740. EssentiaUy, accesses to the SEEPROM proceed by clocking one bit at a time into or out of the SEEPROM in a weU known way that is consistent with the SEEPROM device specifications. The SEEPROM is typically programmed at the time of manufacture of Storage Element 320 using a test fixture TIC. Subsequently, during end use of the Storage Element, the SEEPROM is typically only read by host device 300' using TIC 1300. It is to be understood that one of ordinary skiU in the art may implement an unlimited number of alternative aπangements for accessing static memory section 1740, for example, based on a particular type of static memory device that is used and in view of this overaU disclosure. For this reason, aU of these alternative aπangements are considered to fall within the scope of the invention, notwithstanding the specific implementation that is described herein.

1(256 Control of SEEPROM 1740 is implemented using the highly advantageous serial protocol and Serial Gateway 1350 of the present invention so as to form an overaU bi-directional serial interface between TIC 1300 and SEEPROM 1740 via Control Block 1322. Accordingly, TIC 1300 is able to set serial PROM data line 1744 to a high or low state in an output mode and to read the serial PROM data line state in an input mode. As one alternative, it should be appreciated that TIC 1300 can access such a SEEPROM by using a device ID fhat is assigned to the SEEPROM such that the serial data relating to the SEEPROM is routed through serial router 1320.

1(257 As discussed above, the prior art is considered to be devoid of a practical approach with respect to flexible firmware development in new product lines. Certainly, the Storage Element of the present invention represents such a new product line. Furthermore, the Storage Element of the present invention, along with the way in which end user systems or host devices are implemented using it, brings rise to further considerations with respect to firmware. In particular, it is important to understand that the control functions, which implement native code control of the Storage Element, are not operating in the Storage Element, but rather, in the host device (iπespective of whether a TIC is used). Thus, firmware for confrol of the Storage Element is needed within the host device. In essence, a system implemented using the Storage Element of the present invention represents a merging of two major components: the Storage Element and a host device. Each of these major components is likely to be produced by a different entity. Since the Storage Element is cuπently a first generation product, the firmware that is provided within the host device is necessarily first generation firmware that has had no opportunity to undergo the typical generation-to-generation improvements that are available in later generation products, stemming from a particular product line, as discussed above. Given these circumstances, it would not be unreasonable to expect a significant evolution in generation-to-generation Storage Element firmware. Moreover, in the absence of specific provisions, the core firmware present in one generation of Storage Element may be incompatible with the core firmware of another generation, to an extent that a host having first generation firmware, with a later generation Storage Element instaUed therein may be unable to read magneticaUy stored data (including, perhaps, second generation firmware) from the Storage Element. As wUl be seen, the present invention is considered to have resolved these problems using a highly advantageous firmware management system that is unlike anything available heretofore.

258 Refeπing to Figure 22, TTC 1300 includes a memory aπangement 1750 having a ROM firmware section 1751 and a RAM section 1752. The former includes firmware for operating Storage Element 320 using the native code of the Storage Element. As a point of reference, previously described Figure 2 Ulusfrates code within memory aπangement 304, partitioned into device code 306 and native code 308. Since a TIC is not used in the embodiment of Figure 2, Storage Element native code 308 is executed directly by the host processing aπangement.

1(259 Turning to Figure 31 in conjunction with Figure 22, Storage Element 320 is iUusttated in relation to the highly advantageous way in which firmware updates are provided, ultimately for use by the host device. Specifically, one set of updates is indicated as a group of Pre-Patches 1756 that is made up of individual Pre-Patches A, C, F, G and J. Pre- Patches 1756 are preprogrammed in serial ROM 1740. At the same time, another set of updates is indicated as a group of Post-Patches 1758 that is made up of individual Post-Patches K, L, P, R and Z. Post-Patches are stored on disk 340 of the Storage Element at the time of manufacture. The significance of these nominal designations wiU become apparent with continuing descriptions. For the moment, it is sufficient to understand that either type of patch is intended to replace a segment of original code which forms a portion of the firmware that is incorporated in the host device. The Patches may be refened to coUectively as an update set of firmware. Moreover, this firmware system is highly flexible in providing for implementation of new functions and features which could be characterized as entirely new code segments. StiU further aspects of this flexibiUty wiU be brought to light below.

1(260 In order to use a Post-Patch, it must be read from disk 340 by the Storage Element. Pre-Patches, in contrast, are electronicaUy stored and do not require disk access. That is, Pre-Patches are read directly from serial ROM 1740 using the aforedescribed Serial Gateway, without a need for disk access. In this regard, it is important to understand that an initialization procedure is performed by the host device with the Storage Element in order to provide for disk access. Until a specific point, which may be considered as a "disk-access" boundary, is reached within the initialization procedure, the host device is completely unable to read from disk 340. It is therefore recognized that any firmware that is stored on disk 340 cannot be implemented prior to avaUabiUty of disk data; i.e., prior to die initialization procedure reaching the disk access boundary. As an example, a problem in the initial spin-up procedure of the Storage Element would require a Pre-Patch to coπect, since faUure of the spin-up means that nothing, not even Post-Patch(es) can be read from the disk. Therefore, only a Pre-Patch can be used to coπect this problem. Conversely, a problem in the power- down sequencing (powering down various ICs in the Storage Element) can be solved by a Post-Patch, because the power-down sequencing only happens after some kind of operation in the Storage Element which by default will load/activate (he Post-Patch.

1(261 While (he prior art has provided on-disk firmware, it is considered that the objectives of the prior art were to access the disk as soon as possible and to store as much firmware as possible on the disk, rather than to implement a flexible firmware management system. Unfortunately, storing as much firmware as possible on the disk results in the need for a relative large amount of not inexpensive RAM storage in the host device. The present invention avoids this need for additional RAM by patching only those portions of original ROM firmware which must be changed; there is no need to store firmware that is not to be replaced/modified on the disk. It is important to understand that some initial firmware (pre-disk-access boundary) is necessary in order just to reach the disk access boundary. The firmware management system of the present invention presents a new paradigm, in this regard, by providing a highly advantageous Pre-Patch and Post-Patch capabiUty whereby firmware needed to reach the disk access boundary can be updated, as well as post-disk-access firmware. Hence, the nomenclature "Pre-Patch" and "Post-Patch" (genericaUy refened to as "Patch" or "Patches") has been appUed with regard to firmware updates that are directed to opposite sides of the disk-access boundary.

1(262 Referring to Figures 22 and 32, attention is now directed to other aspects of the highly advantageous operation of the firmware management system of the present invention. In particular, Figure 32 Ulusfrates one implementation of this system within memory aπangement 304'. This data structure is formed using the original firmware code that is provided with the host device, along with the Pre-Patches and Post-Patches also shown in Figure 31. For purposes of simpUcity of discussion, it wiU be assumed that a set of original firmware code 1754 for the Storage Element is stored contiguously and is designated as code segments A-Z (selected ones of which are shown). Further, RAM memory section 1752, at least in part, is loaded with a Pre-Patch and Post-Patch structure 1756. It is noted that the code segment designations used in Figure 32 coπespond one-for-one with the Patch designations in both of Figures 31 and 32. Pre- Patches coπespond to segments A, C and F, whUe Post-Patches coπespond to segments G, X and Z. In the present example, the aforedescribed disk access boundary is indicated by the reference number 1760 and seen to be between Pre- Patch F and Post-Patch G. It is to be understood that the code structure that is presented is provided with the intention of faciUtating the reader's understanding and is in no way intended as being limiting. Specific detaUs with respect to how this code structure is formed wUl be provided at an appropriate point below.

If 263 Table 1 comprises another element of the firmware management system of the present invention which is refened to as a "Jump Table". This table is used along with the data structure of Figure 31 to comprise the operational firmware of the Storage Element. Prior to executing any code segment, the host device or TIC queries the Jump Table. Table 1 includes three columns which designate, in turn, each code segment, a jump location which specifies whether the code segment to be used is found in ROM firmware 1751 (original firmware) or in RAM section 1752 (a Pre-Patch or Post-Patch), and a Jump Reference Number which is not part of the firmware, but is provided for purposes of directing the reader to aπows in Figure 32 which are visual representations of each jump. TABLE 1 (JUMP TABLE FOR FIGURE 32)

(*) INDICATES CONTIGUOUS SEGMENTS IN EITHER ROM OR RAM

!f264 Execution of the overaU data structure begins by determining if there is a Patch coπesponding to code segment A. For code segment A, the Jump Table is indicated as being in RAM 1752 such that Pre-Patch A is to be executed, as indicated by a jump aπow 1770. Upon completion of Pre-Patch A, the Jump Table indicates (hat code segment B is in ROM memory 1751. Responsive thereto, a jump 1772 is performed such that code segment B is executed from original Storage Element (SE) firmware. With completion of segment B, the Jump Table requires a jump 1774 back to RAM for execution of Pre-Patch C. For segment D, execution moves back to ROM in a jump 1776. The Jump Table then indicates that segment E is in ROM and is, therefore, contiguous with ROM code segment C so (ha( no jump is required (indicated using an asterisk (*) in the Jump Table) and execution of segment E continues in ROM. Segment F, however, is indicated as being in RAM, necessitating a jump 1778. Execution continues in this manner, and wiU not be described in detail for purposes of brevity, to the completion of code segment Z responsive to Jump 1786. It is of interest to note that (he disk access boundary is essentially transparent within this operation, since all of the Patches have previously been loaded into RAM memory 1752. With completion of this procedure, the system is ready to complete any additional initialization tasks and then enter normal read and write operations. It is of further interest that Patches may be of any required length, either shorter or longer than the original code segment which they replace. Of course, Pre-Patch length may be limited by the capacity of serial ROM 1740 while Post-Patch length is unlimited from a practical standpoint due to the relatively large capacity of media disk 340.

1(265 With respec( (o dividing original firmware code info segments, there are a number of different guidelines which may be used. As one guideline, tire code may be divided in accordance with its function such that different code segments wfll vary in length.

If266 Referring again to Table 1, while these various segments may be partitioned, for patching purposes, on a functional basis, it is to be understood that this is no( a requirement As an example, a patch may replace only a small portion of an overaU code segment that performs a particular function. The Jump Table, in this regard, may be formed so as to jump from or to any addressable location within a functional segment. In this way, even one line of original code can be replaced. This replaced code segment, as part of and for purposes of the Jump Table, is indistinguishable from any other code segment in the Jump Table. This feature is highly advantageous with respect to preserving the avaflability of RAM memory in the TIC by replacing a minimal portion of ROM firmware.

1{267 Having described in detail the highly advantageous way in which the firmware management system of the present invention operates in accordance with the data structure shown in Figure 32, attention is now directed to one automated way in which this data structure can be formed in RAM emofy 1752, with reference to Figure 33. The latter is a Patch Load flow diagram that is generally indicated by the reference number 1760. The system is powered on at step 1762. At step 1762, a two-prong test is performed to determine whether serial ROM 1740 is present and, if so, whether there are Pre-Patches stored therein. In this regard, it should be appreciated that there may be startup procedure steps intervening between power on step 1762 and step 1764, however, these intervening steps are not pertinent with respect to the cuπent discussion. If it appears that the serial ROM is no( ρresen(, step 1764 may attempt any desired number of retries. As an example, ten retries may be attempted. In the event that the serial ROM is presen( and contains Pre-Patch data, execution moves to step 1766. There are any number of alternative ways in which the Pre-Patch data maybe stored in the serial ROM, however, in one implementation, all of the Pre-Patch data may be stored contiguously within the serial ROM. The actual Pre-Patch data may be preceded by a format data indication that indicates the length of the Pre- Patch data which follows. The length of the format data indication wiU depend, of course, upon the size of the serial ROM or other such non-volatile elecfronic storage device that is used. In the present example, 32 bits are used for a 64 KB serial ROM. Moreover, each Pre-Patch includes a header which identifies its location within the overall firmware sfructure. In the present example, the segment code identification serves as header infoπnation. As a further enhancement, a checksum or other such expedient, may be stored with the Pre-Patch data. Based on actual reading of the Pre-Patch data, a running checksum may be calculated for comparison with the stored checksum, in order to confirm validity of the Pre-Patch data. If the two checksums disagree, the process may return to step 1764 a predetermined number of times. If the Pre-Patoh data is ultimately determined to be invalid, step 1766 wiU be skipped.

If268 StiU describing step 1766, certain portions of the Pre-Patch data, for example, the las( Pre-Patch may be directed to initialization of the overaU Pre-Patch structure that is being implemented. In (his regard, certain housekeeping functions may be required such as, for example, updating the Jump Table and initializing firmware related RAM locations. It is noted that the initial Jump Table is created, by ROM firmware 1751, in RAM 1752 according to the unmodified structure of the original ROM firmware. In the event (ha( (he serial ROM is not present or there are no Pre- Patches therein, step 1764 causes step 1766 to be skipped, moving directly to step 1768. This automatic detection method aUows the Storage Element to be consfructed with no SEEPROM if no Pre-Patch is detected, with no change to existing circuitry or firmware, thereby representing a cost savings. SimUarly, if at some particular time in the Ufe cycle of die Storage Element Product, no Pre-Patch is required, but there is reason to expect that a Pre-Patch may be required in the near future (based, for example, on testing results not yet completed), the SEEPROM can be included, but not programmed. This aπangement advantageously allows production to continue while still faciUtating very rapid deployment/implementation of a Pre-Patch, should it be found necessary. Accordingly, invaluable flexibUity is provided during the early portion of the Storage Element or siimlar such product Ufe cycle.

f269 In step 1768, disk 340 spins up and any required configuration data is loaded. If270 A determination is made, in step' 1770 s to the presence of any Post-Patches on disk 340. If so, the Post- Patches are loaded into RAM 1752 responsive to step 1772, the Post-Patches are then initialized and the Jump Table is, once again, updated. In (he instance where there are no Post-Patches, step 1770 causes step 1772 to be skipped. At this point, the firmware structure described with regard to Figure 32 has been realized and, at step 1774, any remaining power-on procedures may be completed prior to entering normal system operation.

1(271 The Patch loading procedure of Figure 33 can be triggered, following power-on, responsive to the first command by the host to the TIC which requires data access to/from disk 340, such as, for example, a read command, a write command or an Identify Device (ED) command. It is noted that the ID command requires disk access in order to read various information such as the Storage Elemen( Serial Number, which is stored on disk 340.

1(272 It is noted that (he firmware managemen( system of the present invention is considered as highly advantageous since the Pre-Patch can be provided with the Storage Element. Accordingly, where an entity manufactures the Storage Element, tha( entity can create and revise the Pre-Patch. Therefore, the Pre-Patch and subsequent revisions need not be sent/communicated to multiple other companies that incorporate the Storage Element as a component. In this way, complete control exists in terms of which Pre-Patch revision is used with which Post-Patch revision, since aU can be co- located on each Storage Element. The Pre-Patch data is written into the SEEPROM in the manufacturing process by connecting each Storage Element to a TIC device which is connected to a testing system. The testing system software can communicate the Pre-Patch data to the TIC, which then writes it to the SEEPROM.

If273 Referring again to Figure 22, an alternative form of Pre-Patch may be utilized wherein (he Pre-Patch is provided in a host ROM section 1780 of the host device. This host ROM comprises (he ROM firmware for confrolling the overall host device. In (his implementation, the host can send/load the Pre-Patch to TIC RAM 1752, for example, using a defined vendor unique command that is initiaUy issued to the TIC. This should be done prior to any attempted access to the Post-Patch reserve area of disk 340.

1(274 StiU referring to Figure 22, as another part of (he highly advantageous firmware management system of the present invention, each Patch is created relative to a specific version of TIC ROM 1751. A Patch that is intended for a given ROM will not work with other ROM revisions. Additionally, if a Patch is loaded and initialized with an inconect ROM version, it could corrupt the firmware and cause the Storage Element to become non-functional. To allow a Storage Element to function with multiple TIC revisions, a highly advantageous methodology is used to preven( incompatible Patches from being loaded and executed. First, at the time of manufacture, Patches for different ROM versions are stored on the Storage Element at different locations on the disk, thereby allowing one Storage Element to function with multiple TIC ROM revisions. Second, the header of a Patch is versioned so that when the Patch header is read by the firmware, the loading and/or initialization of the Patch can be aborted, if the version does not match the cuπently executing ROM release. This versioning prevents Patches from incompatible ROM versions from being executed and avoids the need for an installer of the Storage Element to have to modify Pre-Patch firmware responsive to transitioning from one TIC revision to another. Furthermore, Pre- and Post-ρa(ches may not necessarily be compatible with each other. Therefore, an additional version check is done between Pre- and Post-Patches when a Post-Patch is loaded. A compatibUity version is placed in the Post-Patch that indicates its compatibUity with Pre-Patches. If the compatibUity level of the Post-Patch does not rώatch that of the Pre-Patch, then the Post-Patch loading and/or initialization is aborted.

275 Using the specification to this point and Figures 1-33, it is considered that one of ordinary skiU in the art may readUy practice the present invention in view of the teachings therein. For further explanatory purposes, however, the device aπangement and method disclosed thus far will be described in more detail in conjunction with Figures 34-45. It is noted, in the context of the discussion which foUows, that an integrated circuit which is equivalent to Servo/Control IC 1304 may be refened to using the term "Nova" or "Nova 330", whUe TIC 1300 may be refened to as a "Transition IC".

If276 The Convergent Systems Solutions (CSS) Transition IC (TIC) is a companion ASIC to the CSS Storage Element (SE). When combined together, they form a uniquely high-capacity and low-cost storage system for a wide variety of electronic appUcations including compact, low power, and mobile applications. The TIC is a datapath confroUer IC designed to simplify integration and control of the SE. The TIC is designed to reside on the customer PCBA. Host systems communicate with (he TIC through an interface that is simUar to a CompactFlash True IDE Mode interface. The TIC controls the Storage Element via a 20-conductor interface. The TIC combined with the SE perform aU of the functions required to store and retrieve data over a "CompactFlash True IDE Mode"-like interface. The TTC functions are designed to be integrated into other logic devices contained on the host PCB. This integration is intended as a next-generation cost reduction step and is not intended for the initial application of the TIC/SE.

Features

K277 • Host transfer rates up to PIO Mode 4 (16.7 MB/s) and UDMA Mode 4 (66.7 MB/s) are supported.

1(278 • 16 KB buffer with read look-ahead and write buffering (normaUy disabled) for streaming appUcations.

If279 • Low-power and power-down modes for battery-powered appUcations.

1(280 • Logical Block Addressing (LBA) mode is supported.

1(281 • Automatic eπor detection and coπection with four-way interleave Reed-Solomon ECC code capable of coπecting up to 5 bytes per interleave or twenty bytes per block.

If282 • Single +3.3 Volt supply required.

283 • 144-baU MicrostarBGA¹ package.

1(284 • "CompactFlash True IDE Mode"-like interface for simplified customer integration.

Functional Overview

|285 The CSS Transition IC (TIC) is a datapath/confroUer IC designed specificaUy for use with the CSS Storage Element (SE). The TIC combined with the SE contains all of the elements necessary for a eomplete data storage device. The TIC interfaces to system electronics through an interface that is simUar to a CompactFlash True IDE Mode interface and to the SE through a 20 pin proprietary data and control interface. To facUitate integration into systems the TIC has been designed so that the pin ordering of both interfaces can be reversed. The TIC contains a high performance DSP, "CompactFlash True IDE Mode"-like interface, Buffer Manager, Formatter/ Sequencer, Eπor Coπection Code and Detection circuitry, Servo Logic, and the serial port circuitry. Core logic operates at 1.8V and is suppUed by on-chip regulators from the 3.3V supply.

286 Attention is now directed to a description of Figure 34 which is a functional block diagram of the TIC. A T320C2700BO core is included having a 16-bit fixed point digital signal processor (DSP) optimized for mass storage mechanical and interface control applications. This device confrols the functions of all the internal blocks of the TIC and (he Storage Element. Code for (he DSP is stored in the internal mask programmable ROM. This device draws from the best features of digital signal processing, reduced instruction set computing (RISC), micro-controUer architectures, firmware and tool sets. The DSP features 66K words of internal fast static random-access memory (SRAM), 48K words of read-only memory (ROM), single-cycle instruction execution and fast 32 bit read access to buffer memory.

1(287 The TIC interfaces to host electronics through an interface that is simUar to a CompactFlash True IDE Mode interface (refened to as the TIC Hos( interface throughout this document). The TIC Host interface is the coinmunication and data transfer connection between the host and the SE. The interface is configurable and supports programmed input/output (PIO) and Ultra DMA transfers.

If288 A Buffer Manager is the central confrol and interface between buffer memory RAM embedded in the TIC and the other blocks in the TIC that access the RAM. The Buffer Manager performs all accesses to buffer memory and generates appropriate data, address, and confrol signal tuning. It handles buffer memory access requests from the Formatter/Sequencer, the DSP core, the ECC logic, and the TIC Host interface.

f289 A Formatter/ Sequencer controls and performs the reading and writing of data between the TIC internal Buffer Manager and the Storage Element. This block prepares the user data for deUvery to the Storage Element during write. The block also receives the data from the storage element during read-back and exteacts (he user data, ft interfaces with the read channel, Servo Logic, ECC, DSP and Buffer. The block coordinates operation between the blocks during the different modes of operation.

!f290 An ECC Logic block is designed to ensure user data saved in the Storage Element is accurately delivered to the host during read-back. During a write operation, the circuitry generates ECC information for storage with the user data in the SE. During read back, (he ECC infoπnation is used to check (he da(a for any enors and if enors are detected, a coπection is applied. The ECC is a four-way interleave Reed-Solomon ECC code capable of coπecting up to 5 bytes per interleave or twenty bytes per block.

If291 A Servo Logic block in combination with code running in (he DSP-controls the mechanical aspects of the Storage Element including: spin, head load/unload, head positioning, and seeking. The Servo Logic contains timing

Microstar BOA is a reeistered trademark of Texas Instruments measurement functions for spin control and, servo synchronization, eπor detection logic to quickly identify and process servo related enors, and sequencer logic to provide precisely timed confrol signals to the SE.

1(292 The Serial Port or Gateway provides command and confrol to the Storage Element (SE). The serial port provides communication with the read channel, preamplifier, and servo device within the SE. The confrol lines RG/WG (Read Gate Write Gate), SG (Servo Gate) and SSM/ERR (Servo Sync Mark Eπor) control the operational mode of the SE.

!f293 With reference to Figure 35, (he Transition IC is designed for ease of integration into the host system. Several configuration options provide flexibility in adapting the TIC to the host electronics. The primary required connections to (he hos( are the TIC Hos( interface to Hos( Compac(Flash Interface, external clock, system reset, 3.3V power and ground. To obtain the lowest possible power dissipation when the SE is not in use, the optional power down confrol line (TIC_OFF) should be utilized. The Host system can monitor the SE state by checking (he optional PG (Power Good) pin. The TIC connects to a 20 pin ZIF connector that the Storage Element is attached to. Both the ΗC Host interface and the TTC/SE interface pin orderings can be reversed to simpUfy PCB layout.

If294 The ΗC interfaces to the host electronics through (he ΗC Host Interface. This interface is similar to (he Compac(Flash True IDE Mode interface. To simpUfy board layout, (he pin order of this interface can be reversed on the Transition IC. The Pin Flip signal +CF_PF/-CF_PF defines the pin ordering of the TIC Host interface. Figures 36A and 36B comprise an overall system schematic. See also the Pin Descriptions section for details.

If295 On the other hand, the TIC interfaces to the Storage Element through a 20 signal interface (refened to as the SE/TIC interface). To simpUfy board layout, the pin order of this interface can be reversed on (he Transition IC. The Pin FUp signal +SE TNFLIP/-SEJT FLIP defines the pin ordering of the SE TIC interface. See the Pin Descriptions section for details.

1(296 Several additional signals are avaUable to optimize system integration and performance. These signals include CF_DMARQ, CF_DMAACK, CF_PDAIG, CF_DASP. CF_DMARQ and CF_DMAACK are handshaking signals used in UDMA transfer modes. CF_PDIAG and CF_DASP are used in the Master/Slave handshake protocol (see tile CF+ specification). More infoπnation on each of these topics is provided in the foUowing sections.

f297 The Transition IC (TIC) host interface is very simUar to the CompactFlash Specification Revision 1.4 True IDE mode implementation. The TIC and Storage Element are intended for embedded, non-removable, appUcations only. The foUowing section details the supported commands and electrical connections.

!f298 Table 2 lists the host commands supported by (he TIC: TABLE 2

Vendor Unique (OxFC) - Special TΪC/SE Functions

If 299 The following subcommand functions are supported by placing the appropriate value in the Feature Register. Any unsupported subcommands will result in an Aborted Command eπor status.

Load Code Patch (Feature Register = OxAO)

lf300 If a supplement is required for the internal masked ROM code of the TIC, a code patch can be downloaded by the host system to the TIC memory. This command is also caUed a Pre-patch. If a Pre-patch is required, this command should be sent before any other commands are sent (after power up). A binary code patch file would be provided by CSS for the host system to download into the TIC with this single command. The file transfeπed should be the provided file padded out to a modulo of 512 bytes. The host is responsible for placing a proper count in the Sector Count Register and fransfeπing aU the data when the TIC clears Busy and asserts the DRQ bits.

Get Defect List (Feature Register = 0xA3)

301 This wiU return the factory defect list to the host system The host can determine the number of blocks to transfer by reading the Sector Count Register when the TIC clears the Busy and asserts the DRQ bits or by continuing transferring blocks until the DRQ status bit is no longer asserted. The defect list consists of 32 bit entries. The first entry is the defect count. AU other entries consist of a Ust of defects by LB A in ascending order.

Set Patch Number (Feature Register = 0xA5)

lf302 If a supplemenf is required for the internal masked ROM code of the TIC, a code patch can be loaded into the Transition IC from the Storage Element at first access. If required, this command should be sent before any other commands are sent (after power_^on). If a Pre-patch is also required (see Load Code Patch above), Set Patch Number should be the second command sent after the load 'code patch. This command instructs ⁽he TIC/SE to load a factory instaUed patch from the Storage Element that is not the default patch.

K303 Additional Vendor Unique commands are being developed. The documentation for these commands is under developmen( and wUl be added to this specification in future revisions,

1(304 While the TIC host interface is very simUar to (he CompactFlash Specification Rev 1.4 True IDE mode, it is not fully compliant with that spec. The foUowing is a Ust of the major differences:

lf305 • No mechanical connector, the ΗC is designed into the system PCBA with hard-wired interface connections.

• No PCMICA PC Card capabiUty, not removable, True IDE mode ONLY.

• Master only, the TIC cannot support a slave device or be configured as a slave.

• DRQ timing requirements may not be met, especially if Write Cache is enabled.

• Standby and Sleep Power modes are different. Sleep tri-s(a(es the CF interface.

• The Standby Timer defaults to 2 seconds. For the Standby and Idle commands, each count of the Sector Count Register represents 100 millisec when setting tiie Standby Timer. A value of 0x00 does not disable the Standby timer, but sets a maximum value of 256 or 25.6 seconds. The transition into the Idle mode wUl occur after ^lA of the Standby Timer has elapsed.

• Vendor Unique command (OxFC) supports TIC/SE special functions

• Not aU specified CF commands are implemented. See below.

• Not all specified CF signals are implemented. See below.

f 306 ConφactFlash commands NOT supported by the TIC are given in Table 3 :

TABLE 3

1(307 CompactFlash signals NOT supported by the TIC are given in Table 4: TABLE4

Standby Timer

1(308 The Standby Timer defaults to 2 seconds. For the Standby and Idle commands, each count of the Sector Count Register represents 100 miUisec when setting the Standby Timer. A value of 0x00 does not disable the Standby timer, but sets a maximum value of 256 or 25.6 seconds. The transition into the Idle mode wiU occur after ^lΛ of the Standby Timer has elapsed.

Power Modes and Associated Commands

1J309 The TIC and SE support four different low power modes. Idle, Standby, and Sleep are defined in the CF+ specification. The Idle mode causes the head to unload and the disk remains spinning. The Standby mode unloads the head and causes the disk to spin down. The Sleep mode unloads the head, spins down the disk and tri-states the TIC host interface circuitry. The fourth mode is a unique non-operational mode where the only power consumed is the leakage cuπent. Whenever (he SE is no( in use, it should be placed in the non-operational mode. This mode is initiated by first issuing the Standby, Standby Immediate or Sleep command to place (he SE in Standby or Sleep mode, then asserting the TIC_OFF signal only after the Standby/Standby Immediate/Sleep command has completed. After being asserted, TIC_OFF must not be de-asserted within the first 10 μs. This non-operational mode is equivalent to removing power, so resumption of operation is the same as a power-on.

f310 The Transition IC supports five different commands associated with the above discussed power modes. The Idle and Idle immediate commands both cause the Storage Element to enter the Idle mode, but the Idle command also sets the Standby Timer. The Standby and Standby Immediate commands both cause the Storage Element to enter the Standby Mode, but the Standby command also sets the Standby Timer. The Sleep command causes the Storage Element and Transition IC to enter the Sleep mode.

Proper Use of Power Modes

f311 When using an adequate buffer and streaming data, the host should immediately command the SE to go to a low-power mode (Standby or Sleep) after the host's buffer is either full (read) or empty (write). This may be followed by asserting the TIC_OFF signal and entering the non-operational mode. This minimizes cuπent consumption whenever file TIC/SE are not accessing data. f312 Before signaling the TIC/SE to go to the noή-operational mode (asserting TIC_OFF) or removing power from the TIC or SE, a Standby, Standby Immediate or Sleep command must be issued and completed to ensure (he head has unloaded off of (he disk. Otherwise, a less reUable mode of head refract/unload wiU be used and there will be a greater chance of SE failure.

313 The user is advised to carefully consider appropriate use of the above mentioned power modes. The response time (time to access data) for each mode is different. Response time from the non-operational mode is significantly longer (approximately 1.5s total) than response time from Idle (approximately 300ms total) and response time from Standby mode (approximately Is total). These times should be considered during system design to ensure acceptable customer interface performance.

Transition IC Clock

If 314 The TIC requires an external low jitter clock signal for proper operation. The clock signal should be suppUed to pin CI (CLK_CLKIN) of the Transition IC and must also be supplied to the SE via the 20 conductor ZIF connector. Refer to the Pin Descriptions and Electrical Specifications sections of this documen( for further detaUs. A reference schematic of the Transition IC is included as Figure 35.

If315 The GPIO_8 and GPIO_C pins are reserved for future possible clocking options. CSS recommends inclusion of footprints for resistors connecting these pins to ground. The resistors are not populated at this time. Refer to the Pin Descriptions sections of this document for further details.

Channel Clock Mode

1(316 The Channel Clock Mode is used to configure the internal operation of the Transition IC for the clock signals suppUed to the Transition IC and Storage Element The Transition IC determines the Channel Clock Mode by reading the GPI0 7 pin at power up. This pin should have a 3.3K ohm puU-down resistor to ground.

Transition IC Power-on and Reset

lf317 There are two methods that may be used to bring the TIC from a powered down mode to being ready to accept data from the CF interface. Both methods require that power be stable and good for 300 μs and that the CLK_CLKIN signal be stable for at least 32 cycles after that.

If318 The prefeπed method is to make use of the TIC_OFF signal. Hold the Reset Une inactive and the TIC OFF signal active. Ensure the power is stable and good for 300 μs and the CLK_CLKIN signal is stable for at least 32 cycles after that. Then TIC_OFF should be deasserted. InternaUy, die TIC. will automaticaUy wait for its power regulators to come up and for its internal resets to propagate. At that point, the internal processor core wiU activate and begin executing code that wUl get the TIC ready to accept commands over the CF interface. A status register on the host side must be poUed to know when tiie TIC is ready to accept commands. The time frame from deassertion of TIC_OFF to this time is about 0.1 second. If 319 The other method of bringing the TIC front a non-power state to ready is to anuaUy use tiie Reset line and monitor the PG (Power Good) signal. With this method, TTC_OFF should be held inactive and the Reset Une should be held active. Ensure the power is stable and good for 300 μs and the CLK_CLKIN signal is stable for at least 32 cycles after that. PG wϊtt assert approximately halfway through he required 300 μs waiting period. After rese( is deasserted, the processor core will activate and begin the startup procedure for the TIC as above. Again, ⁽he user should poll (he CF status register on the host side before sending commands over the CF interface. This will take about 0.1 second.

If320 Table 5 describes each pin of the TIC with reference to the system schematic of Figures 36A and 36B.

Table 5- TIC Pin Descriptions

(A "1" represents a high voltage (i.e. greater than 2.1V), and a "0" represents a low voltage (i.e. less than 1.08V).)

² A "1" represents a high voltage (i.e. greater than 2.1V), and a "0" represents a low voltage (i.e. less than 1.08V). Connect to +3.3V or Ground.

³ DMA handshake lines (DMA request, DMA acknowledge). Refer to ATA/ATAPI-4 spec. Used for Multi word DMA modes an UDMA modes.

A A «"11»" represents a high voltage (i.e. greater than 2.1V), and a "0" represents a low voltaεe (i.e. less than 1.08V).

Compact Flash to TTC Cross Reference

K321 The TIC Host Interface is simUar to the CompactFlash True IDE Mode interface with the exceptions previously noted. Table 6 lists the signals used in the CompactFlash specification and their equivalent connections for the Transition IC. TABLE 6

lf322 Having described TIC 1300 in fuϊther detaϋ, attention is now directed to further discussions with respect to Servo/Confrol IC 1304 with reference to Figure 37. The latter is a block diagram of the Servo/Control IC. Table 7, in conjunction wi(h a package Ulusttation in Figure 38, gives the pinout of this IC. Figure 39 comprises a block diagram representation of the overall system, showing (he servo/control IC interfaced therein as weU as signal routing.

TABLE 7

!f323 Table 9 comprises a register map of the Nova Servo/Confrol IC of the present invention. TABLE 9

lf324 Serial communications between the host and Nova chip take place using the RefClk and the SeData pins. The clock runs continuously as it is shared with the read channel's REFCLK input. Data is asserted onto the SeData pin and must be done so synchronously with the RefClk signal. Note that this is a requirement on the host. AU serial communications are initiated by the host Table 10 shows the general format of the serial communications with the Nova:

TABLE 10

Mark Device Select R Wb Packet Field

Header Data

1(325 AU bits are vaUd on the rising edges of (he RefClk signal.

Mark

lf326 Since (here is no separate "enable" or "select" signal, all serial transactions begin with a single Mark bit. It is defined by the assertion of a " 1" on the SeData line.

Device Select (DS)

lf327 After the Mark bit, the next two bits, Device Select, determine which device is being communicated with by the host. The signal router interprets this field as shown in Table 11.

TABLE 11

328 If the selected device is an external chip (read channel or preamp), the appropriate select line for that device (RwSden or PrSden) wiU be asserted and the data bits passed though the appropriate interface (RwSdata or PrSdata). The clock signal to the channel or preamp (RwSclk or PrSclk) wiU only be active when a serial transaction is in progress. R/Wb

1(329 The R/Wb bit indicates the forma( of the Packet Field to follow.

1(330 During a write transaction (R Wb = 0), the entire Packet Field is sent to the target.

1(331 During a read transaction (R Wb = 1), only the Header portion of the Packe( Field is sen( to (he target The remainder of (he Packet Field is supplied by the target. Nova must know the Data portion length so the bi-directional data pin can change from write to read mode. Nova contains configuration registers for Packet Field length and Header portion length (see discussion below).

f332 The select line (RwSden or PrSden) for the selected external chip is asserted at the beginning of the R/Wb field to aUow one clock of setup on the target device. The external chip's select line is deasserted when die pre-programmed number of clock cycles for (hat device has elapsed (see discussion below).

Packet Field

1(333 Only the bits in the Packet field are presented to the selected device; the target never sees the Mark, Device Select or R/Wb bits.

1(334 The number of bits in (he Packe( field depends upon the Device Select setting. The number of bits for the case of Nova being selected (DS = 0) is fixed. The number of bits ttansfened when an external chip is selected is determined by the Packet Field Duration and Header Length registers for the selected device. There is a separate pair of Packet Field Duration and Header Length registers for each non-Nova device. The Packet Field Duration is the total number of data bits to transfer for the serial transaction. The Header Length register is always smaller than (he Packe( Field Duration and indicates how much of (he ρacke( is allocated to header bits. The Header Length register indicates where in the Packet Field the direction should change from write to read during serial read transactions. The programmable number of bits to be fransfeπed should be established prior to attempting communications with those devices.

1(335 For the preamp (DS = 1) the Packet Field Duration register is PsDur and (he Header Length register is PsHlen. The polarity of the PrSden signal is controUed by the setting of the PsPol bit. The polarity of the PrSclk signal is controUed by the setting of the PcPol bit.

K336 The state of the serial interface pins to the preamp while the preamp is not being communicated with is programmable. The PrSpIh register specifies the behavior. While inactive, these pins can either be put into a high-z state or asserted active low.

1(337 There are two device select settings that result in communications with the read channel (DS = 2 and DS = 3). An example of how these two can be used is for one of the device selects to be set up for accessing 8 bit wide registers, and to have the other device select set up for accessing 12 bit wide registers. The Packet Field Duration registers are RsDurl and RsDur2. The Header Length registers are RsHlenl and RsHlen2. The polarity of the RwSden signal is controUed by the setting of the RsPol bit. The polarity of the RwSclk signal is controlled by tiie setting of the RcPol bit. 1(338 The host is responsible for data bit setup and hold relative to the clock for the target device. For example, if the host has a rising clock edge in the middle of a bit window, but the target has an inverted clock, a setup or hold issue could occur. The host should have the capability to align the clock and data so the target then sees its active clock edge in the middle of the bit window.

!f339 Figure 40 is a timing diagram for the highly advantageous serial interface of the present invention, using the serial protocol of Table 10 while Table 12 defines the various parameters tha( are designated.

TABLE 12

Serial interface to Nova registers

lf340 When the device select field is set to select the Nova chip, then the data bits following the device select have the format specified by Table 13.

TABLE 13

lf341 A six bit address field (allows direct addressing of up to 64 registers) is used with one R W bit foUowed by a twelve bit data field.

342 SGate is the servo gate input. This same signal is normally routed directly to the read channel.

If 343 The polarity of the SGate input is controUed by the setting of the SgPol bit.

1(344 The RwGate pin is used to control the assertion of the read channel's RwRgate and RwWgate pins and the preamp's PrRwg pin.

Read channel

f 345 If the WgRg bit is cleared, then RwGate is used as the read gate and is simply passed through to the RwRgate pin.

1(346 If the WgRg bit is set, then the usage of (he RwGate signal can be affected by the setting of the Rlst field. If Rlst = 0 then RwGate is used as the write gate and is simply passed through to the RwWgate pin. 1J347 If Rlst = 1, the first assertion of RwGate is applied to the RwRgate pin and then all subsequent assertions are appUed to the RwWgate pin. The purpose of this system is to allow a single data sector to be read (to obtain, for example, repeatable runout coπection data) and then aU subsequent sectors to be written.

1(348 If Rlst = 2, the first assertion of RwGate is appUed to the RwRgate pin and then subsequent assertions are appUed to the RwWgate pin until SGate is asserted, which resets the entire process. The purpose of this system is to allow the first data sector of each servo wedge to be read and the other sectors in the servo wedge to be written.

If349 The polarity of the RwRgate pin is controUed by the setting of the RwRgPol bit and the polarity of the RwWgate pin is controlled by the setting of the RwWgPol bit.

Preamp

1J350 WhUe the read channel's write gate signal is deasserted, the preamp's PrRwg signal is kept so that the preamp is held in the read mode.

1(351 When the read channel's write gate gets asserted, the preamp's PrRwg signal transitions to put the preamp into write mode. The timing of the fransition can be so that PrRwg is identical to the read channel's RwWgate signal or it can be a delayed version of tha( signal. The amoun( of the delay is controlled by the setting of the PrRwDly register. A setting of zero conesponds to no delay. If PrRwDly has a nonzero setting, tiie PrRwg assertion is delayed by the number of clock ticks specified. The clock used is determined by the setting of the DlyClk bit. If it is cleared, the RefClk is used. If it is set, the NrzClk is used.

If352 If the assertion of the PrRwg signal is delayed so long that it is still asserted when the servo gate (SGate) signal gets asserted, PrRwg wiU be forced into a deasserted state and an enor condition wiU be flagged. The eπor condition flag is SgWgEn.

1(353 The PullPrWg bit allows assertion of SgWgEn to puU write gate to the preamp.

1(354 The polarity of the PrRwg pin is controUed by the setting of the PrRwPol bit.

SsmErr

1(355 The SsmEπ pin has two modes of operation. The active mode depends upon the 'state of the SGate (servo gate) pin. It is always an output from Nova to the host.

Sync mode

!f356 WhUe SGate is asserted, the SsmEπ pin is in the sync mode. It passes through the signal received from the read channel on the RwSsmpin. The polarity of the RwSsm input is determined by the setting of the SsmPol bit.

Error mode

lf357 While SGate is deasserted, the SsmEπ pin is in the eπor mode and is used to sienal eπor conditions to flip, h t The following is a list of events that can generate an eπor condition:

1. Assertion of the RwTad pin (thermal asperity detection) by the read channel.

2. Servo gate asserted while the preamp write gate was still asserted (available only in latched form).

3. Detection of an event from tiie VCM shock/environment sensor.

4. Detection of clock loss.

5. Power fault (POK deasserted).

f 358 Whether or not a particular eπor source is enabled is selected by tiie setting of that source's enable bit in the EπCfrl register. Furthermore, most eπor signals can be appUed to SsmEπ in either their real-time form or latched form. This is controlled by bits in the EπCfrl register that individuaUy coπespond to each eπor source. If the latched form is chosen, SsmEπ remains asserted until the EnStatus register is read, clearing the latched bit and deasserting SsmEπ. The latching circuits are level sensitive so, if the enor condition is active at the time ⁽he latched bit is read, that bit wiU remain set. The EnStatus register contains bits that indicate both the real-time and latched status of each enor source.

359 If an eπor occurs while SGate is asserted, the condition is not reflected on the SsmEπ pin until after SvGate has been deasserted. If a real-time eπor signal is selected and the eπor condition asserts and subsequently deasserts — ll whUe servo gate is asserted, the eπor is never signaled on SsmEπ.

If 360 AU enabled eπor sources are ORed together on the SsmEπ signal. The host must look at the EnStatus register to determine which enor conditions) occuπed.

1(361 The power-on default is for the real-time POK eπor to be the only one enabled.

GPIO pins

1(362 The GPIO pins are highly configurable pins that can be used as inputs or outputs. They can optionally be configured to have a puUup, a pulldown or neither. Several pins have additional, alternate functions.

1(363 The Gpiol pin has no function other than Gpio 1.

1(364 Gpio2 canno( reaUy be used as a GPIO pin. The analog portion of the Nova chip gets its clock from this pin. It must be either be configured so tha( it drives RefClk as an output or as in input with a clock appUed to (he pin. The configuration of the Gpio2 pin is controlled by the Gp2Mode register.

1(365 The Gpio3 pin has no function other than Gpio3.

1(366 Gpio4 is an alternate function that the Fcom pin can be used for. The configuration of the Fcom pin is controUed by the Gp4Mode register.

!f367 Gρio5 is an alternate function that the Zcross pin can be used for. The configuration of the Zcross pin is controUed by the Gp5Mode register. Voltage monitor

lf368 The POK (Power OK) signal from Nova is an indication that the 3.3 volt supply has risen above its threshold voltages plus the hysteresis voltage, and has remained above its threshold voltages plus the hysteresis voltage, for a specified time period. The POK signal in the high state indicates that the power supply is ready. The Nova chip will monitor the 3.3 volt supply by internaUy dividing (he supply down to its threshold level. Once POK is high, if the power supply goes below its threshold voltage, the POK signal will go to its low state, which wUl reset the Nova chip. The POK signal is an open drain with a 10K internal puU-up resistor.

If369 In the absence of a capacitor connected to the Cpok pin, the time delay from when power is good to when the POK signal is asserted is fixed by Nova. When a capacitor is connected to the Cpok pin, the delay is extended. The duration of the extension is determined by the size of the capacitor used. The capacitor is charged with a fixed cuπent. POK is asserted after the voltage on the capacitor has reached the threshold level.

1(370 If no external Cpok capacitor is being used, the pin should not be connected to anything.

1(371 When POK is deasserted, an autorefract is triggered. After POK has deasserted, aU registers wUl be to their power-on default settings. POK deassertion asserts the POK eπor condition. Table 15 recites various parameters relating to Power OK.

TABLE 15

Notes: 1. POK Delay - length of time that POK stays low after Vcc is vaUd (above threshold) 2. Tpok = Kpok * Cpok / Ipok

Thermal monitoring

1(372 Nova also has an internal temperature sensor (diode) that can be used to monitor the junction temperature of the chip. The internal temperature diode is connected to the ADC. The signal is converted when the Vtempi register is read. Vtempi has a typical room temperature (25 degC) voltage of TBD volts and an approximate temperature coefficient of - 7.4 mV/degC. Regulators

lf373 WhUe this version of Nova (Nova 330) does not include a 3.3V regulator, the Nova supports (he implementation of a switchable 3.3V power supply for use by external chips (read channel and preamp). There is a choice of two different implementations.

!f374 First, there is an internal switch. When the internal switch is used, the switchable 3.3V supply for the external chips is provided on the V3p3a and V3p3b pins. The state of the switch is controUed by the setting of the 3p3Sw bit in the serial registers.

If375 Alternatively, if a switch with even lower Rdson is required, Nova can be configured to confrol an external switch. If an external switch is used, it is controUed with the G3p3 pin. The 3ρ3Sw bit is used to control the state of the external switch. See Table 16.

TABLE 16

lf376 The Nova chip provides a -0.55 volt output A bit, EnaVee, aUows this regulator to be disabled.

Single DAC system

1J377 Although there are multiple DAC registers that can be written, the Nova performs all conversions with a single DAC. The DAC cycles through each of the DAC registers performing a conversion on each one at a time.

If378 In most cases, the Nova functionaUy appears to have separate DACs for each DAC register, and (he rue nature of the single DAC architecture is of no consequence to the apphcation. Discussion in (he spec may suggest that there are individual, separate DACs. The fact that there is no discrete DAC for each DAC register will not normally be pointed out.

1(379 The main operational difference that wiU occur in this system (vs. a system with a separate DAC for each register) is that there may be some delay between the time tha( a DAC register is written and the time that the conversion begins. This delay wfll vary depending upon where in the conversion sequence (he DAC is a( the time the register is written. The maximum amount of the delay depends upon the RefClk frequency.

VCM driver

, lf380 Figure 41 shows a block diagram of one embodiment of an integrated VCM driver in tiie Nova.

VCM DACs

1(381 There are two independent VCM DACs, tracking and offset. The two DACs are provided so (hat while ihe VCM fracking DAC is being used for ttack following, tiie VCM offset can be used to set a fixed offset against whatever bias is present. This is usefiil if the gain range desired for ttack foUowing does not have sufficient range to nuU out the bias. Table 17 shows how (he gain range setting affects the VCM fracking DAC output.

TABLE 17

lf382 The VCM offset DAC always has a fixed multipUer of 1/2 (i.e., it commands half the range of cuπent). VCM Offset DAC Gain Options are shown in Table 18.

TABLE 18

lf383 When the midrange value (200h) is written to a VCM DAC register, the coπesponding cuπent output is zero. 3FFh results in maximum positive cuπent (for the specified gain range). OOOh results in maximum negative cunent (for the specified gain range) .

1(384 The gain range for the VCM tracking DAC is shared with the dither system (see below).

Priority of tracking DAC writes

1(385 Normally, the single physical DAC in the Nova chip goes through the conversion of each of the different DAC registers (VCM fracking and offset, spindle tracking and offset, etc.) in a fixed sequence. In this "normal" mode, the VCM tracking DAC register has no special priority over any of the others. So, just as with aU the other DAC registers, there may be a delay from the time the DAC register is written to the time tha( tiie value is converted and the new value appears in the analog system.

386 Recognizing that this delay could introduce significant problems in the frack foUowing confrol loop, Nova provides an ability for writes to the VCM fracking DAC registers to be converted as soon as possible. This is refened to as the "priority" mode. In this mode, the normal DAC conversion cycle is interrupted by a write to the VCM tracking DAC register. Whatever conversion is in progress is aUowed to complete and then tiie VCM fracking DAC register is converted next (regardless of where the system was in the sequence prior to the interruption).

1(387 After the VCM tracking DAC register is converted, the normal DAC conversion sequence resumes at the point where it was interrupted.

1(388 The choice between the normal mode and the priority mode for the fracking DAC writes is controUed by the TdPri bit in the serial port registers.

Dither

1(389 The dither system is designed to improve the VCM performance in the face of high static friction. It is implemented as a set of 4 pairs of VCM cuπent ampUtudes and timer values. Each pair is associated with a dither state as shown in Table 19.

TABLE 19

1(390 When the dither system is enabled by setting the DiEna bit, it is initiaUy in state 0.

1(391 When a dither state is entered, the cuπent specified by the state's ampUtude register is added to commanded VCM cuπent. The dither system remains in that state until the time indicated in the state's time register has elapsed. Then the next dither state is entered. The system progresses through the dither states sequentially; i.e., 1 to 2 to 3 to 4.

1(392 The action taken after the final timer (state 4) has expired depends upon the setting of the DiMode bit. A setting of 0 coπesponds to the free-running mode. In this mode, the dither system simply goes back to the first dither state (state 1) and repeats the entire sequence continuously. A DiMode setting of 1 coπesponds to the restart mode. In the restart mode, the dither system restarts at state 1 every time the VCM DAC register is written.

1J393 The DAC outputs resulting from (he di(her register settings are added to (he other VCM DAC outputs at the cuπent confrol loop summing node.

^' lf394 The gain of the dither DAC output is the same as whatever is selected for the VCM fracking DAC.

If395 The entire dither system can be disabled by clearing the DiEna bit.

1J396 Each LSB of the dither timer registers coπesponds to 1 full cycle of the DAC. Interaction of VCM tracking DAC, VCM offset DAC and the Dither DACs

K397 The output of the VCM fracking DAC, the VCM offset DAC and the cuπently active dither DAC (if enabled) are all summed together. If the settings of these DACs are such that a voltage greater than the reference is commanded, the system simply saturates at the maximum available cuπent.

VCM compensation network

!f398 Compensation of the VCM cuπent control loop is provided by an external network connected to the VcmCmpi and VcmCmpo pins. An internal resistance in series with this network can be provided by the Nova chip. The resistance is controlled by the setting of the CompR register according to Table 20.

Table 20

Integrated spindle driver

lf399 The integrated spindle driver consists of the foUowing subsystems:

• Spin DACs

• Cuπent sense circuit

• Gate drivers and power FETs

• Back EMF sensor and Z-cross generator

• Commutation logic

1[400 Figure 42 shows a block diagram of the spindle driver system.

1(401 Commutation control - The spindle driver controls a 3 phase motor. The power FETs are selectively turned on and off to energize (he motor phases in a sequence that results in spindle rotation. The process of advancing through this sequence (commutation) can be controlled by software, the zero crossings of the motor back-EMF or by an external pin.

1(402 Spin cuπent control - The cuπent applied to the selected pair of motor phases is carefuUy controlled. The spin DACs provide the reference input to the spin cuπent confrol system. The "plant" is the gate drivers and power FETs and the sensor is implemented by the sense resistor and cuπent sensing circuit.

1(403 Center tap - The spindle driver is capable of working with motors that have no center tap connection. Nova wUl internaUy generate a "phantom" center tap to support these motors. If a motor is used that does have a center tap connection, Nova can utilize it instead of the phantom center tap system. Spin DACs

1(404 There are two 10-bit spin DAC registers (converted into analog signals by a single physical DAC). One is normaUy adjusted to maintain spin speed (SpnTrkDac) and the other is used to offset up to the run cuπent (SpnOffDac). The converted outputs are summed together.

If 405 The fine spin DAC (SpnTrkDac) has higher resolution but less range than the offset DAC. It can span 1/4 of (he fidl range. Table 21 shows the Spin offsef DAC ranges.

TABLE 21

Referring to Table 22, DNL is defined as die deviation from an ideal 1 LSB step (1 LSB +/- DNL). INL is defined as the deviation from the ideal steps between the real (measured) voltage end points. LSB is defined as (3FF hex voltage - 000 hex voltage) / (2^Λbits -1).

TABLE 22

Current sense circuit

1(407 The cuπent sense circuit has as its input the voltage across the sense resistor. This voltage is scaled so that when (he maximum cuπen( is flowing (hrough (he sense resistor, the output of (he circuit is a voltage that is the same as the maximum commanded spin DAC voltage. Related parameters are described in Table 23.

TABLE 23

Gate drivers and power FETs

1(408 A spin cuπent eπor signal is created by linearly comparing the summed output of the spin DACs (V_COm_man_d) to (he scaled vol(age from the cunent sense circuit (V_fe_{d ack})- This eπor signal is used to drive the "low side driver" gate of the power FETs. The gate drive modulates (he power FET in such a manner that drives the spin motor cuπen( to the desired value. In this linear mode, the "low side driver" is basically used as a variable resistor. The cunent confrol loop bandwidth must be high enough that the closed loop phase loss, at 15 Hz, is less than 5 degrees.

f 409 The "high side drivers" are operated as on/off switches, based on the commutation state.

If410 The power FETs are internal to the Nova chip. Figure 43 shows a diagram of the gate drivers and the power FETs.

1(411 There is a deadband buil( into (he cuπen( loop command. The deadband is jus( enough to guarantee a low leakage cuπent when zero amps is commanded. Related parameters are given in Table 24.

TABLE 24

Notes: See the section "Reference Voltage" for Vrefi

Slew rate limiting

If 412 The power FET gate drivers have a slew rate limiting capabiUty to confrol the voltage spike when turning off cuπent in one motor coil and turning on the cuπent in the next motor coil during commutation. The slew rate limiting eUminates the need for an external snubbing circuit.

If413 Slew rate is controUed by a constant cuπent being driven into the gate capacitance of the power FETs. The commutation slew cuπent is designed to prevent voltage overshoots from occurring when the motor coils have the specifications given in the Table 25.

1(414 The commutation Slew cunent may be reduced by 1/2 by setting the Sslew bit. TABLE 25

BEMF sensing and z-cross generation

1(415 The BEMF of the undriven motor phase (at any given time, one phase is high, a second phase is low, and the third phase is undriven) is sensed by (he Nova chip. The chip generates a logic signal that has an edge coπesponding to each zero crossing of the BEMF signal.

If 416 The z-cross signal can be appUed to the Zcross pin so that it is available for use by external devices. This is enabled by setting the Gρ5Mode bit in tiie serial registers. The polarity of the z-cross output is controUed by the setting oftbe ZcrPolbit

Commutation logic

1(417 The commutation logic determines which pair of power FETs is being employed at any given time. Each motor phase outout has two FETs associated with it: a "high" and "low". When the high side FET is selected, it is turned completely on. WTien the low side FET is selected, its associated gate drive circuit is enabled. There are six different configurations, or commutation states, (hat the power FETs can be in. Table 26 shows, for each commutation state, which (if any) FET is employed for each motor phase:

TABLE 26

1(418 All of the FETs are off when EnSpn is zero. Transitioning the EnSpn bit from 0 to 1 causes the commutation state to reset to 0. To put the Nova chip into a known commutation state, the spin drivers must first be disabled and then enabled.

1(419 The commutation advance sequence is 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, etc. There are three methods for advancing the commutation state: manual, automatic and external. The selected method is determined by setting of the ComSel field in the serial registers. See Table 27. TABLE 27

1(420 In (he automatic commutation mode (ComSel = 1) the z-cross to FCOM timer (ZFT) is reset every time a z- cross edge occurs. The timer is incremented until it reaches the value specified in (he SpnConiDly register. The rate at which the ZFT increments depends upon the ComRfCk registers setting (see Table 28). Once the ZFT has incremented up to where it is equal to the SpnComDly setting, the commutation signal is generated and the timer stops.

TABLE 28

1(421 During initial spin motor start, the manual commutation mode can be used with the commutation state machine advanced by writing to the SpnCom register. The manual advance wfll bring the spin motor speed to approximately 5 to 15 percent of the final speed. Once 5 to 15 percent of speed is achieved, the automatic commutation mode can be selected.

1(422 The polarity of the Fcom input (used in the external commutation mode) is controlled by the setting of (he FcomPolbit.

1(423 Figure 44 shows the Nova commutation control logic. Table 29 provides details with regard to various signals under discussion.

TABLE 29

1(424 Figure 44 shows the Nova commutation confrol logic. Table 29 provides detaUs with regard to various signals under discussion. Autoretract

1(425 Power4oss autorefract - When a power fault occurs (indicated by deassertion of POK), Nova automatically refracts (he VCM using energy stored in an external capacitor. The capacitor is connected to the Nova chip on the Cret pin.

1(426 There is presently no provision for extracting energy from the rotating spindle. If no capacitor connected to the Cret pin, no autorefract capability is provided in tiie event of a power loss.

f427 In normal operation (i.e., prior to performing the retract), Nova charges the refract capacitor to a specified voltage. TTie capacitor may initiaUy be in a discharged state and some time wiU be required for it to become fully charged to its full voltage. The time required to fuUy charge the retract capacitor depends upon its size.

If428 During the retract, Nova actively controls the voltage appUed to the VCM. This is to provide control over the maximum velocity the actuator can attain during the refract process. The voltage limit is selected through the Refract serial port register.

f429 There is no provision for confrolling the duration of the retract (other than by changing the capacitance of the retract cap). The refract process continues until the voltage on the capacitor falls below tiie circuit's ability to continue operation.

1(430 If the power returns before the refract is completed, Nova forces tiie refract cycle to complete. After the refract cycle completes, Nova begins the normal power up cycle with the normal POK delay, coming up in the sleep mode.

If431 Clock-loss autoretract - There is an optional capability to cause an autorefract to occur if no edges are detected on the RefClk pin for more than a specified period of time. This capabiUty can be enabled by setting the NoCkAr bit (default it disabled). When an autorettac( is triggered by the loss of RefClk, the power is taken from Vcc rather than the retract capacitor.

f432 The clock-loss autorefract wiU be superceded the power-loss autorefract Specifically, if (he RefClk is lost, initiating a clock-loss autorefract drawing power from Vcc and then, shortly after, the power is lost, the autorefract circuit wiU immediately switch over to taking power from (he retract cap. Various autorefract related parameters are described in Table 30.

TABLE 30

A D converter

lf433 Refeπing to Table 31, the Nova chip has a 10-bit A D converter. The AdcCh register determines which signal is to be converted. The conversion process is initiated by writing to the AdcCh register. The converted result is obtained by reading (he AdcRead register. This register also contains the Busy bit, which indicates whether or no( the conversion has completed yet.

TABLE 31

A/D Converter Input Choices

lf434 The ADC can be configured to accommodate 3 different ranges of voltage. The range is controlled by the setting of the AdcRng register. In aU cases, the midrange is centered at the reference voltage of 0.9 volts. See Table 32.

TABLE 32

If435 DNL is defined as the deviation from an ideal 1 LSB step (1 LSB +/- DNL). HSTL is defined as the deviation from (he ideal steps between the real (measured) voltage end points. LSB is defined as (IFF hex voltage - 00 hex voltage) / (2^Λbits -1). See Table 33.

TABLE 33

Park detect

f 436 The PrkDet pin has a weak puUup resistor on it. The "park" condition is signaled by pulUng this pin down to ground. The puUup can be enabled and disabled with a bit (PdPuEn).

If437 Information about activity on the PrkDet pin is made available to the host via the PdCur and PdLtch bits in the serial port registers. The PdCur bit reflects the instantaneous state of the pin. When PrkDet is pulled down (asserted), the PdCur bit is set to 1.

1(438 The PdLtch bit latches the state of the PdCur bit. When PdCur gets set, the PdLtch bit gets set and remains set until the register containing it gets read. The PdLtch bit remains set until read even if the PrkDe( bi( deasserts. Whenever the register containing the PdLtch bit is read, the PdLtch bit gets cleared to zero. It remains cleared until the PrkDet pin gets asserted again.

1(439 The PdBounce bit indicates that the park detect switch closed, (hen opened and (he finally closed again.

BEMF measurement

1(440 With reference to Figure 45, the Nova chip provides a circuit that aUows precise measurement of the BEMF on the VCM. The general approach is to subtract the voltage due to the applied cuπent from the raw voltage appearing across the VCM. The remaining voltage is due to BEMF and is available as an input to the ADC. It is considered that one of ordinary sktil in the art may implement circuitry directed to this pmpose in any number of alternative ways in view of this disclosure; one suitable implementation is shown in Figure 45 and is further described immediately below.

1(441 SsRcal is register that is adjustable so as to control the value of a resistor designated as Rbemf and has a range that allows the ratio of SsRcal R2 to closely approximate the ratio of Rvcm to Rsense, where Rvcm is a DC resistance of a coU in the voice coil motor and Rsense is a series resistor that may also be designated as Rvs. The max SsRcal setting available is 125K ohms. R2 is 5K ohms giving a maximum Rvcm Rsense ratio of 25:1. The Nova's Rsense is 1 ohm so tiie Nova wiU accommodate VCM coU resistances up to 25 ohms. The minimum SsRcal is 50 K ohms providing accommodation of VCM coU resistances as low as 10 ohms. The resistors in (he difference amp circuit are lOKohms each.

1(442 It is noted that portions of the foregoing descriptions are presented in terms of symbolic representations of operations on data bits within an electronic device. These descriptions and representations are the means used by (hose skUled in the data processing arts to most effectively convey the substance of their work to others sktiled in the art. The operations are those requiring physical manipulations of physical quantities. UsuaUy, though not necessarily, these quantities take (he form of electrical or magnetic signals capable of being stored, transfeπed, combined, compared, and otherwise manipulated. It has proven convenient at times, principaUy for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that aU of these and simUar terms are to be associated with the appropriate physical quantities and are merely convenient labels appUed to these quantities.

1(443 Further, manipulations performed may be refened to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capabiUty of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases, the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to an apparatus and to a method for operating an electromechanical aπangement in processing electrical or other (e.g., magnetic) physical signals to generate other desired physical signals.

1(444 Since the Storage Element, devices in which the Storage Element is used and associated method disclosed herein may be provided in a variety of different configurations and (he method may be practiced in a variety of different ways, it should be understood that the present invention may be embodied in many other specific ways wifhout departing from the spirit or scope of the invention. Therefore, the present examples and methods are to be considered as iUusfrative and not restrictive, and the invention is not to be limited to (he details given herein, but may be modified within the scope of file appended claims.

Claims

WHAT IS CLAIMED IS:

1. In a digital system, an assembly comprising: an electromechanical digital data storage aπangement including a rotatable disk and at least responsive to a read gate signal for initiating a read therefrom and responsive to a write gate signal for initiating a write thereto; a host device that is configured for controlling the data storage aπangement and for generating said read gate signal and said write gate signal in a mutually exclusive way; and an interface electrically interconnecting the data storage anangement and the host device using a plurality of electrical conductors such that a selected one of the conductors carries both the read gate signal and the write gate signal.

2. The system of claim 1 wherein said electromechanical storage aπangement is configured for storing servo information and user data on the rotatable disk and for generating a servo synchronization signal responsive to handling said servo information and for generating an eπor signal responsive to detection of an eπor relating at least to said user data and said host device is configured for controlling the data storage aπangement, at least in part, by using said servo synchronization signal and said eπor signal, and said interface includes a particular one of tiie conductors which carries both the servo synchronization signal and the enor signal in a mutuaUy exclusive manner.

3. In a digital system, a method comprising the steps of: providing an electromechanical digital data storage aπangement including a rotatable disk and being at least responsive to a read gate signal for initiating a read therefrom and responsive to a write gate signal for initiating a write thereto; configuring a host device for controlling the data storage aπangement and for generating said read gate signal and said write gate signal in a mutually exclusive way; and aπanging an interface for electricaUy interconnecting the data storage aπangement and the host device using a plurality of electrical conductors such that a selected one of the conductors carries both the read gate signal and the write gate signal.

4. The method of claim 3 wherein said electromechanical storage arrangement is configured for storing servo information and user data on the rotatable disk and for generating a servo synchronization signal responsive to handling said servo infoπnation and for generating an eπor signal responsive to detection of an eπor relating at least to said user data and said host device is configured for confrolling the data storage aπangement, at least in part, by using said servo synchronization signal and said eπor signal, and the step of aπanging the interface includes the step of using a particular one of the conductors to carry both the servo synchronization signal and (he eπor signal in a mutuaUy exclusive manner.

5. In a digital system, an assembly comprising: an electromechanical digital data storage aπangement including a rotatable disk having servo information and user data storable thereon and configured for generating a servo synchronization signal responsive to said servo information and at least for generating an eπor signal responsive to detection of an eπor relating to said user data; a host device (hat is configured for confrolling the data storage aπangement, at least in part, by using said servo synchronization signal and said eπor signal; and an interface electrically interconnecting the data storage aπangement and (he host device using a plurality of electrical conductors such that a selected one of (he conductors carries both tiie servo synchronization signal and the eπor signal in a mutually exclusive manner.

6. In a digital system, a method comprising the steps of: providing an electromechanical digital data storage aπangement including a rotatable disk having servo information and user data storable thereon and configured for generating a servo synchronization signal responsive to said servo information and at least for generating an eπor signal responsive to detection of an enor relating to said user data; configuring a host device for confrolling the data storage aπangement, at least in part, by using said servo synchronization signal and said eπor signal; and aπanging an interface to electricaUy interconnect the data storage aπangement and the host device using a pluraUty of electrical conductors suchtha( a selected one of Ihe conductors carries both he servo synchronization signal and die enor signal in a mutuaUy exclusive manner.

7. In a system including an electromechanical digital data storage anangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the confrol of a servo electronics device having a servo serial interface, in cooperation with a read/write electronics device having a read/write serial interface for confrol thereof, and a preamp electtonics device having a preamp serial interface for confrol thereof, such fha( digital data can be written to or read from said disk responsive to a host device, said storage aπangement thereby including a plurality of device serial interfaces, an interface anangement, comprising: an external serial interface, forming part of the storage anangement, for use in externaUy electricaUy connecting the storage aπangement and for bi-directionaUy externaUy transferring a serial control-related data, for use in operating each of the servo device, the read/write device and die preamp device; a host serial interface, forming part of the host device, in data communication with the external serial interface of the storage anangement, configured for applying a device identification on the external serial interface in a way which directly associates at least a portion of the serial control-related data with each of the device serial interfaces; and a serial router, forming part of said storage aπangement, in data communication with each of (he device serial interfaces, for using said device identification to manage said serial control-related data bi-directionaUy between die device serial interfaces and the external serial interface.

8. In an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the confrol of a servo electronics device having a servo serial interface, in cooperation with a read/write electtonics device having a read write serial interface for confrol thereof and a preamp electtonics device having a preamp serial interface for control thereof; such that digital data can be written to or read from said disk, and said storage anangement thereby including a plurality of device serial interfaces, an external interface aπangement, comprising: a primary serial gateway for implementing external bi-directional transfer of a serial control-related data that is used in operating each of the servo device, the read/write device and the preamp device, consistent with a serial protocol; and a serial router in data communication with said primary serial gateway for using said serial protocol to manage said serial control-related data bi-directionaUy between the primary serial gateway and each of tiie device serial interfaces.

9. In a system including an electromechanical digital data storage anangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the control of a servo electronics device having a servo serial interface, in cooperation with a read write electronics device having a read/write serial interface for control thereof, and a preanp electtonics device having a preamp serial interface for confrol thereof, such that digital data can be written to or read from said disk responsive to a host device, and said storage anangement thereby including a pluraUty of devices and associated device serial interfaces, an interface aπangement, comprising: a primary serial gateway, forming part of the storage aπangement for externally bi-directionaUy transfeπing a serial control-related data, which is used in operating said devices; a hos( serial interface, forming part of the host device and in data communication with the primary serial gateway of the storage aπangement configured for applying a serial protocol to the serial control-related data passing between the host device and the storage anangement; and a serial router, forming part of said storage arrangement and in data communication with said primary serial gateway, for using said serial protocol to manage said serial conttol-related data between the primary serial gateway and each of (he device serial interfaces.

10. The system of claim 9 wherein said serial control-related data includes a series of commands issued by tiie host device to the storage aπangement and wherein said host device is configured for adding a device ID, as part of said serial protocol, to each of said commands, which device ID selectively identifies one of said devices for use by said serial router.

11. The system of claim 9 wherein said serial control-related data includes a series of commands issued by the host device to the storage aπangement which is made up of read commands and write commands and wherein said host device is configured for tracking a portion of said serial control-related data that is associated with each command

12. The system of claim 11 wherein, for a cuπent one of said commands, the host device and the serial router are confijgured to cooperate to capture the serial gateway for use by the cunent command prior to the host device issuing a subsequent command.

13. The system of claim 11 wherein the storage anangement includes an operation definitions section which specifies a command length for each command that is associated with a particular device and the host device cooperates with the storage aπangement for fracking a cuπent command based on the command length for that command, as part of said serial protocol.

14. The system of claim 13 wherein the host device is configured to Usten for a specified number of bits during transfer of said cuπent command until said command length is reached and, thereafter, initiates a subsequent command.

15. The system of claim 14 wherein (he cuπent command is a write command that is directed to a targeted one of said device serial interfaces, using said device ID, and each write command, including the cuπen( command, includes a header portion and a data portion, to cause (he targeted device, that is associated with (he targeted device serial interface, to store the data portion at a particular location in the targeted device.

16. The system of claim 14 wherein tiie cuπent command is a read command that is directed to a targeted one of said device serial interfaces, using said device ID, and each read command, including the cuπent command, includes a header portion and a data portion, such that tiie host device and the storage aπangement cooperate to send the header portion to a targeted device, that is associated with a targeted device serial interface, to cause the targeted device to use the header portion to read a specific data group from a specific data location within the targeted device and, thereafter, the storage arrangement returns the specific data to die host device as said data portion.

17. The system of claim 9 wherein said serial control-related date includes a series of commands issued by the host device to the storage aπangement and each command is directed to a targeted one of said devices and includes a first set of infoπnation that is for use by the storage aπangement at least for controlling said serial router and a second set of information that is for internal use by said targeted device.

18. The system of claim 17 wherein (he firsf se( of information includes a mark bi( which initiates (he command and further identifies the command as one of a read command and a write command.

19. The system of claim 18 wherein the first set of information further includes a device identification that indicates the targeted device.

20. The system of claim 17 wherein the second set of information includes a header portion, which specifies a specific data location in tiie targeted device, and a data portion for one of reading from or writing to the specific data location.

21. The interface aπangemen( of claim 9 wherein said host serial interface is configured for applying a device identification to a specific portion of said serial control-related data that is to be directed to a targeted one of said device serial interfaces and said serial router is configured for recognizing (he device identification for each device serial interface and directing that specific portion of the serial control-related data to tiie targeted device.

22. The interface aπangement of claim 21 wherein said serial router is further configured for sending the specific portion of said serial control-related data to tiie targeted device without sending the device identification to tiie targeted device serial interface.

23. The interface aπangement of claim 22 wherein each of said devices is operated responsive to a read and write command set that is unique to each device and wherein said serial control-related data is used, at least in part, to selectively assert tiie unique read and write command set to each of said devices.

24. The interface aπangement of claim 23 wherein said host device includes a sequencer that is customizable for tiie read and write command set of each device.

25. The interface anangement of claim 9 wherein said serial router is provided as part of an overall integrated circuit.

26. In a system including an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under (he control of a servo electronics device having a servo serial interface, in cooperation wi(h a read/write electtonics device having a read/write serial interface for control thereof, and a preamp electtonics device having a preamp serial interface for confrol (hereof, such that digital data can be written to or read from said disk responsive to a host device, and said storage arrangement thereby including a pluraUty of devices and associated device serial interfaces, a method comprising the steps of: configuring a primary serial gateway, forming part of the storage aπangement for externally bi-directionally transferring a serial control-related data, which is used in operating said devices; aπanging a host serial interface, as part of the host device in data communication with (he primary serial gateway of (he storage anangement, for applying a serial protocol to the serial control-related data passing between die host device and the storage aπangement; and using a serial router, as part of said storage aπangement and in data coinmunication with said primary serial gateway, to manage said serial control-related data between the primary serial gateway and each of the device serial interfaces.

27. The method of claim 26 wherein said serial conttol-related data includes a series of commands issued by file host device to tiie storage aπangement and wherein said host device is configured for adding a device ID, as part of said serial protocol, to each of said commands, which device ID selectively identifies one of said devices.

28. The method of claim 27 wherein, for a cuπent one of said commands, the host device and the serial router are configured to cooperate to capture the serial gateway for use by the cuπent command prior to the host device issuing a subsequent command

29. The method of claim 27 including the step of configuring an operation definitions section which specifies a command length for each command that is associated with a particular device, as part of said storage aπangement, and causing the host device to track a cunent command on the command length for that command, as part of said serial protocol.

30. The method of claim 29 including the step of Ustening with the host device for a specified number of bits during transfer of said cunent command, until said command length is reached, and, (hereafter, initiating a subsequent command.

31. The method of claim 30 wherein the cuπent command is a write command that is directed to a targeted one of said device serial interfaces, using said device ID, and including the step of forming each write command, including (he cunent command, to include a header portion and a date portion, to cause the targeted device, that is associated with (he targeted device serial interface, to store the data portion at a particular location in the targeted device.

_ 32. The method of claim 30 wherein the cuπent command is a read command that is directed to a targeted one of said device serial interfaces, using said device ED, and including the step of forming each read command, including the cuπent command, to include a header portion and a data portion, such that ⁽he hos( device and the storage aπangement cooperate to send the header portion to a targeted device, that is associated with a targeted device serial interface, to cause the targeted device to use the header portion to read a specific data group from a specific date location within (he targeted device and, (hereafter, the storage aπangement returns the specific data group to the host device as said data portion.

33. The method of claim 26 wherein said serial control-related data includes a series of commands issued by the host device to the storage aπangement and each command is directed to a targeted one of said devices and including the step of forming each command to include a first set of infoπnation that is for use by the storage aπangement, at least for controlling said serial router, and a second set of information that is for internal use by said targeted device.

34. The method of claim 33 including tiie steps of providing a mark bit as part of said first set of information for use in initiating tiie command and further identifying the command as one of a read command and a write command.

35. The method system of claim 34 including the step of adding a device identification to the first set of information (hat indicates (he targeted device.

36. The method of claim 33 including (he step of adding a header portion to the second set of information, which specifies a specific data location in the targeted device, and a date portion for one of reading from or writing to the specific data location.

37. The method of claim 26 including the steps of configuring said host serial interface for applying a device identification to a specific portion of said serial control-related date that is to be directed to a targeted one of said device serial interfaces and configuring said serial router for recognizing the device identification for each device serial interface and directing fhat specific portion of the serial control-related data to the targeted device.

38. The method of claim 37 including the step of further configuring the serial router for sending the specific portion of said serial control-related data to the targeted device without sending the device identification to the targeted device serial interface.

39. The method of claim 38 wherein each of said devices is operated responsive to a read and write command set that is unique to each device and including tiie step of using said serial conttol-related data, at least in part, to selectively assert the unique read and write command set to each of said devices.

40. The method of claim 39 including the steps of providing a sequencer as part of said said host device and customizing the sequencer for the read and write command set of each device.

41. The method of claim 26 including the step of integrating said serial router and the servo device as part of an overaU integrated circuit.

42. In an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the control of a servo electtonics device having a servo serial interface for transferring serial servo date, in cooperation with a read/write electronics device having a read write serial interface for transferring serial read/write data, and a preamp electtonics device having a preamp serial interface for transferring serial preamp data, such (hat user date can be written to or read from said disk, said storage aπangement thereby including a pluraUty of device serial interfaces, each of which is configured for transferring a device specific serial date, a method comprising the steps of: configuring a primary serial gateway for use in externaUy bi-directionaUy fransferring a serial control-related date which is made up of device-specific serial data for operating each of the servo device, (he readwrite device and the preamp device; identifying at least a portion of said serial control-related data that travels through said external serial interface to associate that portion of the serial control-related data with targeted ones of (he device serial interfaces; and configuring a serial router for routing said serial control-related data, based at least in part on the identified portion of tiie serial control-related data, between the external serial interface and each targeted one of the device serial interfaces.

43. In a system including an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the control of a servo device having a servo serial interface, in cooperation with a read/write device having a read/write serial interface for control thereof, and a preamp device having a preamp serial interface for confrol thereof, such (hat digital data can be written to or read fromsaid disk responsive to a host device, and said storage aπangement thereby including a pluraUty of device serial interfaces each of which is associated with a device such that each device is operated responsive to a read and write command set that is unique to that device, an interface aπangement, comprising: a primary serial gateway, forming part of the storage anangement, for electrically interconnecting the storage arrangement to the host device to implement external bi-directional transfer of a serial control-related date which is used in operating each of the servo device, the read/write device and the preamp device; a host serial interface, forming part of the host device and in data communication with the primary serial gateway of (he storage aπangement, configured for use in selectively asserting each read and write command set to each of said devices on said primary serial gateway for use in managing each device and for identifying a command that is asserted by the host device to a targeted one of the devices using a device identification; and a serial router, forming part of said storage aπangement, in selective data communication with each of the device serial interfaces, for using said device identification to direc( die asserted command to the targeted device.

44. The interface aπangement of claim 43 wherein the command that is asserted to the targeted device is a read command and wherein said serial router is configured for passing a read response, originated by the targeted device, back to the host device via the primary serial gateway.

45. The interface anangement of claim 44 wherein the read response includes a predetermined data length and wherein said host device includes a sequencer that is customized to the read and write command set of each device to cause the sequencer to Usten for the read response over a period which conesponds to the predetermined length of (he read response.

46. In a system including an electromechanical digital date storage aπangement having a rotatable disk and an actuator arm for performing write operations to and read operations from said disk under the control of a servo device having a servo serial interface, in cooperation with a read/write device having a read/write serial interface for control thereof, and a preamp device having a preamp serial interface for confrol thereof, such that digital date can be written to or read from said disk responsive to a host device, and said storage aπangement thereby including a pluraUty of device serial interfaces each of which is associated with a device such that each device is operated responsive to a read and write command set that is unique to that device, a method comprising the steps of: forming a primary serial gateway, as part of the storage aπangement, for electricaUy interconnecting the storage aπangement to (he hos( device to implement external bi-directional transfer of a serial control-related date which is used in operating each of the servo device, (he read/write device and the preamp device; configuring a host serial interface, as part of the host device, in date communication with the primary serial gateway of the storage arrangement, for use in selectively asserting each read and write command set to each of said devices on said primary serial gateway for managing each device and for identifying a command that is asserted by the host device to a targeted one of the devices using a device identification; and aπanging a serial router, as part of said storage anangement, in selective data coinmunication with each of the device serial interfaces, for using said device identification to direct the asserted command to (he targeted device.

47. The method of claim 46 wherein tiie command that is asserted to the targeted device is a read command and including tiie step of configuring said serial router for passing a read response, originated by the targeted device, back to the host device via the primary serial gateway.

48. The method of claim 47 wherein the read response includes a predetermined data length and including the steps of providing a sequencer, as part of said host device, and customizing the sequencer to the read and write command set of each device to cause the sequencer to listen for the read response over a period which coπesponds to the predetermined length of the read response.

49. hi an electromechanical digital data storage aπangement having a rotatable disk and an actuator arm for use in elecfromagneticaUy writing user data to tiie disk and for use in elecfromagneticaUy reading the user date from the disk under the control of an electronics aπangement through the use of conttol-related data, and which electronics aπangement is externaUy interfaced for transferring said user date, a data interface aπangement comprising: at least one date line for use in externaUy transferring said user data during said read operations and said write operations; and a configuration for using said date line during operation of the storage aπangement to cany a( leas( a portion of said conttol-related data at a time when said data Une is not carrying said user data.

50. The data interface aπangement of claim 49 wherein said electromechanical digital data storage aπangement performs a start-up procedure that is associated with spinning up said rotatable disk prior to reading and writing the user data and wherein said configuration uses the date line during the start-up procedure.

51. The data interface aπangement of claim 50 wherein said electromechanical digital data storage aπangement includes a spindle motor for rotating said disk under the control of said electronics aπangement and said spindle motor is used to generate a back EMF signal whfle spinning and wherein said data line carries zero crossing data that is generated responsive to the back EMF signal during said start-up procedure.

52. The date interface aπangement of claim 51 wherein said electromechanical digital date storage aπangement includes an additional data line for carrying said user date and said spindle motor is controlled using a commutation signal as part of said conttol-related data and wherein said additional date line carries said commutation signal, as another portion of said control-related data, during said start-up procedure.

53. The dat interface aπangement of claim 50 wherein said electromechanical digital data storage aπangement includes a spindle motor for rotating said disk under the control of said elecfronics aπangement and said spindle motor is controUed using a commutation signal and wherein said data line carries the commutation signal during said start-up procedure.

54. The data interface anangement of claim 49 wherein the date line is an NRZ line.

55. In an electromechanical digital data storage anangement having a rotatable disk and an actuator arm for use in elecfromagneticaUy writing user data to the disk and for use in elecfromagneticaUy reading the user data from the disk under the control of an electronics anangement through the use of conttol-related dat , and which elecfronics aπangement is externally interfaced for transferring said user data, a method comprising (he steps of: providing af least one data line for use in externally transferring said user date during said read operations and said write operations; and using said.data line, during operation of the storage aπangement, to carry at least a portion of said control- related data at a time when said date line is not canying said user date.

56. The method of claim 55 wherein said electromechanical digital date storage aπangement performs a start-up procedure that is associated with spinning up said rotatable disk prior to reading and writing the user data and the step of using tiie data line for canying at least a portion of said conttol-related date is performed during the start-up procedure.

57. The method of claim 56 wherein said electromechanical digital data storage aπangement includes a spindle motor for rotating said disk under the confrol of said electronics aπangement and said spindle motor is used to generate a back EMF signal while spinning and the step of using the data line to carry at least a portion of the control-related date includes the step of transferring a zero crossing date that is generated responsive to the back EMF signal during said start-up procedure.

58. The method of claim 57 wherein said electromechanical digital data storage aπangement includes an additional data line for carrying said user date and said spindle motor is controUed using a commutation signal as part of said conttol-related data and said method includes the step of using the additional data to carry said commutation signal, as another portion of said control-related data, during said start-up procedure.

59. The method of claim 56 wherein said electromechanical digital data storage aπangement includes a spindle motor for rotating said disk under the control of said elecfronics aπangement and said spindle motor is controUed using a commutation signal and the step of using the date line to carry at least a portion of (he conttol-related data includes the step of fransferring the commutation signal during said start-up procedure.

60. The method of claim 55 including the step of using the data line as an NRZ line for transfer of said user data.

61. In an electromechanical digital date storage aπangement including a disk for storing user date thereon which user date is transfeπed through a data port, a method comprising the steps of: providing a serial port for operating the storage aπangement using a bi-directional control-related serial data tha( is clocked using a clock signal; and writing said user data to said disk using said clock signal as a time base reference.

62. In an electromechanical digital data storage aπangement including a disk for storing user date thereon which user date is ttansfeπed through a data port, a configuration conφrising: a serial port for operating the storage aπangement using a bi-directional control-related serial data that is clocked using a clock signal; and ₍ means for using said clock signal as a time base reference for writing said user dat to said disk.

63. In an overaU system including a host device for operational support of an electromechanical storage arrangement, which is provided separate from the host device, and which stores digital date on a rotatable disk, and said host device is provided with a particular firmware configuration for controlling a particular version of the storage arrangement and said storage aπangemen( may he provided in an updated version which requires an updated firmware configuration in the host device, such that the particular firmware configuration, provided with the host device, is limited in controlling the updated version of the storage aπangement, a method comprising the steps of: installing an update set of firmware, tha( coπesponds to differences between the particular firmware configuration and the updated firmware configuration, as part of the updated version of the storage aπangement; configuring the particular firmware configuration of the host device to automaticaUy query, iπespective of the version of the storage arrangement, any storage aπangement with which the hos( device is connected for the presence of said update set of firmware; connecting the host device to an updated version of the storage anangement; and upon detection of said update firmware set responsive to (he query, estebUshing (he updated firmware configuration in tiie host device, based on tiie update firmware set, to cause tiie host device to operate the storage aπangement using the updated firmware configuration

64. The method of claim 63 wherein said update firmware set replaces only a portion of the particular firmware configuration.

65. The method of claim 63 wherein said particular firmware configuration is divided into a plurality of original code segments and said update firmware set includes individual update segments fha( coπespond to individual ones of the plurality of original code segments such that each update segment of the updated firmware configuration replaces one of the original code segments.

66. The method of claim 65 wherein, prior to using any specific one of the original code segments of the particular firmware configuration, the host device performs a query to determine if that specific code segment is replaced by the updated firmware configuration.

67. The method of claim 66 including the step of using a jump table in the step of performing said query such that the jump table specifies each update segment of (he updated firmware configuration.

68. The method of claim 66 wherein, upon determining that the specific code segment has been replaced, the host device executes that specific code segment as provided by the updated firmware configuration.

69. The method of claim 68 wherein (he specific code segment, as part of the updated firmware configuration, includes a different length than that specific code segment, as part of the particular firmware configuration,

70. The method of claim 65 wherein said storage aπangement includes non-volatile elecfronic memory means and wherein the step of instøUing the updated firmware set in the storage aπangement includes the steps of loading a first portion of said code segments into said electronic memory means and a second portion of said code segments onto said disk such (ba(, upon start-up of tiie storage aπangemen(, said firsf portion of the code segments relate to initialization of tiie storage aπangement to, thereafter, enable reading digital data, including said second portion of (he code segments, from the disk.

71. In an overaU system including a host device for operational support of an electromechanical storage anangement, which is provided separate from the host device, and which stores digital date on a rotatable disk, and said host device is provided with a particular firmware configuration for controlling a particular version of the storage arrangement and said storage aπangement may be provided in an updated version which requires an updated firmware configuration in (he hos( device, such that the particular firmware configuration, provided with the host device, is limited in controlling the updated version of the storage aπangement, an aπangement comprising: an update set of firmware, instaUed in said updated version of the storage aπangement, that coπesponds to differences between the particular firmware configuration and the updated_^firmware configuration; first means for causing the host device to automaticaUy query, iπespective of the version of the storage aπangement, any storage aπangement with which the host device is connected for the presence of said update set of firmware; and second means for estebUshing tiie updated firmware configuration in (he hos( device upon detection of said update firmware set responsive to the query, based on the update firmware set, to cause the host device to operate the storage anangement using the updated firmware configuration,

72. The anangement of claim 71 wherein said update firmware set replaces only a portion of the particular firmware configuration

73. The aπangement of claim 71 wherein said particular firmware configuration is divided into a plurality of original code segments and said update firmware set includes individual update segments that coπespond to individual ones of the pluraUty of original code segments such that each update segment of the updated firmware configuration replaces one of the original code segments.

74. The anangement of claim 73 wherein, prior to using any specific one of the original code segments of the particular firmware configuration, the host device is configured to perform a query to determine if that specific code segment is replaced by the updated firmware configuration.

75. The aπangement of claim 74 wherein the updated firmware configuration includes using a jump table to which said query is directed such that the jump table specifies each update segment of the updated firmware configuration.

76. The aπangement of claim 74 wherein, upon determining that tiie specific code segment has been replaced, the host device is configured to execute that specific code segment as provided by the updated firmware configuration.

77. The aπangement of claim 76 wherein the specific code segment, as part of the updated firmware configuration, includes a different length than its coπesponding original code segment, as part of the particular firmware configuration.

78. The aπangement of claim 73 wherein said storage aπangement includes non-volatile electronic memory means for storing a first portion of the update set of firmware as a first group of update code segments and a second portion of said updated firmware set is stored as a second group of update code segments on said disk such that, upon start-up of the storage aπangement, said first portion of the update code segments relate to initialization of the storage aπangement to, thereafter, enable reading digital data, including said second portion of the update code segments, from the disk.

79. In a system including a host device having a host processing aπangement for confrolling the overaU host device and for operational support of an electromechanical storage aπangement, which is initially provided separate from the host device, and which stores digital data on a rotatable disk, and a particular firmware configuration is used for controlling a particular version of the storage aπangement such that a first portion of the particular firmware configuration is required to allow the storage anangement to access any digital data that is stored on the rotatable disk, and said storage anangement may be provided in an updated version which requires an updated firmware configuration that changes at least the first portion of the updated firmware configuration, compared to the first portion of the particular firmware configuration, in a way which would at least Umit access to the digital data that is stored on the rotatable disk, a method comprising the steps of: electricaUy interfacing storage aπangement confrol means with said host processing aπangement of the host device and with (he updated version of the storage aπangement, said storage aπangement confrol means including the particular firmware configuration for controlling the particular version of the storage aπangement; storing a first firmware update in the host device that coπesponds at least to a difference between the first portion of the particular firmware and the first portion of the updated firmware configuration in a way that is accessible to the host processing aπangement; and transferring the first firmware update to the storage anangement control means, using the host processing anangement, in a way that causes the storage aπangement control means to install the first portion of the updated firmware configuration for controlling the storage aπangement.

80. The method of claim 79 including the step of storing a second firmware update on the rotatable disk, approximately at a time of manufacture of the storage aπangement, coπesponding to an additional difference between a second portion of the particular firmware configuration, as compared to a second portion of the updated firmware configuration, and (he step of accessing (he second firmware update, using the storage aπangemen( control means, after installing the firsf portion of tiie updated firmware configuration to install the second portion of the updated firmware configuration.

81. In a system including a host device having a host processing aπangement for confroUing the overaU host device and for operational support of an electromechanical storage anangement, which is initially provided separate from the host device, and which stores digital data on a rotatable disk, and a particular firmware configuration is used for confroUing a particular version of the storage aπangemen( such (ha( a firsf portion of the particular firmware configuration is required to allow the storage aπangement to access any digital data that is stored on the rotatable disk, and said storage aπangement may be provided in an updated version which requires an updated firmware configuration that changes at least the first portion of the updated firmware configuration, compared to the first portion of the particular firmware configuration, in a way which would at least limit access to the digital data that is stored on the rotatable disk, a firmware control aπangement, comprising: storage aπangement control means electricaUy interfaced with said host processing aπangement of the host device and with tiie updated version of the storage aπangement, said storage anangement confrol means including the particular firmware configuration for confrolling the particular version of the storage aπangement; a firmware update stored in the host device that coπesponds at least to a difference between the first portion of the particular firmware and the first portion of the updated firmware configuration in a way that is accessible to the host processing aπangement; and means for transferring the firmware update to the storage aπangement confrol means, using the host processing aπangement, in a way that causes the storage aπangement control means to, thereafter, execute the first portion of the updated firmware configuration in confroUing the storage aπangement.

82. The firmware control aπangement of claim 81 wherein a second firmware update is stored on the rotatable disk, approximately at a time of manufacture of the storage aπangement, coπesponding to an additional difference between a second portion of the particular firmware configuration, as compared to a second portion of the updated firmware configuration, and said storage aπangement confrol means is configured for accessing the second firmware update, using the storage aπangement confrol means, after installing the first portion of the updated firmware configuration to install the second portion of the updated firmware configuration.