WO2004107433A1 - Apparatus and method for photo-thermal dopant activation in semiconductors - Google Patents

Apparatus and method for photo-thermal dopant activation in semiconductors Download PDF

Info

Publication number
WO2004107433A1
WO2004107433A1 PCT/US2004/016385 US2004016385W WO2004107433A1 WO 2004107433 A1 WO2004107433 A1 WO 2004107433A1 US 2004016385 W US2004016385 W US 2004016385W WO 2004107433 A1 WO2004107433 A1 WO 2004107433A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor workpiece
chamber
source
ozone
workpiece
Prior art date
Application number
PCT/US2004/016385
Other languages
French (fr)
Inventor
Emil Kamieniecki
Original Assignee
Accent Optical Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Accent Optical Technologies, Inc. filed Critical Accent Optical Technologies, Inc.
Publication of WO2004107433A1 publication Critical patent/WO2004107433A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the present invention generally relates to semiconductor processing, characterization, and evaluation. More specifically, aspects of the invention relate to preparation of a near-surface region of a semiconductor to facilitate in-line, real-time monitoring of processes involved in the manufacturing of semiconductor devices. Some implementations of the invention have particular utility in connection with measuring electrical characteristics of thin semiconductor films and sub-surface layers in bulk silicon wafers, e.g., measuring doping concentration of these films and layers.
  • Akazawa which discloses a method for cleaning a surface of a semiconductor substrate without providing a damaged layer to the surface thereof;
  • U.S. Patent No. 5,470,799 issued 28 November 1995 in the names of H. Itoh, M. Iwasaki, A. Tokui, and K. Tsukamoto, which discloses a method for removing a natural gas film or contaminant adhering on a surface of a silicon semiconductor substrate;
  • j U.S. Patent No. 5,716,495, issued 10 February 1998 in the names of J.W. Butterbaugh and D.C. Grey which discloses a method for removing native oxide and other contaminants from a wafer surface while minimizing the loss of a desired film;
  • hydrogen can be introduced by diffusion from ambient gas [2,3], during chemomechanical polishing of the wafer [7,8], by wet and dry etching, during ion implantation [9], and during growth of epitaxial silicon layers. Hydrogen passivation is particularly problematic in near-surface region of the silicon wafer since hydrogen can penetrate this region relatively easily. Investigators observed some time ago that heating the sample in a vacuum restores most, if not all, of the sample's resistivity prior to hydrogen exposure [2,3].
  • Figure 1 is a schematic cross-sectional view of a wafer-processing chamber in accordance with an embodiment of the invention in which the semiconductor workpiece is oriented generally horizontally.
  • Figure 1A is a schematic, enlarged cross-sectional view of a semiconductor workpiece taken from the area labeled "Fig. 1A" in Figure 1.
  • Figure 2 schematic cross-sectional view of a wafer-processing chamber in accordance with an embodiment of the invention wherein the semiconductor workpiece is oriented generally vertically.
  • Figure 3 is a graph comparing surface charge retention for a sample that has been treated according to an embodiment of the invention with surface charge retention for a sample that has not been so treated.
  • Figure 4 is a graph comparing process in accordance with an embodiment of the present invention.
  • semiconductor workpiece is used herein to refer to articles comprising semiconductors that may be used in or comprise all or part of a microelectronic component.
  • semiconductor workpieces include, but are not limited to, substantially pure silicon wafers, silicon wafers including one or more layers of integrated circuitry (e.g., a wafer including a plurality of completed or partially completed microelectronic component dies or photodiodes), and dies singulated from a wafer.
  • Aspects of the invention have particular utility in connection with semiconductor workpieces that comprise silicon, but may find use in other semiconductor workpieces, as well.
  • a method in accordance with one embodiment of the invention relates to treating a semiconductor workpiece, which comprises silicon, to stably activate a hydrogen-deactivated dopant in a near-surface region of the semiconductor workpiece.
  • This method includes positioning a semiconductor workpiece in a chamber; heating the near-surface region of the semiconductor workpiece at an elevated treatment temperature; oxidizing a surface of the semiconductor workpiece overlying the near- surface region with ozone at the treatment temperature; and generating electron-hole pairs in the near-surface region.
  • Another embodiment of the invention provides a method of treating a semiconductor workpiece that comprises silicon.
  • This method includes positioning a semiconductor workpiece in a chamber with a first surface facing a first direction, a second surface facing a generally opposite second direction, and a doped region subjacent the first surface.
  • the doped region of the semiconductor workpiece is heated at a treatment temperature of about 150-500° C using a heat source juxtaposed with the second surface of the semiconductor workpiece.
  • Ozone is delivered to the chamber to react with the first surface of the semiconductor workpiece and the semiconductor workpiece is irradiated at a wavelength of 1 ⁇ m or less, e.g., by using a radiation source emitting at least a majority of its energy in a wavelength range less than 1 ⁇ m.
  • a semiconductor workpiece treatment system in another embodiment includes a workpiece support, an ozone source, a heat source, and a radiation source.
  • the workpiece support is configured to support a semiconductor workpiece within a chamber.
  • the ozone source may deliver ozone from outside the chamber to an interior of the chamber.
  • the heat source is positioned with respect to the workpiece support to heat a semiconductor workpiece supported on the workpiece support.
  • the radiation source emits radiation in a wavelength adapted to generate electron-hole pairs in a surface region of the semiconductor workpiece.
  • the heat source may be spaced from the radiation source, e.g., the heat and radiation sources may be disposed on opposite sides of a semiconductor workpiece supported by the workpiece support.
  • a semiconductor workpiece treatment system that also includes a workpiece support, an ozone source, a heat source, and a radiation source.
  • the heat source may be configured to be in physical or fluid communication with a semiconductor workpiece supported on the workpiece support.
  • the radiation source emits radiation in a wavelength adapted to generate electron-hole pairs in a surface region of the semiconductor workpiece.
  • the radiation source may contribute no more than about 20%, e.g., 10% or less, of the heat delivered to the wafer.
  • a further embodiment of the invention includes a chamber configured to receive a semiconductor workpiece; an ozone source; a heat source, a temperature gauge, means for generating electron-hole pairs in a surface region of the semiconductor workpiece, and a controller.
  • the heat source may be configured to deliver heat to a semiconductor workpiece positioned in the chamber and the temperature gauge may be adapted to determine a temperature within the chamber, e.g., a temperature of the semiconductor workpiece.
  • the controller is operatively coupled to the heat source and the temperature gauge and may be programmed to control the heat source to heat the semiconductor workpiece to a temperature of at least about 150° C and no greater than about 450° C.
  • the controller desirably is adapted to control the heat source substantially independently of the means for generating electron-hole pairs.
  • the first section describes dopant activation systems for semiconductor workpieces in accordance with certain embodiments of the invention.
  • the second section outlines methods of treating semiconductor workpieces in accordance with other embodiments of the invention.
  • FIGS. 1 and 2 schematically illustrate two alternative embodiments of semiconductor workpiece treatment systems in accordance with the invention.
  • the semiconductor workpiece treatment system 10 of Figure 1 generally includes a chamber 20, a workpiece support 30, an ozone source 40, a heat source 50, and a radiation source 60.
  • the walls 22 of the chamber 20 define an interior 24 that is sized to receive a semiconductor workpiece 12.
  • the chamber may be slightly larger than 300 mm in diameter. This chamber 20 may be sealed to limit the ingress of gases and particulates that might damage the semiconductor workpiece 12.
  • the workpiece support 30 comprises a plurality of pins or raised contacts 32 that contact a back surface 18 ( Figure 1A) of the semiconductor workpiece 12 at spaced-apart locations.
  • the heat source 50 includes a hot plate 52 with a confronting surface 54 that is juxtaposed with the semiconductor workpiece back surface 18.
  • the contacts 32 may be spaced about the confronting surface 54 to hold the back surface 18 of the semiconductor workpiece generally parallel to the confronting surface 54 at a suitable distance, e.g., 1 mm or less.
  • the contacts 32 are omitted and the semiconductor workpiece back surface 18 may rest directly on the hot plate confronting surface 54.
  • the heat source 50 which includes the hot plate 52, may be used to heat the semiconductor workpiece 12.
  • the heater 50 may heat the workpiece 12 primarily by conduction, by convection, or by a combination of conduction and convection.
  • the hot plate 52 may generate some energy as infrared radiation, it is anticipated that infrared radiation will play a relatively minor role in heating the workpiece 12 at the operating temperatures currently contemplated.
  • the hot plate 52 of the heat source 50 is operatively coupled to a power supply 56. Suitable hot plates 52 and power supplies 56 are widely commercially available from a variety of sources.
  • the semiconductor workpiece treatment system 10 of Figure 1 also includes an ozone supply 40.
  • the ozone supply 40 may be positioned outside the chamber. Ozone from the ozone supply 40 may be delivered to the interior 24 of the chamber 20 by a suitable delivery line 44.
  • the delivery line 44 of Figure 1 includes a selectively controllable valve 42 that may be used to selectively initiate and terminate flow of ozone into the chamber 20.
  • the valve 42 can be controlled to vary the flow rate of ozone into the chamber over a suitable range to maintain the ozone concentration in the interior 24 of the chamber 20 within targeted parameters, discussed below.
  • Ozone sources suitable for use in the ozone supply 40 are commercially available from a variety of suppliers, such as BMT MESSTECHNIK GMBH Berlin, Argentinische Allee 32a, D-14163 Berlin, Germany (e.g., Ozone Generator model BMT 802 or BMT 803); Ozone Systems & Technology International, Inc., P.O. Box 3320, Monterey, CA 93940, USA; and Hongin Co., Ltd., Sungwoo Bldg. 5F.75-2, Yangjae- Dong, Seocho-ku Seoul, Korea (e.g., model LAB 802).
  • the semiconductor workpiece treatment system 10 also includes a radiation source 60.
  • This radiation source emits radiation in a wavelength that is adapted to generate electron-hole pairs in a near-surface region (16 in Figure 1A) of the semiconductor workpiece 12.
  • the system 10 of Figure 1 includes a radiation source 60 to achieve this objective, any other suitable means for generating electron- hole pairs may be used instead.
  • the semiconductor workpiece 12 may be subjected to an electrical bias that lowers the surface potential barrier of the workpiece surface 14 ( Figure 1A). This bias may be applied instead of or in conjunction with radiation from a radiation source 60.
  • the radiation source 60 of Figure 1 employs a plurality of lamps 62 arranged in a lamp envelope 64.
  • the lamp envelope 64 may be sealed from the treatment chamber 20 by a barrier 65 that transmits the desired wavelengths of radiation from the lamps 62 to the chamber 20.
  • the barrier may comprise a quartz or fused quartz window; such windows are well known in the field.
  • the lamps 62 are connected to a power supply 66. All of the lamps may be connected to a common power supply or each of the lamps may be provided with a separately controllable power supply.
  • a fan 68 may be used to cool the lamp envelope 64 to prevent overheating of the lamps 62.
  • the lamps 62 generate radiation in a wavelength range that generates electron-hole pairs in a near-surface region (16 in Figure 1A) of the semiconductor workpiece 12.
  • the appropriate wavelength depends on the nature of the semiconductor workpiece being tested, particularly on the band gap of the material. For a typical silicon wafer, for example, radiation at a wavelength below about 1 ⁇ m will typically suffice. Although a monochromatic light source could be used, it is anticipated that the radiation source will emit radiation across a range of wavelengths. Desirably, however, at least a majority of the radiation from the lamps 62 will have a wavelength no longer than the wavelength corresponding to the band gap of the semiconductor material being treated.
  • the lamps 62 may be arc lamps, e.g., sodium or mercury arc lamps, that tend to emit more energy as short wavelength radiation, e.g., UV light, and less energy in longer wavelengths, e.g., infrared radiation.
  • the heat source 50 and the radiation source 60 are spaced from one another.
  • the confronting surface 54 of the hot plate 52 is juxtaposed with the back surface 18 ( Figure 1A) of the semiconductor workpiece 12 while the radiation source 60 irradiates the front surface 14 ( Figure 1A) of the workpiece 12.
  • the radiation will generate electron-hole pairs in the near-surface region 16 ( Figure 1A), but the heater 50 can be controlled largely independently of the intensity of the radiation from the lamps 62.
  • the programmable controller 70 may comprise a programmable computer, e.g., a personal computer or an ASIC-based system.
  • the controller is operatively coupled to the control valve 42 of the ozone supply 40, the power supply 56 of the heat source 50, and the power supply 66 (and, optionally, the fan 68) of the radiation source 60.
  • the controller 70 may also be coupled to a thermocouple (shown schematically at 72 in Figure 1) so it may monitor the temperature of the semiconductor workpiece 12 during treatment.
  • FIG. 2 schematically illustrates a semiconductor workpiece treatment system 110 in accordance with another embodiment of the invention.
  • Analogous components of the two systems 10 and 110 bear like reference numerals, but those in Figure 2 are increased by 100.
  • the system 10 of Figure 1 employs a controller 70 and the system 110 of Figure 2 includes an analogous controller 170.
  • the semiconductor workpiece treatment system 110 differs from the system 10 of Figure 1 in several respects.
  • the semiconductor workpiece 12 is oriented generally vertically in Figure 2.
  • the workpiece support 130 of Figure 2 includes a plurality of peripheral members 132 that supportingly engage a periphery of the workpiece 12 to maintain a generally vertical orientation.
  • This support 130 may extend around and engage substantially the entire periphery of the semiconductor workpiece, effectively dividing the interior 124 of the chamber 122 into an activating region 123 between the semiconductor workpiece and the barrier 165 of the radiation source 160 and a heating plenum 155 on the back side 18 ( Figure 1A) of the semiconductor workpiece.
  • the heat supply 150 employs heated gas to heat the semiconductor workpiece by convection instead of a hot plate.
  • the gas may be any suitable gas, but preferably includes relatively little or no hydrogen. In one embodiment, the gas is substantially hydrogen-free. An inert gas such as dry nitrogen is expected to suffice. In other embodiments, the heated gas may comprise heated air. Heated gas is directed through the heating plenum 155 to heat the semiconductor workpiece 12 by convection. The temperature of the semiconductor workpiece can be controlled by varying the temperature and/or flow rate of the gas in the plenum 155.
  • the radiation source 160 of Figure 2 includes two different sets of lamps 162a and 162b, each of which is powered by a separate power supply 166a and 166b, respectively.
  • the first set of lamps 162a may comprise halogen lamps and the second set of lamps 162b may comprise arc lamps, e.g., sodium or mercury arc lamps.
  • all of the lamps 162 are the same type of lamp, e.g., they may all be mercury arc lamps.
  • the ozone source 40 was located outside the chamber 20 and delivered the ozone to the interior of the chamber.
  • the ozone source 140 comprises a source of oxygen.
  • the UV radiation from the arc lamps 162b interacts with the oxygen to form ozone in situ in the activating region 123 of the chamber 120. This avoids the need to have an external ozone generator, but it may also limit the concentration of ozone in the activating region 123. If needed to achieve the targeted ozone concentration proximate the front surface 14 ( Figure 1A) of the semiconductor workpiece 12, the oxygen of the ozone source 140 may also include ozone.
  • inventions provide methods of treating semiconductor workpieces, e.g., by activating a dopant that has been deactivated by hydrogen.
  • a dopant that has been deactivated by hydrogen.
  • One embodiment of the invention provides a method for treating a semiconductor workpiece to stably activate a dopant in a near-surface region 16 of the semiconductor workpiece 12.
  • This method has particular utility for reactivating dopants, e.g., boron, that have been deactivated by hydrogen, e.g., dopants in a CVD-deposited epitaxial silicon layer or in a near-surface region of a semiconductor workpiece treated with HF.
  • two or more semiconductor workpieces can be treated at once in a batch process, e.g., by positioning them side-by-side on the hot plate 52 or by positioning a wafer carrier with a stack of wafers inside the chamber 20.
  • An alternative embodiment treats a single wafer at a time in the chamber 20.
  • the at least partially deactivated semiconductor workpiece may be positioned on the workpiece support 30 in the interior 24 of the chamber 20, e.g., using a robotic wafer transporter.
  • the semiconductor workpiece 12 may be heated until at least the near-surface region 16 reaches a desired treatment temperature.
  • the interior of the chamber 20 may be maintained heated between successive workpieces 12 so the next workpiece is introduced to an environment that is- already preheated to at least the target temperature.
  • the controller 70 can monitor the temperature of the workpiece 12 via the thermocouple 72 and adjust power delivered to the semiconductor workpiece by the heat source 50 to achieve and maintain the desired treatment temperature.
  • the treatment temperature at which the semiconductor workpiece is heated is desirably at least about 150° C and no greater than about 500° C.
  • the treatment temperature is about 150-450° C, preferably about 150-350° C, e.g., 250- 350° C This treatment temperature is believed sufficient to achieve the desired degree of dopant activation while avoiding some of the undesirable consequences of heating some semiconductor workpieces at temperatures greater than about 450-500° C.
  • the ozone in the chamber 20 from the ozone source 40 will react with the surface 14 of the semiconductor workpiece 12.
  • the ozone may oxidize the semiconductor material and clean any organic residue from the workpiece surface 14.
  • the workpiece 12 is a silicon wafer, for example, the ozone can oxidize the silicon at the surface 14 of the wafer and break down any contaminants on the surface 14. This yields a silicon oxide (SiO x ) layer on the surface 14 overlying the near-surface region 14. It is believed that this SiO x layer is fairly amorphous, but it may be polycrystalline.
  • heating a semiconductor material can activate hydrogen-deactivated dopants such as boron by dissociating the dopant and the hydrogen, e.g., breaking BH down into B " and H + . Irradiating the surface 14 of the workpiece 12 will produce electron-hole pairs at or subjacent the surface 14. This allows minority carriers (electrons in p-type semiconductors) to accumulate at the surface and, in turn, reduce the surface potential barrier. Doing so while the hydrogen is dissociated from the dopant is believed to allow the hydrogen to diffuse toward the surface and into the oxide layer.
  • the heating, oxidizing, and radiation processes may be conducted in a variety of sequences.
  • the surface of the semiconductor workpiece 12 may first be oxidized, then the semiconductor workpiece may be heated and irradiated.
  • the workpiece 12 may be oxidized by exposing the semiconductor to ambient air for an extended period of time, or by treating the surface with an oxidizing solution such as a mix of ammonium hydroxide and hydrogen peroxide. More preferably, though, the oxide layer is formed by exposure to ozone as discussed above.
  • the workpiece 12 may be positioned in a pre- heated chamber 12 and irradiated by the radiation source 60 and the control valve 42 on the ozone source 40 may be opened to deliver ozone to the chamber 20.
  • the workpiece 12 may be treated in this fashion for a treatment period that may range from about 30 seconds to 10 minutes.
  • a treatment period may range from about 30 seconds to 10 minutes.
  • lower temperatures and lower radiation intensities will lengthen the desired treatment period; higher temperatures and/or higher radiation intensities tend to achieve the intended objective in a shorter treatment period.
  • dopant activated in accordance with an embodiment of the invention remains activated for a very long time, perhaps even permanently.
  • the present inventor speculates that the dissociated hydrogen in the near-surface region becomes trapped or bound in a high-stress interface region where the bulk semiconductor ends and the oxide layer begins. The inventor further theorizes that irradiating the workpiece and forming the oxide layer simultaneously at the elevated treatment temperature may bind the hydrogen even more tightly than it might be bound if the workpiece were first oxidized then heated and irradiated.
  • a 200 mm silicon wafer having an epitaxial silicon layer of about 3 ⁇ m doped with boron at a nominal concentration of about 1 x 10 16 cm "3 was given an initial surface charge by corona charging.
  • the surface charge of the wafer was then monitored over a period of about 90 seconds. This process was conducted three times, with the initial surface charge differing between the three tests.
  • the wafer was positioned on a wafer support 30 of a semiconductor workpiece treatment system generally as shown in Figure 1 and treated at a temperature of about 300° C for a treatment time of about 10 minutes.
  • Ozone was generated in the ozone source 40 from a flow rate of about 3 liters of O 2 /min.
  • FIG. 1 illustrates the surface charge as a function of time for each of the wafer measurements.
  • the surface charge in each of the first three samples dropped off quite sharply from the initial surface charge, with most of the surface charge disappearing in the first 10-15 seconds. By about 30 seconds, each of these samples leveled off at a surface charge about an order of magnitude less than the initial surface charge.
  • the surface charge for the wafer treated in accordance with aspects of the invention remained substantially constant (in this case varying by well under 5%) over the entire 90-second period over which it was measured. It is anticipated that this surface charge will remain substantially constant, e.g., it will not change by more than 5%, over a period exceeding two minutes, likely an hour or longer. (Other factors, e.g., application of an external electrical field, could significantly impact this result.
  • the anticipated surface charge stability is based on an assumption that the semiconductor workpiece will be placed in a dry inert gas environment promptly following the treatment in the chamber 20.
  • the AC-SPV/G value was significantly higher; this value corresponded to about 5.5 x10 15 /cm 3 for both of these measurements.
  • This wafer was then treated or "conditioned” in accordance with an embodiment of the invention.
  • the wafer was treated at a temperature of about 250° C for about 10 minutes with an ozone concentration in the chamber interior 24 of about 20 g/m 3 during the treatment time.
  • the dopant concentration curve for this "re-conditioned" wafer is close to the curve for the initial measurement, with an average dopant concentration of about 9.9x10 15 /cm 3 . (In this particular test, it is believed that the initial measurement was inaccurate; if the initial measurement were more accurate, it is expected that the initial and re-conditioned curves would be much closer to one another.)
  • the stability of the active dopant in semiconductor workpieces treated in accordance with an embodiment of the invention is substantially longer than one skilled in the art would expect.
  • a boron dopant in conventional silicon can be deactivated relatively quickly; in this example, the active boron concentration dropped over 40% in less than 5 hours.
  • the concentration of an active dopant (e.g., active boron) in a semiconductor workpiece (e.g., a silicon wafer) treated in accordance with an embodiment of the invention can remain substantially constant (e.g., changing by no more than 15%) for at least 45 days, e.g., 60 days or longer when stored in a dry inert gas environment, which may be substantially hydrogen-free.
  • the active dopant concentration is expected to change by no more than 15% under such storage conditions for 120 days or longer.

Abstract

This disclosure provides apparatus and methods for permanently activating dopants in semiconductors, e.g., silicon wafers. One such method treats a semiconductor workpiece, which comprises silicon, to stably activate a hydrogen-deactivated dopant in a near-surface region of the semiconductor workpiece. This method includes positioning a semiconductor workpiece (12) in a chamber (20) and heating the near-­surface region (14) of the semiconductor workpiece at an elevated treatment temperature, e.g., 150-500° C. A surface of the semiconductor workpiece overlying the near-surface region is oxidized with ozone at the treatment temperature and electron­hole pairs are generated in the near surface region, e.g., using a radiation source (60). In some implementations, this has been found to yield a surprisingly stable surface charge and a dopant that can retain its activated state for an extended period of time.

Description

APPARATUS AND METHOD FOR PHOTO-THERMAL DOPANT ACTIVATION IN SEMICONDUCTORS
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of United States Provisional Application No, 60/472,915, filed 23 May 2003 and entitled "APPARATUS AND METHOD FOR PHOTO-THERMAL DOPANT ACTIVATION IN SEMICONDUCTORS," the entirety of which is incorporated herein by reference.
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, characterization, and evaluation. More specifically, aspects of the invention relate to preparation of a near-surface region of a semiconductor to facilitate in-line, real-time monitoring of processes involved in the manufacturing of semiconductor devices. Some implementations of the invention have particular utility in connection with measuring electrical characteristics of thin semiconductor films and sub-surface layers in bulk silicon wafers, e.g., measuring doping concentration of these films and layers.
BIBLIOGRAPHY
Patent Documents
Known patents relating to photo-thermal treatment of semiconductor surfaces include: U.S. Patent No. 6,325,078 B2, issued 4 December 2001 in the name of E. Kamieniecki, which discloses an apparatus for surface treating a semiconductor wafer; U.S. Patent No. 4,871 ,417, issued 3 October 1989 in the names of H. Nishizawa, M. Morita, and M. Tanaka, which discloses a method for surface treating of thin substrates such as semiconductor wafers; U.S. Patent No. 5,306,671 , issued 26 April 1994 in the names of T. Ogawa, H. Morita, T. Ishida, K. Kawai, and M. Akazawa, which discloses a method for cleaning a surface of a semiconductor substrate without providing a damaged layer to the surface thereof; U.S. Patent No. 5,470,799, issued 28 November 1995 in the names of H. Itoh, M. Iwasaki, A. Tokui, and K. Tsukamoto, which discloses a method for removing a natural gas film or contaminant adhering on a surface of a silicon semiconductor substrate; j U.S. Patent No. 5,716,495, issued 10 February 1998 in the names of J.W. Butterbaugh and D.C. Grey, which discloses a method for removing native oxide and other contaminants from a wafer surface while minimizing the loss of a desired film; and
U.S. Patent No. 6,168,961 B1 , issued 2 January 2001 in the name of G. Vaccari, which discloses a process for evaluating a silicon wafer having an n-type or a p-type 0 epitaxial layer on its surface.
Other Publications
Known publications relating to photo-thermal treatment of semiconductor surfaces include:
1. C.T. Sah, J.Y.C. Sun, and J.J.T. Tzou, Appl. Phys. Lett., Vol. 43 (1983), p. 204 5 and J. Appl. Phys., Vol. 54 (1983), p. 5864;
2. J.I. Pankove, D.E. Carlson, J.E. Berkeyheiser, and R.O. Wance, "Neutralization of shallow acceptor levels in silicon by atomic hydrogen," Phys. Rev. Lett., Vol. 51 (1983), pp. 2224-2225;
3. J.I. Pankove, R.O. Wance, and J.E. Berkeyheiser, "Neutralization of acceptors in 0 silicon by atomic hydrogen," Appl. Phys. Lett., Vol. 45 (1984), pp. 1100-1102;
4. J.I. Pankove, P.J. Zancucchi, and CW. Magee, "Hydrogen localization near boron in silicon," Appl. Phys. Lett., Vol. 46 (1985), pp. 421-423;
5. N.M. Johnson, C. Herring, and D.J. Chadi, Phys. Rev. Lett., Vol. 56 (1986), p. 769.
6. S . Pantalides, "Hydrogen diffusion and hydrogen-dopant reactions in crystalline 5 silicon," Defects in Semiconductors, ed. H.J. von Bardeleben, Material Science
Forum Vol. 10-12 (1986), pp. 573-578;
7. A. Schnegg, H. Prigge, M. Grundner, P.O. Hahn, and H. Jacob, Meter. Res. Soc. Symp. Proc, Vol. 104 (1988), p. 291 ;
8. H. Prigge, P. Gerlach, P.O. Hahn, A. Schnegg, and H. Jacob, J. Electrochem. 0 Soc, Vol. 138 (1991 ), p. 1385; 9. CH. Seager, R.A. Anderson, and J.K.G. Panitz, "The diffusion of hydrogen in silicon and mechanism for 'unintentional' hydrogenation during ion beam processing," J. Mater. Res., Vol. 2 (1987), pp. 96-106;
10. E. Kamieniecki and G. Foggiato, "Analysis and control of electrically active contaminants by Surface Charge Analysis," Handbook of Semiconductor Wafer
Cleaning Technology, Part IV-11 , Ed. W. Kern, Noyes Publications (1993), pp. 497-536;
11. P. Roman, M. Brubaker, J. Staffa, E. Kamieniecki, and J. Ruzyllo, "Non-Contact Monitoring of Electrical Characteristics of Silicon Surface and Near-Surface Region," Proc. 1998 Intern. Conf. Characterization and Metrology for ULSI
Technology, NIST, Gaithersburg, Maryland, Mar. 23-27, 1998;
12. P. Roman, J. Staffa, S. Fakhouh, M. Brubaker, J. Ruzyllo, K. Torek, and E. Kamieniecki, "Surface dopant concentration monitoring using noncontact surface charge profiling," J. Appl. Phys., Vol. 83 (1998), pp. 2297-2300; and 13. J. Ruzyllo, G.T. Durenko, and . . Hoff, "Preoxidation UV treatment of silicon wafers," J. Electrochem. Soc, Vol. 134 (1987), pp. 2052-2055.
The entirety of each of the patents and other publications identified in this application, including those listed above, are incorporated herein by reference.
BACKGROUND Precise knowledge of silicon wafer electrical characteristics can greatly enhance process control in the manufacture of integrated circuits. Of particular importance are electrical characteristics, particularly concentration of dopants, in the near-surface region in which integrated circuits (ICs) are formed. However, the presence of other ions, especially hydrogen, in various phases of production can deactivate these dopants. Determining accurate concentrations of dopants in a near- surface region of the wafer may require activation of the deactivated dopants. The need to activate these dopants has impeded development of practical equipment for commercially effective real-time metrology.
Sah and coworkers observed that hydrogen could passivate shallow acceptors in semiconductor materials. [1] These authors attributed a drastic increase in resistivity of a near-surface p-type silicon layer to hydrogen diffusion into the silicon layer. Subsequent experiments by Pankove et al. [2-4] confirmed that hydrogen deactivates shallow acceptors. Johnson et al. [5] has shown that hydrogen also partially passivates n-type silicon. In 1986 Pantalides [6] analyzed experimental data and suggested a mechanism by which hydrogen passivation occurs.
Several conventional steps in the manufacture of ICs of can introduce hydrogen into silicon. For instance, hydrogen can be introduced by diffusion from ambient gas [2,3], during chemomechanical polishing of the wafer [7,8], by wet and dry etching, during ion implantation [9], and during growth of epitaxial silicon layers. Hydrogen passivation is particularly problematic in near-surface region of the silicon wafer since hydrogen can penetrate this region relatively easily. Investigators observed some time ago that heating the sample in a vacuum restores most, if not all, of the sample's resistivity prior to hydrogen exposure [2,3]. More recent research has established that a mild thermal anneal in ambient air at temperatures ranging between 150°C and 250°C (e.g., annealing at 200°C for 15-30 min) can dissociate B-H complexes, which are responsible for boron deactivation, and substantially restoring pre-hydrogenation conditions [9-12].
A number of researchers [9,12] indicated that once the B-H (boron-hydrogen) complexes located in the depletion layer dissociate due to the thermal annealing, the electric field present in the region causes the positively charged hydrogen to drift away from the surface region towards the silicon bulk. During wafer storage this hydrogen could diffuse back towards the surface and again deactivate boron. This suggests that effectiveness of the long-term boron activation, either by thermal or photo-thermal method, is dependent on the surface condition, and specifically on the presence of the surface depletion layer. Therefore, presence of the oxide could assure that, independent of initial surface conditions, doping activation may have a long-term effect. Many conventional approaches simply heat the wafer with a hot plate or in a furnace. United States Patent 6,325,078 B2, however, suggests heating the wafer on a hot plate instead of using infrared radiation (IR) and illuminating it only with radiation generating electron-hole pairs at the surface. Even so, this patent does not disclose a method that would allow substantially permanent dissociation of B-H complexes as the hydrogen may diffuse back to the boron vicinity and deactivate it again. Deactivation by this returning hydrogen can be particularly problematic for epitaxial films freshly removed from the epi-growing reactor and for wafers treated with hydrofluoric acid to remove oxide from the surface. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic cross-sectional view of a wafer-processing chamber in accordance with an embodiment of the invention in which the semiconductor workpiece is oriented generally horizontally. Figure 1A is a schematic, enlarged cross-sectional view of a semiconductor workpiece taken from the area labeled "Fig. 1A" in Figure 1.
Figure 2 schematic cross-sectional view of a wafer-processing chamber in accordance with an embodiment of the invention wherein the semiconductor workpiece is oriented generally vertically. Figure 3 is a graph comparing surface charge retention for a sample that has been treated according to an embodiment of the invention with surface charge retention for a sample that has not been so treated.
Figure 4 is a graph comparing process in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION A. Overview
Various embodiments of the present invention provide systems and methods for treating semiconductor workpieces. The term "semiconductor workpiece" is used herein to refer to articles comprising semiconductors that may be used in or comprise all or part of a microelectronic component. By way of example, semiconductor workpieces include, but are not limited to, substantially pure silicon wafers, silicon wafers including one or more layers of integrated circuitry (e.g., a wafer including a plurality of completed or partially completed microelectronic component dies or photodiodes), and dies singulated from a wafer. Aspects of the invention have particular utility in connection with semiconductor workpieces that comprise silicon, but may find use in other semiconductor workpieces, as well.
A method in accordance with one embodiment of the invention relates to treating a semiconductor workpiece, which comprises silicon, to stably activate a hydrogen-deactivated dopant in a near-surface region of the semiconductor workpiece. This method includes positioning a semiconductor workpiece in a chamber; heating the near-surface region of the semiconductor workpiece at an elevated treatment temperature; oxidizing a surface of the semiconductor workpiece overlying the near- surface region with ozone at the treatment temperature; and generating electron-hole pairs in the near-surface region.
Another embodiment of the invention provides a method of treating a semiconductor workpiece that comprises silicon. This method includes positioning a semiconductor workpiece in a chamber with a first surface facing a first direction, a second surface facing a generally opposite second direction, and a doped region subjacent the first surface. The doped region of the semiconductor workpiece is heated at a treatment temperature of about 150-500° C using a heat source juxtaposed with the second surface of the semiconductor workpiece. Ozone is delivered to the chamber to react with the first surface of the semiconductor workpiece and the semiconductor workpiece is irradiated at a wavelength of 1 μm or less, e.g., by using a radiation source emitting at least a majority of its energy in a wavelength range less than 1 μm.
A semiconductor workpiece treatment system in another embodiment includes a workpiece support, an ozone source, a heat source, and a radiation source. The workpiece support is configured to support a semiconductor workpiece within a chamber. The ozone source may deliver ozone from outside the chamber to an interior of the chamber. The heat source is positioned with respect to the workpiece support to heat a semiconductor workpiece supported on the workpiece support. The radiation source emits radiation in a wavelength adapted to generate electron-hole pairs in a surface region of the semiconductor workpiece. The heat source may be spaced from the radiation source, e.g., the heat and radiation sources may be disposed on opposite sides of a semiconductor workpiece supported by the workpiece support.
Another embodiment of the invention provides a semiconductor workpiece treatment system that also includes a workpiece support, an ozone source, a heat source, and a radiation source. The heat source may be configured to be in physical or fluid communication with a semiconductor workpiece supported on the workpiece support. The radiation source emits radiation in a wavelength adapted to generate electron-hole pairs in a surface region of the semiconductor workpiece. The radiation source may contribute no more than about 20%, e.g., 10% or less, of the heat delivered to the wafer.
A further embodiment of the invention includes a chamber configured to receive a semiconductor workpiece; an ozone source; a heat source, a temperature gauge, means for generating electron-hole pairs in a surface region of the semiconductor workpiece, and a controller. The heat source may be configured to deliver heat to a semiconductor workpiece positioned in the chamber and the temperature gauge may be adapted to determine a temperature within the chamber, e.g., a temperature of the semiconductor workpiece. The controller is operatively coupled to the heat source and the temperature gauge and may be programmed to control the heat source to heat the semiconductor workpiece to a temperature of at least about 150° C and no greater than about 450° C. The controller desirably is adapted to control the heat source substantially independently of the means for generating electron-hole pairs.
For ease of understanding, the following discussion is broken down into two areas of emphasis. The first section describes dopant activation systems for semiconductor workpieces in accordance with certain embodiments of the invention. The second section outlines methods of treating semiconductor workpieces in accordance with other embodiments of the invention.
B. Semiconductor Dopant Activation Systems Figures 1 and 2 schematically illustrate two alternative embodiments of semiconductor workpiece treatment systems in accordance with the invention. The semiconductor workpiece treatment system 10 of Figure 1 generally includes a chamber 20, a workpiece support 30, an ozone source 40, a heat source 50, and a radiation source 60. The walls 22 of the chamber 20 define an interior 24 that is sized to receive a semiconductor workpiece 12. For example, if the semiconductor workpiece 12 comprises a 300 mm silicon wafer, the chamber may be slightly larger than 300 mm in diameter. This chamber 20 may be sealed to limit the ingress of gases and particulates that might damage the semiconductor workpiece 12.
The semiconductor workpiece may be supported in the chamber 20 in a variety of ways. In the embodiment shown in Figure 1 , the workpiece support 30 comprises a plurality of pins or raised contacts 32 that contact a back surface 18 (Figure 1A) of the semiconductor workpiece 12 at spaced-apart locations. In this particular implementation, the heat source 50 includes a hot plate 52 with a confronting surface 54 that is juxtaposed with the semiconductor workpiece back surface 18. The contacts 32 may be spaced about the confronting surface 54 to hold the back surface 18 of the semiconductor workpiece generally parallel to the confronting surface 54 at a suitable distance, e.g., 1 mm or less. On other embodiments, the contacts 32 are omitted and the semiconductor workpiece back surface 18 may rest directly on the hot plate confronting surface 54.
The heat source 50, which includes the hot plate 52, may be used to heat the semiconductor workpiece 12. In the illustrated embodiment wherein the hot plate 52 is positioned within the interior 24 of the chamber 20 in close proximity with the workpiece 12, the heater 50 may heat the workpiece 12 primarily by conduction, by convection, or by a combination of conduction and convection. Although the hot plate 52 may generate some energy as infrared radiation, it is anticipated that infrared radiation will play a relatively minor role in heating the workpiece 12 at the operating temperatures currently contemplated. The hot plate 52 of the heat source 50 is operatively coupled to a power supply 56. Suitable hot plates 52 and power supplies 56 are widely commercially available from a variety of sources.
The semiconductor workpiece treatment system 10 of Figure 1 also includes an ozone supply 40. The ozone supply 40 may be positioned outside the chamber. Ozone from the ozone supply 40 may be delivered to the interior 24 of the chamber 20 by a suitable delivery line 44. The delivery line 44 of Figure 1 includes a selectively controllable valve 42 that may be used to selectively initiate and terminate flow of ozone into the chamber 20. In a preferred embodiment, the valve 42 can be controlled to vary the flow rate of ozone into the chamber over a suitable range to maintain the ozone concentration in the interior 24 of the chamber 20 within targeted parameters, discussed below. Ozone sources suitable for use in the ozone supply 40 are commercially available from a variety of suppliers, such as BMT MESSTECHNIK GMBH Berlin, Argentinische Allee 32a, D-14163 Berlin, Germany (e.g., Ozone Generator model BMT 802 or BMT 803); Ozone Systems & Technology International, Inc., P.O. Box 3320, Monterey, CA 93940, USA; and Hongin Co., Ltd., Sungwoo Bldg. 5F.75-2, Yangjae- Dong, Seocho-ku Seoul, Korea (e.g., model LAB 802).
The semiconductor workpiece treatment system 10 also includes a radiation source 60. This radiation source emits radiation in a wavelength that is adapted to generate electron-hole pairs in a near-surface region (16 in Figure 1A) of the semiconductor workpiece 12. Although the system 10 of Figure 1 includes a radiation source 60 to achieve this objective, any other suitable means for generating electron- hole pairs may be used instead. In one alternative embodiment, the semiconductor workpiece 12 may be subjected to an electrical bias that lowers the surface potential barrier of the workpiece surface 14 (Figure 1A). This bias may be applied instead of or in conjunction with radiation from a radiation source 60.
The radiation source 60 of Figure 1 employs a plurality of lamps 62 arranged in a lamp envelope 64. As is known in the art, the lamp envelope 64 may be sealed from the treatment chamber 20 by a barrier 65 that transmits the desired wavelengths of radiation from the lamps 62 to the chamber 20. For example, the barrier may comprise a quartz or fused quartz window; such windows are well known in the field. The lamps 62 are connected to a power supply 66. All of the lamps may be connected to a common power supply or each of the lamps may be provided with a separately controllable power supply. A fan 68 may be used to cool the lamp envelope 64 to prevent overheating of the lamps 62.
As noted previously, the lamps 62 generate radiation in a wavelength range that generates electron-hole pairs in a near-surface region (16 in Figure 1A) of the semiconductor workpiece 12. The appropriate wavelength depends on the nature of the semiconductor workpiece being tested, particularly on the band gap of the material. For a typical silicon wafer, for example, radiation at a wavelength below about 1 μm will typically suffice. Although a monochromatic light source could be used, it is anticipated that the radiation source will emit radiation across a range of wavelengths. Desirably, however, at least a majority of the radiation from the lamps 62 will have a wavelength no longer than the wavelength corresponding to the band gap of the semiconductor material being treated.
As explained below, it is useful in some embodiments of the invention to employ a radiation source that contributes relatively little heating of the semiconductor workpiece, e.g., 20% or less of the heat delivered to the semiconductor workpiece during treatment. Conventional halogen lamps 62 can meet this objective with appropriate control of the power supply 66. In other embodiments, however, the lamps 62 may be arc lamps, e.g., sodium or mercury arc lamps, that tend to emit more energy as short wavelength radiation, e.g., UV light, and less energy in longer wavelengths, e.g., infrared radiation. In the embodiment of Figure 1 , the heat source 50 and the radiation source 60 are spaced from one another. In particular, the confronting surface 54 of the hot plate 52 is juxtaposed with the back surface 18 (Figure 1A) of the semiconductor workpiece 12 while the radiation source 60 irradiates the front surface 14 (Figure 1A) of the workpiece 12. As a consequence, the radiation will generate electron-hole pairs in the near-surface region 16 (Figure 1A), but the heater 50 can be controlled largely independently of the intensity of the radiation from the lamps 62.
The programmable controller 70 may comprise a programmable computer, e.g., a personal computer or an ASIC-based system. The controller is operatively coupled to the control valve 42 of the ozone supply 40, the power supply 56 of the heat source 50, and the power supply 66 (and, optionally, the fan 68) of the radiation source 60. The controller 70 may also be coupled to a thermocouple (shown schematically at 72 in Figure 1) so it may monitor the temperature of the semiconductor workpiece 12 during treatment.
Figure 2 schematically illustrates a semiconductor workpiece treatment system 110 in accordance with another embodiment of the invention. Analogous components of the two systems 10 and 110 bear like reference numerals, but those in Figure 2 are increased by 100. For example, the system 10 of Figure 1 employs a controller 70 and the system 110 of Figure 2 includes an analogous controller 170.
The semiconductor workpiece treatment system 110 differs from the system 10 of Figure 1 in several respects. For example, the semiconductor workpiece 12 is oriented generally vertically in Figure 2. The workpiece support 130 of Figure 2 includes a plurality of peripheral members 132 that supportingly engage a periphery of the workpiece 12 to maintain a generally vertical orientation. This support 130 may extend around and engage substantially the entire periphery of the semiconductor workpiece, effectively dividing the interior 124 of the chamber 122 into an activating region 123 between the semiconductor workpiece and the barrier 165 of the radiation source 160 and a heating plenum 155 on the back side 18 (Figure 1A) of the semiconductor workpiece.
The heat supply 150 employs heated gas to heat the semiconductor workpiece by convection instead of a hot plate. The gas may be any suitable gas, but preferably includes relatively little or no hydrogen. In one embodiment, the gas is substantially hydrogen-free. An inert gas such as dry nitrogen is expected to suffice. In other embodiments, the heated gas may comprise heated air. Heated gas is directed through the heating plenum 155 to heat the semiconductor workpiece 12 by convection. The temperature of the semiconductor workpiece can be controlled by varying the temperature and/or flow rate of the gas in the plenum 155. The radiation source 160 of Figure 2 includes two different sets of lamps 162a and 162b, each of which is powered by a separate power supply 166a and 166b, respectively. In one embodiment, the first set of lamps 162a may comprise halogen lamps and the second set of lamps 162b may comprise arc lamps, e.g., sodium or mercury arc lamps. In an alternative implementation, all of the lamps 162 are the same type of lamp, e.g., they may all be mercury arc lamps.
In the system 10 of Figure 1, the ozone source 40 was located outside the chamber 20 and delivered the ozone to the interior of the chamber. In Figure 2, the ozone source 140 comprises a source of oxygen. The UV radiation from the arc lamps 162b interacts with the oxygen to form ozone in situ in the activating region 123 of the chamber 120. This avoids the need to have an external ozone generator, but it may also limit the concentration of ozone in the activating region 123. If needed to achieve the targeted ozone concentration proximate the front surface 14 (Figure 1A) of the semiconductor workpiece 12, the oxygen of the ozone source 140 may also include ozone.
C Methods of Treating Semiconductor Workpieces
Other embodiments of the invention provide methods of treating semiconductor workpieces, e.g., by activating a dopant that has been deactivated by hydrogen. In the following discussion of such methods, reference is made to the semiconductor workpiece treatment system 10 shown in Figure 1 and the semiconductor workpiece 12 shown in Figure 1A. This is solely for purposes of illustration and the following methods are not limited to use of the particular structures or systems shown in the drawings or discussed above.
One embodiment of the invention provides a method for treating a semiconductor workpiece to stably activate a dopant in a near-surface region 16 of the semiconductor workpiece 12. This method has particular utility for reactivating dopants, e.g., boron, that have been deactivated by hydrogen, e.g., dopants in a CVD-deposited epitaxial silicon layer or in a near-surface region of a semiconductor workpiece treated with HF. In one embodiment, two or more semiconductor workpieces can be treated at once in a batch process, e.g., by positioning them side-by-side on the hot plate 52 or by positioning a wafer carrier with a stack of wafers inside the chamber 20. An alternative embodiment treats a single wafer at a time in the chamber 20. The at least partially deactivated semiconductor workpiece may be positioned on the workpiece support 30 in the interior 24 of the chamber 20, e.g., using a robotic wafer transporter. The semiconductor workpiece 12 may be heated until at least the near-surface region 16 reaches a desired treatment temperature. The interior of the chamber 20 may be maintained heated between successive workpieces 12 so the next workpiece is introduced to an environment that is- already preheated to at least the target temperature. The controller 70 can monitor the temperature of the workpiece 12 via the thermocouple 72 and adjust power delivered to the semiconductor workpiece by the heat source 50 to achieve and maintain the desired treatment temperature. The treatment temperature at which the semiconductor workpiece is heated is desirably at least about 150° C and no greater than about 500° C. In one embodiment, the treatment temperature is about 150-450° C, preferably about 150-350° C, e.g., 250- 350° C This treatment temperature is believed sufficient to achieve the desired degree of dopant activation while avoiding some of the undesirable consequences of heating some semiconductor workpieces at temperatures greater than about 450-500° C.
At the treatment temperature, the ozone in the chamber 20 from the ozone source 40 will react with the surface 14 of the semiconductor workpiece 12. Depending on the nature and condition of the semiconductor workpiece 12, the ozone may oxidize the semiconductor material and clean any organic residue from the workpiece surface 14. If the workpiece 12 is a silicon wafer, for example, the ozone can oxidize the silicon at the surface 14 of the wafer and break down any contaminants on the surface 14. This yields a silicon oxide (SiOx) layer on the surface 14 overlying the near-surface region 14. It is believed that this SiOx layer is fairly amorphous, but it may be polycrystalline. As is known in the literature, heating a semiconductor material can activate hydrogen-deactivated dopants such as boron by dissociating the dopant and the hydrogen, e.g., breaking BH down into B" and H+. Irradiating the surface 14 of the workpiece 12 will produce electron-hole pairs at or subjacent the surface 14. This allows minority carriers (electrons in p-type semiconductors) to accumulate at the surface and, in turn, reduce the surface potential barrier. Doing so while the hydrogen is dissociated from the dopant is believed to allow the hydrogen to diffuse toward the surface and into the oxide layer. The heating, oxidizing, and radiation processes may be conducted in a variety of sequences. For example, the surface of the semiconductor workpiece 12 may first be oxidized, then the semiconductor workpiece may be heated and irradiated. In such an embodiment, the workpiece 12 may be oxidized by exposing the semiconductor to ambient air for an extended period of time, or by treating the surface with an oxidizing solution such as a mix of ammonium hydroxide and hydrogen peroxide. More preferably, though, the oxide layer is formed by exposure to ozone as discussed above.
In one particularly useful embodiment, all three of these processes may be carried out simultaneously. For example, the workpiece 12 may be positioned in a pre- heated chamber 12 and irradiated by the radiation source 60 and the control valve 42 on the ozone source 40 may be opened to deliver ozone to the chamber 20. The workpiece 12 may be treated in this fashion for a treatment period that may range from about 30 seconds to 10 minutes. Generally speaking, lower temperatures and lower radiation intensities will lengthen the desired treatment period; higher temperatures and/or higher radiation intensities tend to achieve the intended objective in a shorter treatment period.
As explained below, conventionally activating dopant in a doped region of a silicon wafer by heating the wafer yields only short-lived reactivation; the surface charge of the wafer, for example, may quickly drop off again when the wafer is allowed to cool. Surprisingly, dopant activated in accordance with an embodiment of the invention remains activated for a very long time, perhaps even permanently. Without intending to be bound by this theory, the present inventor speculates that the dissociated hydrogen in the near-surface region becomes trapped or bound in a high-stress interface region where the bulk semiconductor ends and the oxide layer begins. The inventor further theorizes that irradiating the workpiece and forming the oxide layer simultaneously at the elevated treatment temperature may bind the hydrogen even more tightly than it might be bound if the workpiece were first oxidized then heated and irradiated.
Certain aspects of the invention are highlight in the following experimental examples. These examples are intended to be merely illustrative and should not be deemed to limit the invention to the specific parameters or conditions listed therein. Experimental Example I
A 200 mm silicon wafer having an epitaxial silicon layer of about 3 μm doped with boron at a nominal concentration of about 1 x 1016 cm"3 was given an initial surface charge by corona charging. The surface charge of the wafer was then monitored over a period of about 90 seconds. This process was conducted three times, with the initial surface charge differing between the three tests. Thereafter, the wafer was positioned on a wafer support 30 of a semiconductor workpiece treatment system generally as shown in Figure 1 and treated at a temperature of about 300° C for a treatment time of about 10 minutes. ' Ozone was generated in the ozone source 40 from a flow rate of about 3 liters of O2/min. to produce an ozone concentration in the chamber interior 24 of about 20 g/m3 during the treatment time. The wafer was allowed to cool to ambient temperature in a substantially hydrogen-free environment and was given an initial surface charge by corona charging. The surface charge of the wafer was then monitored over a period of about 90 seconds. Figure 3 illustrates the surface charge as a function of time for each of the wafer measurements. The surface charge in each of the first three samples dropped off quite sharply from the initial surface charge, with most of the surface charge disappearing in the first 10-15 seconds. By about 30 seconds, each of these samples leveled off at a surface charge about an order of magnitude less than the initial surface charge. Surprisingly, the surface charge for the wafer treated in accordance with aspects of the invention remained substantially constant (in this case varying by well under 5%) over the entire 90-second period over which it was measured. It is anticipated that this surface charge will remain substantially constant, e.g., it will not change by more than 5%, over a period exceeding two minutes, likely an hour or longer. (Other factors, e.g., application of an external electrical field, could significantly impact this result. The anticipated surface charge stability is based on an assumption that the semiconductor workpiece will be placed in a dry inert gas environment promptly following the treatment in the chamber 20. It is also assumed that no external electrical or magnetic field will be applied to the semiconductor workpiece during the period of substantial stability.) Surface charging is sometimes used to characterize a concentration of dopant in a near-surface region of a semiconductor workpiece (see, e.g., co-pending International Application No. PCT/US03/40069). The semiconductor workpieces that were not treated in accordance with the invention rapidly lost their initial surface charge, making reliable measurements highly dependent on the exact time of the measurement. As a result, characterization of semiconductor workpieces using such conventional measurements is subject to significant inaccuracy and imprecision. The longer-term stability of the surface charge for a semiconductor workpiece treated in accordance with the invention permits more accurate and precise characterization of such semiconductor workpieces.
Experimental Example II
The boron concentration profile of a 200 mm silicon wafer similar to that used in Experimental Example I was measured using a system substantially as shown and described in co-pending International Application No. PCT/US03/40069, which designated the United States and is incorporated herein in its entirety by reference. (In this graph, AC-SPV is the alternating current surface photovoltage and G is the light- induced generation rate of carriers. These values are described in more detail in the identified international application.) This initial profile, shown as the lower curve in Figure 4, suggested an average dopant concentration of about 9.9x1015/cm3. The profile was again measured after the wafer was allowed to sit at about 25° C in ambient air for about 3 hours and again after about 4.5 hours. As shown by the two upper curves, the AC-SPV/G value was significantly higher; this value corresponded to about 5.5 x1015/cm3 for both of these measurements. This wafer was then treated or "conditioned" in accordance with an embodiment of the invention. In particular, the wafer was treated at a temperature of about 250° C for about 10 minutes with an ozone concentration in the chamber interior 24 of about 20 g/m3 during the treatment time. As suggested in Figure 4, the dopant concentration curve for this "re-conditioned" wafer is close to the curve for the initial measurement, with an average dopant concentration of about 9.9x1015/cm3. (In this particular test, it is believed that the initial measurement was inaccurate; if the initial measurement were more accurate, it is expected that the initial and re-conditioned curves would be much closer to one another.)
Current investigation suggests that the stability of the active dopant in semiconductor workpieces treated in accordance with an embodiment of the invention is substantially longer than one skilled in the art would expect. As suggested in Figure 4, a boron dopant in conventional silicon can be deactivated relatively quickly; in this example, the active boron concentration dropped over 40% in less than 5 hours. In contrast, the inventor currently believes that the concentration of an active dopant (e.g., active boron) in a semiconductor workpiece (e.g., a silicon wafer) treated in accordance with an embodiment of the invention can remain substantially constant (e.g., changing by no more than 15%) for at least 45 days, e.g., 60 days or longer when stored in a dry inert gas environment, which may be substantially hydrogen-free. In some embodiments, the active dopant concentration is expected to change by no more than 15% under such storage conditions for 120 days or longer.
The above-detailed embodiments and examples are intended to be illustrative, not exhaustive, and those skilled in the art will recognize that various equivalent modifications are possible within the scope of the invention. For example, whereas steps are presented in a given order, alternative embodiments may perform steps in a different order. The various embodiments described herein can be combined to provide further embodiments. In general, the terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification unless the preceding description explicitly defines such terms. The inventors reserve the right to add additional claims after filing the application to pursue additional claim forms for other aspects of the invention.

Claims

CLAIMSI/We claim:
1. A method of treating a semiconductor workpiece, which comprises silicon, to stably activate a hydrogen-deactivated dopant in a near-surface region of the semiconductor workpiece, comprising: positioning a semiconductor workpiece in a chamber; heating the near-surface region of the semiconductor workpiece at an elevated treatment temperature; oxidizing a surface of the semiconductor workpiece overlying the near-surface region with ozone at the treatment temperature; and generating electron-hole pairs in the near-surface region.
2. The method of claim 1 wherein the treatment temperature is about 150-500° C
3. The method of claim 1 wherein the treatment temperature is about 150-450° C
4. The method of claim 1 wherein the treatment temperature is about 150-350° C.
5. The method of claim 1 wherein the treatment temperature is about 250-350° C.
6. The method of claim 1 wherein the treatment temperature is about 250-350° C and the semiconductor workpiece is treated at the treatment temperature for about 0.5-10 minutes.
7. The method of claim 1 wherein the semiconductor workpiece is treated at the treatment temperature for about 0.5-10 minutes and a surface charge of the first surface changes by no more than about 5% over a period of at least 90 seconds promptly following the treatment in a dry inert gas environment without application of an external electrical field.
8. The method of claim 1 wherein the semiconductor workpiece is treated at the treatment temperature for about 0.5-10 minutes and the doped region of the semiconductor workpiece comprises an activated dopant, and further wherein a concentration of the activated dopant after the treatment changes by no more than about 15% when stored in a dry inert gas environment for 45 days.
9. The method of claim 1 further comprising removing the semiconductor workpiece from the chamber after the heating, the oxidizing, and generating the electron-hole pairs, wherein the dopant comprises boron and a concentration of activated boron in the near-surface region remains substantially stable after the semiconductor workpiece is removed from the chamber.
10. The method of claim 1 wherein the ozone is delivered from an ozone supply positioned outside the chamber.
1 1 , The method of claim 1 wherein generating the electron-hole pairs comprises radiating the semiconductor workpiece with radiation having a wavelength range, wherein wavelengths no greater than about 1 micron provide a majority of an intensity of the radiation.
12. The method of claim 1 wherein a halogen lamp is used to generate the electron- hole pairs.
13. The method of claim 1 wherein an arc lamp is used to generate the electron-hole pairs.
14. The method of claim 1 wherein a radiation source is used to generate the electron- hole pairs and the radiation source contributes no more than 20% of the heat delivered to the semiconductor workpiece during heating of the semiconductor workpiece at the treatment temperature.
15. The method of claim 1 wherein a radiation source is used to generate the electron- hole pairs and the radiation source contributes no more than 10% of the heat delivered to the semiconductor workpiece during heating of the semiconductor workpiece at the treatment temperature.
16. A method of treating a semiconductor workpiece that comprises silicon, the method comprising: positioning a semiconductor workpiece in a chamber with a first surface facing a first direction, a second surface facing a generally opposite second direction, and a doped region subjacent the first surface; heating the doped region of the semiconductor workpiece at a treatment temperature of about 150-500° C using a heat source juxtaposed with the second surface of the semiconductor workpiece; delivering ozone to the chamber to react with the first surface of the semiconductor workpiece; and irradiating the semiconductor workpiece at a wavelength of 1 μm or less.
17. The method of claim 16 wherein the treatment temperature is about 150-350° C.
18. The method of claim 16 wherein the treatment temperature is about 250-350° C.
19. The method of claim 16 wherein the doped region of the semiconductor workpiece prior to the treatment includes a dopant that has been at least partially deactivated.
20. The method of claim 16 further comprising removing the semiconductor workpiece from the chamber after the heating, delivering the ozone, and the irradiation, wherein the doped region of the semiconductor workpiece comprises boron and the doped region has a substantially stable concentration of activated boron after the semiconductor workpiece is removed from the chamber.
21. The method of claim 16 wherein the semiconductor workpiece is treated at the treatment temperature for about 0.5-10 minutes and the doped region of the semiconductor workpiece comprises an activated dopant, and further wherein a concentration of the activated dopant in the doped region after the treatment changes by no more than about 15% when stored in a dry inert gas environment for 45 days.
22. The method of claim 16 wherein the semiconductor workpiece is treated at the treatment temperature for about 0.5-10 minutes and a surface charge of the first surface changes by no more than about 5% over a period of at least two minutes promptly following the treatment in a dry inert gas environment without application of an external field.
23. The method of claim 16 wherein the ozone is delivered from an ozone supply positioned outside the chamber.
24. The method of claim 16 wherein a halogen lamp is used to generate the electron- hole pairs.
25. The method of claim 16 wherein the semiconductor workpiece is irradiated with a radiation source that contributes no more than 20% of the heat delivered to the semiconductor workpiece during heating of the semiconductor workpiece at the treatment temperature.
26. The method of claim 16 wherein irradiating the semiconductor workpiece generates electron-hole pairs in the doped region of the semiconductor workpiece.
27. A semiconductor workpiece treatment system comprising: a workpiece support configured to support a semiconductor workpiece within a chamber; an ozone source that delivers ozone from outside the chamber to an interior of the chamber; a heat source positioned with respect to the workpiece support to heat a semiconductor workpiece supported on the workpiece support; and a radiation source emitting radiation in a wavelength adapted to generate electron- hole pairs in a surface region of the semiconductor workpiece, the heat source being spaced from the radiation source.
28. The system of claim 27 wherein the heat source is configured to heat the semiconductor workpiece primarily by conduction, by convection, or by conduction and convection.
29. The system of claim 27 wherein the heat source is in physical or fluid communication with the semiconductor workpiece.
30. The system of claim 27 wherein the heat source comprises a hot plate.
31. The system of claim 27 wherein the heat source is positioned within the chamber.
32. The system of claim 27 wherein the heat source has a heated surface positioned to be no farther than about one mm from a confronting surface of the semiconductor workpiece.
33. The system of claim 27 wherein the heat source is disposed on one side of the semiconductor workpiece and the radiation source primarily illuminates an opposite side of the semiconductor workpiece.
34. The system of claim 27 wherein the radiation source comprises a halogen lamp.
35. The system of claim 27 wherein the radiation source comprises an arc lamp.
36. The system of claim 27 further comprising a programmable controller operatively connected to the heat source and the radiation source, the controller being programmed to control power delivered to the radiation source such that the radiation source contributes no more than 20% of the heat delivered to the semiconductor workpiece.
37. The system of claim 27 wherein the ozone source is configured to maintain an ozone concentration in the chamber of at least about 10 g/m3.
38. The system of claim 27 wherein the ozone source is configured to maintain an ozone concentration in the chamber of about 10-40 g/m3.
39. A semiconductor workpiece treatment system comprising: a workpiece support configured to support a semiconductor workpiece within a chamber; an ozone source; a heat source configured to be in physical or fluid communication with a semiconductor workpiece supported on the workpiece support; and a radiation source emitting radiation in a wavelength adapted to generate electron- hole pairs in a surface region of the semiconductor workpiece, the radiation source contributing no more than about 20% of the heat delivered to the wafer.
40. The system of claim 39 wherein the radiation source comprises a source of UV radiation and the ozone source comprises an oxygen source that is optionally supplemented with ozone, and wherein the UV radiation and a flow rate of gas from the oxygen source are controlled to maintain an ozone concentration within the chamber of about 10-40 g/m3.
41. The system of claim 39 wherein the ozone source comprises an ozone source external to the chamber but in fluid communication with the chamber.
42. The system of claim 39 wherein the ozone source is configured to maintain an ozone concentration in the chamber of at least about 10 g/m3.
43. The system of claim 39 wherein the ozone source is configured to maintain an ozone concentration in the chamber of about 10-40 g/m3.
44. The system of claim 39 wherein the heat source comprises a hot plate.
45. The system of claim 39 wherein the heat source is positioned within the chamber
46. The system of claim 39 wherein the heat source is disposed on one side of the semiconductor workpiece and the radiation source primarily illuminates an opposite side of the semiconductor workpiece.
47. The system of claim 39 wherein the radiation source comprises a halogen lamp.
48. The system of claim 39 further comprising a programmable controller operatively connected to the heat source and the radiation source, the controller being programmed to control power delivered to the radiation source such that the radiation source contributes no more than 20% of the heat delivered to the semiconductor workpiece.
49. A semiconductor workpiece treatment system comprising: a chamber configured to receive a semiconductor workpiece; an ozone source; a heat source configured to deliver heat to a semiconductor workpiece positioned in the chamber; a temperature gauge adapted to determine a temperature within the chamber; 5 a means for generating electron-hole pairs in a surface region of the semiconductor workpiece; and a controller operatively coupled to the heat source and the temperature gauge and programmed to control the heat source to heat the semiconductor workpiece to a temperature of at least about 150° C and no greater than about 450° C, ■10 the controller being adapted to control the heat source substantially independently of the means for generating electron-hole pairs.
50. The system of claim 49 wherein the controller is programmed to control the heat source to heat the semiconductor workpiece to a temperature of no greater than about 350° C.
75 51. The system of claim 49 wherein the controller is programmed to control the heat source to heat the semiconductor workpiece to a temperature of about 250-350° C.
52. The system of claim 49 wherein the means for generating electron-hole pairs comprises a radiation source that directs radiation toward a surface of the
20 semiconductor workpiece.
53. The system of claim 49 wherein the means for generating electron-hole pairs comprises a halogen lamp.
54. The system of claim 49 wherein the heat source has a heated surface positioned to be no farther than about one mm from a confronting surface of the
25 semiconductor workpiece.
PCT/US2004/016385 2003-05-23 2004-05-24 Apparatus and method for photo-thermal dopant activation in semiconductors WO2004107433A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47291503P 2003-05-23 2003-05-23
US60/472,915 2003-05-23

Publications (1)

Publication Number Publication Date
WO2004107433A1 true WO2004107433A1 (en) 2004-12-09

Family

ID=33490537

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/016385 WO2004107433A1 (en) 2003-05-23 2004-05-24 Apparatus and method for photo-thermal dopant activation in semiconductors

Country Status (1)

Country Link
WO (1) WO2004107433A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015010168A1 (en) * 2013-07-26 2015-01-29 Newsouth Innovations Pty Limited Thermal processing in silicon
WO2015010167A1 (en) * 2013-07-26 2015-01-29 Newsouth Innovations Pty Limited High concentration doping in silicon
WO2017079168A1 (en) * 2015-11-04 2017-05-11 The Regents Of The University Of California Iii-nitride tunnel junction with modified p-n interface

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168642A (en) * 1983-03-15 1984-09-22 Nec Corp Oxidizing device for semiconductor substrate
US5178682A (en) * 1988-06-21 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate and apparatus therefor
US5693578A (en) * 1993-09-17 1997-12-02 Fujitsu, Ltd. Method of forming thin silicon oxide film with high dielectric breakdown and hot carrier resistance
US5723383A (en) * 1994-03-25 1998-03-03 Nippon Telegraph And Telephone Corporation Semiconductor substrate treatment method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168642A (en) * 1983-03-15 1984-09-22 Nec Corp Oxidizing device for semiconductor substrate
US5178682A (en) * 1988-06-21 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate and apparatus therefor
US5693578A (en) * 1993-09-17 1997-12-02 Fujitsu, Ltd. Method of forming thin silicon oxide film with high dielectric breakdown and hot carrier resistance
US5723383A (en) * 1994-03-25 1998-03-03 Nippon Telegraph And Telephone Corporation Semiconductor substrate treatment method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0090, no. 19 (E - 292) 25 January 1985 (1985-01-25) *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015010168A1 (en) * 2013-07-26 2015-01-29 Newsouth Innovations Pty Limited Thermal processing in silicon
WO2015010167A1 (en) * 2013-07-26 2015-01-29 Newsouth Innovations Pty Limited High concentration doping in silicon
CN105474364A (en) * 2013-07-26 2016-04-06 新南创新私人有限公司 High concentration doping in silicon
KR20160039635A (en) * 2013-07-26 2016-04-11 뉴사우스 이노베이션즈 피티와이 리미티드 High concentration doping in silicon
CN105493296A (en) * 2013-07-26 2016-04-13 新南创新私人有限公司 Thermal processing in silicon
US9824897B2 (en) 2013-07-26 2017-11-21 Newsouth Innovations Pty Limited Thermal processing in silicon
US9947821B2 (en) 2013-07-26 2018-04-17 Newsouth Innovations Pty Limited High concentration doping in silicon
TWI625769B (en) * 2013-07-26 2018-06-01 新南創新有限公司 High concentration doping in silicon
AU2014295816B2 (en) * 2013-07-26 2018-09-13 Newsouth Innovations Pty Limited High concentration doping in silicon
KR102289901B1 (en) * 2013-07-26 2021-08-18 뉴사우스 이노베이션즈 피티와이 리미티드 High concentration doping in silicon
WO2017079168A1 (en) * 2015-11-04 2017-05-11 The Regents Of The University Of California Iii-nitride tunnel junction with modified p-n interface

Similar Documents

Publication Publication Date Title
US6803588B2 (en) Apparatus and method for rapid photo-thermal surfaces treatment
TW417225B (en) Process for the preparation of epitaxial wafers for resistivity measurements
KR20170128360A (en) Processing method of silicon material
Correra et al. Incoherent‐light‐flash annealing of phosphorus‐implanted silicon
WO2004107433A1 (en) Apparatus and method for photo-thermal dopant activation in semiconductors
Cummings et al. Rapid annealing of GaAs: Uniformity and temperature dependence of activation
Conway et al. Thermal pulse annealing of boron‐implanted HgCdTe
Lee Rapid thermal processing of silicon solar cells: passivation and diffusion
Hazdra et al. The influence of implantation temperature and subsequent annealing on residual implantation defects in silicon
US9939511B2 (en) Surface photovoltage calibration standard
Fiory Methods in microelectronics for rapid thermal annealing of implanted dopants
Seager Hydrogenation methods
RU2069414C1 (en) Method for doping silicon with chalcogens
Correra et al. Annealing of phosphorus implanted silicon by incoherent light scanning
Kumar et al. Effect of swift heavy ion irradiation on deep levels in Au∕ n-Si (100) Schottky diode studied by deep level transient spectroscopy
Yukhymchyk et al. RF plasma effect on amorphous thin ion-implanted layers of n-and p-type germanium: Raman and AFM research
Fiory et al. Photothermal activation of shallow dopants implanted in silicon
Larsen et al. Annealing of arsenic-and antimony-implanted silicon single crystals using a CW xenon arc lamp
Maydell-Ondrusz Transient electron beam annealing of arsenic implanted silicon
Yoo et al. Comprehensive Characterization of B+ Implanted Silicon after Rapid Thermal Annealing
Sobolev et al. Structural and luminescent properties of electron-irradiated silicon
Alford et al. Low temperature dopant activation using variable frequency microwave annealing
Castaldini et al. Surface damage in processed silicon
Ransom et al. DLTS characterization of N-type silicon after Rapid Thermal Annealing of Boron Implantation
Akano et al. Annealing and activation of Si implanted InP

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPEN Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101)
122 Ep: pct application non-entry in european phase