WO2004109644A1 - Display device addressing method - Google Patents

Display device addressing method Download PDF

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Publication number
WO2004109644A1
WO2004109644A1 PCT/IB2004/050798 IB2004050798W WO2004109644A1 WO 2004109644 A1 WO2004109644 A1 WO 2004109644A1 IB 2004050798 W IB2004050798 W IB 2004050798W WO 2004109644 A1 WO2004109644 A1 WO 2004109644A1
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WO
WIPO (PCT)
Prior art keywords
row
electrodes
voltage
data signal
applying
Prior art date
Application number
PCT/IB2004/050798
Other languages
French (fr)
Inventor
Roel Van Woudenberg
Franciscus P. M. Budzelaar
Original Assignee
Koninklijke Philips Electronics N.V.
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Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP04735305A priority Critical patent/EP1634269A1/en
Publication of WO2004109644A1 publication Critical patent/WO2004109644A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/3473—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on light coupled out of a light guide, e.g. due to scattering, by contracting the light guide with external means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames

Definitions

  • the present invention relates to method for addressing a display device having a set of row electrodes and a set of column electrodes for addressing a plurality of pixels defined by intersections of said electrodes.
  • the invention also relates to a display driver for implementing such a method, and a display device comprising such a driver.
  • Such displays are normally referred to as "bi- stable" displays, and are typically addressed with passive matrix addressing.
  • the dynamic foil display as described in e.g. WOOO/38163 is an example of such a display.
  • the switching curves of a pixel element of the display in WOOO/38163 is shown in Fig. 1, where the x- and y-axis represent the row and column voltages respectively.
  • V row For a suitable row voltage level (V row ,unsei), the state of the pixel cannot be switched (neither ON nor OFF) by changing the column voltage level between V co i, S eioN and V 00 ⁇ jSe ⁇ oFF, but maintains its present state.
  • This memory effect makes it possible to use a passive matrix addressing method to drive the display.
  • addressing is performed in the following way. First, all pixels are erased, e.g. by applying a high voltage to all columns. Then, all but one row is put at the unselect voltage, V roW)Unse ⁇ , and remains in its current state (hence OFF) when the data voltages (V co ⁇ jSe ⁇ oN or V co ⁇ >se ⁇ o FF ) are applied on the column voltage.
  • One row is put at the ON- select voltage, V row>se io N - At this voltage, a pixel will switch ON and emit light when the column voltage is at V co ⁇ jSe ⁇ o N , while it will remain in its current position (hence OFF) when the column voltage is V C oi, S eiOFF-
  • the rows are addressed sequentially during a first scan, to allow switching all pixels ON, and then a second scan is performed during which the selective row voltage is r ow,seio FF> and all column voltages are put to V co ⁇ ,sei ⁇ F F, i.e. all pixels are switched to the OFF state.
  • the frame period is divided into several pairs of such ON- and OFF-scans, each such pair being referred to as a sub-field.
  • Grey scales can be accomplished by switching a pixel ON during appropriate sub-fields, which preferably are weighted, for example in a binary fashion (binary weighted sub- fields, BWS).
  • BWS binary weighted sub- fields
  • An important parameter of an addressing scheme is the number of "time slots" which are needed for a full scheme within a frame period, since that determines the available row selection (addressing) time. Roughly stated, the larger the addressing time, the easier it is to address correctly.
  • An object of the present invention is to provide an improved addressing scheme, increasing the available row selection time. According to the invention, this object is achieved by a method of the kind mentioned by way of introduction, comprising applying a data signal to all column electrodes in the set, applying to a first row electrode an ON-select voltage such that the pixels connected to said first row electrode can be switched ON by the data signal, applying to at least one second row electrode an OFF voltage such that the pixels connected to said second row electrode are switched OFF regardless of the data signal, and applying to all remaining row electrodes in the set an unselect voltage, such that the pixels connected to these row electrodes remain in their present state (ON or OFF) regardless of the voltage applied on the column electrodes.
  • the "set" of electrodes not necessarily includes all electrodes of the display.
  • the electrodes of the display may advantageously be divided into several sets, in order to provide a more efficient addressing.
  • ON and OFF addressing can be performed during the same scan, and this effect is referred to as "dual action".
  • This is made possible by applying a voltage adapted to place the line in the OFF state regardless of the voltage applied to the pixels in the line. With reference to Fig. 1, this would correspond to a row voltage level to the left of the junction between the OFF-curve and V co ⁇ , Se i ⁇ N.
  • the method according to the invention serves to reduce the dead time in addressing schemes and to decrease the required number of addressing slots, thus increasing the (maximum) row selection time for addressing the display. Moreover, it provides more freedom in choosing sub- field weight and removes some of the restrictions present in previous addressing schemes.
  • the unselect voltage is preferably between the ON-select voltage and the OFF voltage levels.
  • the method according to the invention can be advantageously implemented in a dynamic foil display.
  • the above objects are also achieved by a display driver, comprising means for applying the mentioned voltages in the specified manner.
  • the display driver comprises at least two switching circuits, each being arranged for simultaneous supply of two of at least three different switching voltages, wherein each switching circuit is connected to a different set of row electrodes and arranged to alternatingly supply these row electrodes with different pairs of voltages.
  • Such a driver allows addressing a display with three or more voltage levels at the same time.
  • One of the voltages in a first voltage pair can be applied only to one row electrode, and be adapted to allow pixels to be switched ON by a data signal applied to the column electrodes.
  • Another voltage in a second voltage pair can be adapted to switch pixels OFF regardless of a data signal applied to the column electrodes.
  • Fig. 1 illustrates the switching curves of a pixel element having a bi-stable region.
  • Fig. 2 is a side view of a dynamic foil display.
  • Figs. 3a and 3b illustrates two conventional addressing schemes for a display having bi-stable pixel elements.
  • Fig. 4 illustrates the switching curves of a pixel element addressed according to the invention.
  • Figs. 5a and 5b illustrate two addressing scheme according to a first embodiment of the invention.
  • Fig. 6 illustrates an addressing scheme according to a second embodiment of the invention.
  • Figs. 7a and 7b are schematic drawings of a driver circuit suitable for implementing the method according to the invention.
  • a dynamic foil display described in e.g. WOOO/38163.
  • a dynamic foil display is illustrated in Fig. 2, and comprises a light guide 5 in the form of an edge lit glass plate and a non-lit back plate 6, with a scattering foil 7 clamped in between.
  • Light from a light source 4 is coupled into the light guide 5.
  • the electrodes 9 on the light guide are referred to as column electrodes, while the electrodes 8 in the back plate are row electrodes.
  • the voltages applied to the electrodes are controlled by a row driver and a column driver. Pixels are defined by the intersections of rows and columns.
  • Fig. 3a and 3b Examples of addressing schemes are illustrated in Fig. 3a and 3b.
  • checked boxes 11 indicate time slots in which pixels in the row can be activated (turned ON), while the following white boxes 12 indicate time slots during which they will stay on if activated.
  • Black boxes 13 indicate time slots in which the pixels may be turned OFF (and always are turned OFF), while dotted boxes 14 indicate time slots during which the pixels stay OFF.
  • the pixels are always in the bi-stable region 1 shown in Fig. 1.
  • the pixels are further always in the OFF state, while in the white periods 12, they may be in different states (ON or OFF), depending on the switching performed in the preceding checked box 11.
  • a voltage V row>se ⁇ o N is applied to one row at a time, while other rows are connected to the voltage V r0WjUnse i- At the same time, all columns are provided with image information in the form of column data signals, applying one of the voltages 0 oi,sei ⁇ N or V co ⁇ , S eioFF to the columns.
  • V ro w,seioN is applied to a row, the pixels in columns provided with V co ⁇ ,sei ⁇ N are switched ON.
  • the same procedure is repeated for row voltage V roWj seioFF 5 and pixels in columns provided with V co ⁇ ;S eio F F are switched OFF.
  • the dead time which is at least equal to the number of lines minus one.
  • the length of the shortest sub-field (LSB) 10 has to include a number of time slots at least equal to the number of lines minus one, in order to allow completion of the first ON scan before the first OFF scan starts. (It is noted that the length of the sub-field here is defined as the number of white boxes 12.)
  • the ON- and OFF-scans are interleaved with each other, by introducing an intermediate time slot 16 between two consecutive ON-selections of rows.
  • this intermediate time slot the OFF-scan of a different row can take place.
  • This addressing scheme allows for a shorter first sub-field 10 (LSB). However, the minimum distance between two successive ON-scans is still two times the number of lines.
  • the addressing method according to the invention is implemented by applying three different voltage levels to the row electrodes during each time slot instead of two.
  • One row is provided with the voltage level V roWjSe ⁇ oN, and pixels on this row can then, just as was described above with reference to Fig. 3 a, be switched ON by applying column data voltage V co ⁇ ⁇ Se ⁇ o N to the column electrodes.
  • At least one row is further provided with a voltage level V ⁇ OWJOFF> which is chosen to be no larger than the voltage level intersecting the point where the OFF curve crosses the column data voltage V co ⁇ ⁇ Se ⁇ oN- When provided with this voltage, the pixels in the row are robustly switched OFF, regardless of the column data voltage (V co ⁇ >se ⁇ oN or V co i, S eioFF) that is applied to the column electrodes. Finally, all remaining rows are provided with the unselect voltage V row>u ⁇ se ⁇ .
  • the foil display is preferably made such that the robust row OFF action can be performed at a modest voltage level.
  • Fig. 5a shows the addressing scheme in Fig. 3a, improved by implementing the method according to the invention.
  • the OFF addressing boxes 17 black
  • OFF addressing boxes 17 are now robust OFF addressing, i.e. the pixels are turned OFF regardless of column data.
  • Each OFF scan can now be immediately followed by an ON scan, thereby eliminating the periods of dead time 14 present in Fig. 3a.
  • the first time slot with dual action is indicated with an arrow 20.
  • the LSB 10 can have L-2 slots, due to the overlap of the OFF scan with the ON scan made possible by the dual action addressing according to the invention.
  • the weight of the LSB 10 can be significantly reduced. This is illustrated in Fig. 5b, where the OFF scans 13 in Fig. 5a has been moved to the left to form sub-field weights of 2, 4, 8 and 16. As a consequence, the periods of dead time 14 are reintroduced. Just as in Fig. 5a, an overlap of the ON- and OFF- scans minimizes the introduced dead time, as every time slot is used for ON addressing of one of the rows.
  • the number of slots per sub-field in Fig. 5b equals the number of lines in the display as long as the sub-field weight is smaller than the number of lines minus 1.
  • Fig. 6 the addressing scheme in Fig. 3b has been improved by implementing the addressing method according to the invention.
  • the different sub-field scans have been moved closer together, so that again every time slot is used for ON addressing of one of the rows.
  • the distance between two successive ON scans is reduced, and is now equal to the number of lines for all sub- fields with weights smaller than the number of lines minus two.
  • the method according to the invention requires providing three different voltage levels to the pixel lines simultaneously, requiring a row driver with three levels.
  • scan ICs normally only are capable of applying one voltage level to one (or more) rows, and another voltage level on the other rows. Most often, the scan ICs can choose between only two voltages (its upper and lower supply voltages).
  • the patent application NL030380 herewith enclosed by reference, discloses a "jumping" IC having several different high levels and several different low levels. The upper and lower supplies of the scan IC are switched to those two values that are currently needed at a specific moment in time. However, this solution does not provide more than two output levels at the same time. To achieve three output levels at the same time, the display device is driven by
  • all odd rows can be connected to a first scan IC 71 and all even rows (r2, r4, r6) to a second scan IC 72.
  • the odd scan IC 71 is arranged to apply a row select voltage
  • V roW;Se ⁇ oN to one row and a row unselect voltage V r0W;U ⁇ sei to other rows, i.e. performs ON addressing.
  • the even scan IC 72 is arranged to apply a row unselect voltage Vro .unsei or a robust off row voltage V ro w,o F F, i.e. performs OFF addressing.
  • V .unsei or a robust off row voltage V ro w,o F F, i.e. performs OFF addressing.
  • the first scan IC 71 can be arranged to apply V row ,seioN to row 1 (rl) and V row , un sei to all other odd rows (r3, r5) during the first time slot (Fig. 7a), and arranged to apply V ⁇ OW , OFF to row 3 (r3) and V r0 ,u ns ei to all other odd rows (rl, r5) during the second time slot (Fig. 7b).
  • the second scan IC 72 can be arranged to apply V ⁇ OW ,OFF to row 2 (r2) and V row ,unsei to all other even rows (r4, r6) during the first time slot (Fig. 7a), and arranged to apply
  • V row seioN to row 2 (r2) and V row , Uns ei to all other even rows (r4, r6) during the second time slot (Fig. 7b).
  • the pattern is repeated with increased row numbers.
  • row electrodes and “column electrodes” are used in the description and claims generally to indicate a system of electrodes capable of addressing each pixel independently. This is normally accomplished by two orthogonal sets of parallel electrodes (hence the names), but may equally well be accomplished by two arbitrary sets of electrodes, as long as each pixel is connected to one electrode in each set.

Abstract

A method for addressing a display device comprising applying a data signal to all column electrodes in a set and applying to a first row electrode an ON-select voltage (VrowseloN) such that the pixels connected to said first row electrode can be switched ON by the data signal. Further, an OFF voltage (Vrow,OFF) is applied to at least one second row electrode such that the pixels connected to said second row electrode are switched OFF regardless of the data signal. As a consequence of the inventive method, ON and OFF addressing can be performed during the same scan, and this effect is referred to as 'dual action'. The method according to the invention serves to reduce the dead time in addressing schemes and to decrease the required number of addressing slots.

Description

Display device addressing method
The present invention relates to method for addressing a display device having a set of row electrodes and a set of column electrodes for addressing a plurality of pixels defined by intersections of said electrodes.
The invention also relates to a display driver for implementing such a method, and a display device comprising such a driver.
Such displays are normally referred to as "bi- stable" displays, and are typically addressed with passive matrix addressing. The dynamic foil display as described in e.g. WOOO/38163 is an example of such a display. The switching curves of a pixel element of the display in WOOO/38163 is shown in Fig. 1, where the x- and y-axis represent the row and column voltages respectively. The bi-stable region 1, between the ON-curve 2 and the OFF- curve 3, creates a memory effect in the pixel element. For a suitable row voltage level (Vrow,unsei), the state of the pixel cannot be switched (neither ON nor OFF) by changing the column voltage level between Vcoi,SeioN and V00ιjSeιoFF, but maintains its present state. This memory effect makes it possible to use a passive matrix addressing method to drive the display.
Conventionally, addressing is performed in the following way. First, all pixels are erased, e.g. by applying a high voltage to all columns. Then, all but one row is put at the unselect voltage, VroW)Unseι, and remains in its current state (hence OFF) when the data voltages (VcoιjSeιoN or Vcoι>seιoFF) are applied on the column voltage. One row is put at the ON- select voltage, Vrow>seioN- At this voltage, a pixel will switch ON and emit light when the column voltage is at VcoιjSeιoN, while it will remain in its current position (hence OFF) when the column voltage is VCoi,SeiOFF- The rows are addressed sequentially during a first scan, to allow switching all pixels ON, and then a second scan is performed during which the selective row voltage is row,seioFF> and all column voltages are put to Vcoι,seiθFF, i.e. all pixels are switched to the OFF state. The frame period is divided into several pairs of such ON- and OFF-scans, each such pair being referred to as a sub-field. Grey scales can be accomplished by switching a pixel ON during appropriate sub-fields, which preferably are weighted, for example in a binary fashion (binary weighted sub- fields, BWS). The sub-fields of a frame period are organized in an addressing scheme, which describes in what order the rows are being addressed with ON and OFF addressing actions.
An important parameter of an addressing scheme is the number of "time slots" which are needed for a full scheme within a frame period, since that determines the available row selection (addressing) time. Roughly stated, the larger the addressing time, the easier it is to address correctly.
An object of the present invention is to provide an improved addressing scheme, increasing the available row selection time. According to the invention, this object is achieved by a method of the kind mentioned by way of introduction, comprising applying a data signal to all column electrodes in the set, applying to a first row electrode an ON-select voltage such that the pixels connected to said first row electrode can be switched ON by the data signal, applying to at least one second row electrode an OFF voltage such that the pixels connected to said second row electrode are switched OFF regardless of the data signal, and applying to all remaining row electrodes in the set an unselect voltage, such that the pixels connected to these row electrodes remain in their present state (ON or OFF) regardless of the voltage applied on the column electrodes.
It should be noted that the "set" of electrodes not necessarily includes all electrodes of the display. On the contrary, the electrodes of the display may advantageously be divided into several sets, in order to provide a more efficient addressing.
As a consequence of the inventive method, ON and OFF addressing can be performed during the same scan, and this effect is referred to as "dual action". This is made possible by applying a voltage adapted to place the line in the OFF state regardless of the voltage applied to the pixels in the line. With reference to Fig. 1, this would correspond to a row voltage level to the left of the junction between the OFF-curve and Vcoι,SeiθN.
The method according to the invention serves to reduce the dead time in addressing schemes and to decrease the required number of addressing slots, thus increasing the (maximum) row selection time for addressing the display. Moreover, it provides more freedom in choosing sub- field weight and removes some of the restrictions present in previous addressing schemes.
The unselect voltage is preferably between the ON-select voltage and the OFF voltage levels. The method according to the invention can be advantageously implemented in a dynamic foil display.
According to a second aspect of the invention, the above objects are also achieved by a display driver, comprising means for applying the mentioned voltages in the specified manner. According to one embodiment, the display driver comprises at least two switching circuits, each being arranged for simultaneous supply of two of at least three different switching voltages, wherein each switching circuit is connected to a different set of row electrodes and arranged to alternatingly supply these row electrodes with different pairs of voltages. Such a driver allows addressing a display with three or more voltage levels at the same time.
One of the voltages in a first voltage pair can be applied only to one row electrode, and be adapted to allow pixels to be switched ON by a data signal applied to the column electrodes. Another voltage in a second voltage pair can be adapted to switch pixels OFF regardless of a data signal applied to the column electrodes. Such a driver presents a practical implementation of the inventive addressing concept of dual action.
These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing currently preferred embodiments of the invention.
Fig. 1 illustrates the switching curves of a pixel element having a bi-stable region.
Fig. 2 is a side view of a dynamic foil display. Figs. 3a and 3b illustrates two conventional addressing schemes for a display having bi-stable pixel elements.
Fig. 4 illustrates the switching curves of a pixel element addressed according to the invention. Figs. 5a and 5b illustrate two addressing scheme according to a first embodiment of the invention.
Fig. 6 illustrates an addressing scheme according to a second embodiment of the invention. Figs. 7a and 7b are schematic drawings of a driver circuit suitable for implementing the method according to the invention.
In the following, the method according to the invention will be described in relation to a dynamic foil display, described in e.g. WOOO/38163. Such a display is illustrated in Fig. 2, and comprises a light guide 5 in the form of an edge lit glass plate and a non-lit back plate 6, with a scattering foil 7 clamped in between. Light from a light source 4 is coupled into the light guide 5. On both plates there are respective sets of parallel electrodes 8, 9 which are arranged perpendicularly with respect to each other. The electrodes 9 on the light guide are referred to as column electrodes, while the electrodes 8 in the back plate are row electrodes. The voltages applied to the electrodes are controlled by a row driver and a column driver. Pixels are defined by the intersections of rows and columns. By applying suitable voltages to a row and a column electrode, an area of the foil 7 can be brought into contact with the light guide 5, to thereby disturb the total internal reflection and extract light from the light guide 5.
Conventionally, the dynamic foil display is addressed in the way which was described above, with reference to Fig. 1. Examples of addressing schemes are illustrated in Fig. 3a and 3b. In these Figures (and in the following Figures 5a, 5b and 6), checked boxes 11 indicate time slots in which pixels in the row can be activated (turned ON), while the following white boxes 12 indicate time slots during which they will stay on if activated. Black boxes 13 indicate time slots in which the pixels may be turned OFF (and always are turned OFF), while dotted boxes 14 indicate time slots during which the pixels stay OFF. During the white periods 12 and the dotted periods 14 the pixels are always in the bi-stable region 1 shown in Fig. 1. In the dotted periods 14, the pixels are further always in the OFF state, while in the white periods 12, they may be in different states (ON or OFF), depending on the switching performed in the preceding checked box 11.
During an ON-scan, a voltage Vrow>seιoN is applied to one row at a time, while other rows are connected to the voltage Vr0WjUnsei- At the same time, all columns are provided with image information in the form of column data signals, applying one of the voltages 0oi,seiθN or Vcoι,SeioFF to the columns. When Vrow,seioN is applied to a row, the pixels in columns provided with Vcoι,seiθN are switched ON. During the OFF scan, the same procedure is repeated for row voltage VroWjseioFF5 and pixels in columns provided with Vcoι;SeioFF are switched OFF. After a pixel has been switched OFF there is a time period 14 during which the pixel is idle, referred to as the dead time, which is at least equal to the number of lines minus one. Further, the length of the shortest sub-field (LSB) 10 has to include a number of time slots at least equal to the number of lines minus one, in order to allow completion of the first ON scan before the first OFF scan starts. (It is noted that the length of the sub-field here is defined as the number of white boxes 12.)
In Fig. 3b, the ON- and OFF-scans are interleaved with each other, by introducing an intermediate time slot 16 between two consecutive ON-selections of rows. In this intermediate time slot, the OFF-scan of a different row can take place. This addressing scheme allows for a shorter first sub-field 10 (LSB). However, the minimum distance between two successive ON-scans is still two times the number of lines.
With reference to Fig. 4, the addressing method according to the invention is implemented by applying three different voltage levels to the row electrodes during each time slot instead of two. One row is provided with the voltage level VroWjSeιoN, and pixels on this row can then, just as was described above with reference to Fig. 3 a, be switched ON by applying column data voltage VcoιιSeιoN to the column electrodes. At least one row is further provided with a voltage level VΓOWJOFF> which is chosen to be no larger than the voltage level intersecting the point where the OFF curve crosses the column data voltage VcoιιSeιoN- When provided with this voltage, the pixels in the row are robustly switched OFF, regardless of the column data voltage (Vcoι>seιoN or Vcoi,SeioFF) that is applied to the column electrodes. Finally, all remaining rows are provided with the unselect voltage Vrow>uπseι.
By this dual action addressing, whereby pixels on different rows can be addressed ON and OFF respectively during the same scan, the addressing schemes illustrated in Fig. 3a and 3b can be improved significantly.
In order to avoid sparks between the foil and the row, the foil display is preferably made such that the robust row OFF action can be performed at a modest voltage level.
Fig. 5a shows the addressing scheme in Fig. 3a, improved by implementing the method according to the invention. The OFF addressing boxes 17 (black) are now robust OFF addressing, i.e. the pixels are turned OFF regardless of column data. Each OFF scan can now be immediately followed by an ON scan, thereby eliminating the periods of dead time 14 present in Fig. 3a. The first time slot with dual action is indicated with an arrow 20. According to this addressing scheme, the LSB 10 can have L-2 slots, due to the overlap of the OFF scan with the ON scan made possible by the dual action addressing according to the invention.
In order to compare the addressing scheme in Fig. 5 with that in Fig. 3a, consider a (W-)VGA display with L=480 lines and NSF=8 binary sub-fields working at 50 Hz. In the addressing scheme in Fig. 3a the weight of the LSB is wLSB=L- 1=479 slots. The number of time slots used to generate light is Lslots = wLSB * (2NSF - 1) = 479*255 = 122145.
The total number of slots is
Nslots = Lslots + NSF * (L+l) = 122145 + 8*481 = 125993.
This results in a slot time of 20 ms / 125993 = 0.159 μs and an efficiency of 122145/125993 = 96,9 %. The corresponding values for the scheme in Fig. 5a, where wLSB is L-2, are:
Lslots = 478*255 = 121890,
Nslots = Lslots + 2*NSF + (L-l) = 122385,
Resulting in slot time = 0.163 μs and efficiency = 99,6 %.
In summary, the efficiency has been increased significantly, while the slot time has also been increased.
By allowing a certain amount of dead time, the weight of the LSB 10 can be significantly reduced. This is illustrated in Fig. 5b, where the OFF scans 13 in Fig. 5a has been moved to the left to form sub-field weights of 2, 4, 8 and 16. As a consequence, the periods of dead time 14 are reintroduced. Just as in Fig. 5a, an overlap of the ON- and OFF- scans minimizes the introduced dead time, as every time slot is used for ON addressing of one of the rows.
While it in principle would be possible to have a LSB weight of one time slot, with the currently preferred row driver implementation which will be mentioned below, it is advantageous to have a LSB comprising an even number of time slots, so that all sub-fields have even weights.
It can be observed that the number of slots per sub-field in Fig. 5b equals the number of lines in the display as long as the sub-field weight is smaller than the number of lines minus 1. For the example mentioned above, with 480 lines, 8 binary sub- fields with a lowest weight LSB of 2 time slots (as indicated in Fig. 5b), the total number of slots required for the full scheme would be Nslots = 8 * 480 + 256 + 1 = 4097 slots, which would result in an addressing slot time of 4.88 μs for a 50 Hz frame rate, while light is generated during Lslots = 2*255 = 510 slots, i.e. at 12.4 % of the full frame time. For LSB = 4, Nslots = 4353, Lslots = 1020, slot time = 4.59 μs and efficiency = 23.4 %. We can thus increase the slot time significantly compared to that of the conventional addressing scheme in Fig. 3a, at the cost of some efficiency.
In Fig. 6, the addressing scheme in Fig. 3b has been improved by implementing the addressing method according to the invention. Here, the different sub-field scans have been moved closer together, so that again every time slot is used for ON addressing of one of the rows. Thereby the distance between two successive ON scans is reduced, and is now equal to the number of lines for all sub- fields with weights smaller than the number of lines minus two.
The implementation in Fig. 6 requires that the voltage VΓOW>OFF is applied to two rows in the same time slot. This introduces no problems since the OFF action is not data- dependent and thus not pixel-selective. Therefore, an OFF data signal can be applied to all columns independent of the data that was displayed, in order to be cause an OFF switching for any rows that are OFF-addressed. This is in contrast with the ON-addressing action, where the voltages applied at the columns only correspond to data for the row being addressed. In that case, the data for individual pixels in the column is not necessarily the same, and thus this ON-addressing needs to be done row-at-a-time.
An advantage of the scheme in Fig. 6 compared with the schemes in Fig. 5a and 5b is that the currently preferred row driver implementation which will be mentioned below can be used for all sub-field weights. This goes at the cost of some efficiency: for the addressing scheme in Fig. 6, the total number of required slots is Nslots = 8 * L + L + MSB + 1 = 4577 slots in our example from above, which would result in an addressing slot time of 4.37 μs for a 50 Hz frame rate. Light is generated during Lslots = 2*255 = 510 slots, i.e. at 11 % of the full frame time. For LSB = 4, we have Nslots = 4833, Lslots = 1020, slot time = 4.13 μs and efficiency = 21 %.
As mentioned above, the method according to the invention requires providing three different voltage levels to the pixel lines simultaneously, requiring a row driver with three levels. This is generally not possible as scan ICs normally only are capable of applying one voltage level to one (or more) rows, and another voltage level on the other rows. Most often, the scan ICs can choose between only two voltages (its upper and lower supply voltages). The patent application NL030380, herewith enclosed by reference, discloses a "jumping" IC having several different high levels and several different low levels. The upper and lower supplies of the scan IC are switched to those two values that are currently needed at a specific moment in time. However, this solution does not provide more than two output levels at the same time. To achieve three output levels at the same time, the display device is driven by
(at least) two scan ICs of the kind mentioned above, each of which is connected to a different set of rows.
As an example, illustrated in Fig. 7a and 7b, all odd rows (rl, r3, r5) can be connected to a first scan IC 71 and all even rows (r2, r4, r6) to a second scan IC 72. During odd time slots (Fig. 7a), the odd scan IC 71 is arranged to apply a row select voltage
VroW;SeιoN to one row and a row unselect voltage Vr0W;Uπsei to other rows, i.e. performs ON addressing. At the same time, the even scan IC 72 is arranged to apply a row unselect voltage Vro .unsei or a robust off row voltage Vrow,oFF, i.e. performs OFF addressing. During even time slots (Fig. 7b), the roles and voltages of both ICs are reversed. When implementing an addressing scheme with dual action according to the invention, the first scan IC 71 can be arranged to apply Vrow,seioN to row 1 (rl) and Vrow,unsei to all other odd rows (r3, r5) during the first time slot (Fig. 7a), and arranged to apply VΓOW,OFF to row 3 (r3) and Vr0 ,unsei to all other odd rows (rl, r5) during the second time slot (Fig. 7b). Similarly, the second scan IC 72 can be arranged to apply VΓOW,OFF to row 2 (r2) and Vrow,unsei to all other even rows (r4, r6) during the first time slot (Fig. 7a), and arranged to apply
Vrow,seioN to row 2 (r2) and Vrow,Unsei to all other even rows (r4, r6) during the second time slot (Fig. 7b). For the third and following time slots the pattern is repeated with increased row numbers.
As all flat panels already use a number of scan ICs to drive the whole panel, the above arrangement does not add cost.
Note that in the addressing scheme illustrated in Fig. 5b, if the weight of the LSB is only one time slot, an ON and OFF action are simultaneously performed on two odd or on two even rows. When using a driver according to Fig. 7, this would require that the groups of rows are organized differently. It would also put restrictions on the maximum weight of the MSB. However, as mentioned above, when using a driver according to Fig. 7, it is preferred to let the LSB weight be an even number of time slots.
Many modifications of the embodiments described above are possible within the scope of the appended claims. For example, the number of lines, number of sub-fields and frequency of the display may be different compared to the given examples, thereby altering the given numeric values.
Further, it should be noted that the terms "row electrodes" and "column electrodes" are used in the description and claims generally to indicate a system of electrodes capable of addressing each pixel independently. This is normally accomplished by two orthogonal sets of parallel electrodes (hence the names), but may equally well be accomplished by two arbitrary sets of electrodes, as long as each pixel is connected to one electrode in each set.

Claims

CLAIMS:
1. A method for addressing a display device having a set of row electrodes (8) and a set of column electrodes (9) for addressing a plurality of pixels defined by intersections of said electrodes, comprising: applying a data signal (Vcoι>seιoN> coιιSeιoFF) to all column electrodes (9) in the set, and applying to a first row electrode an ON-select voltage (Vro ,seiON) such that the pixels connected to said first row electrode can be switched ON by the data signal, applying to at least one second row electrode an OFF-voltage (VΓ0WJ0FF) such that the pixels connected to said second row electrode are switched OFF regardless of the data signal, and applying to all remaining row electrodes in the set an unselect voltage level (Vrow.unsei). such that the pixels connected to these row electrodes remain in their present state (ON or OFF) regardless of the data signal.
2. A method according to claim 1, applied in a display device with a driver having two switching circuits (71, 72), each being arranged for simultaneous supply of two of said three different voltages (Vro >seioN, Vrow,oFF5 Vrow>unseι), wherein each switching circuit is connected to a different set of row electrodes, further comprising: during a first time slot controlling the first switching circuit to provide one of the row electrodes connected thereto with the ON-select voltage (Vrow,SeiθN)5 and remaining row electrodes in the set with the unselect voltage (VroWιUnseι), and controlling the second switching circuit to provide at least one of the row electrodes connected thereto with the OFF voltage (VroWιoFF)> and remaining row electrodes in the set with the unselect voltage
I row.unsel during a second time slot controlling the first switching circuit to provide at least one of the row electrodes connected thereto with the OFF voltage (Vro >OFF)5 and remaining row electrodes in the set with the unselect voltage (Vr0WjUnseι), and controlling the second switching circuit to provide one of the row electrodes connected thereto with the ON- select voltage (Vrow,seioN)s and remaining row electrodes in the set with the unselect voltage
( ro .unsel)-
3. A method according to claim 1 or 2, wherein said unselect voltage level is between said ON-select and said OFF voltage levels.
4. A method according to any of the preceding claims, wherein said display device comprises a light guide (5) and a flexible element (7), and wherein said row and column electrodes (8, 9) are arranged to bring selected portions of the flexible element (7) into contact with the light guide in order to extract light from the light guide (5).
5. A display driver intended for use in a display device having a set of row electrodes (8) and a set of column electrodes (9) for addressing a plurality of pixels defined by intersections of said electrodes, said driver comprising means for applying a data signal (VcoιιSeιoN> coιjSeιoFF) to all column electrodes
(9) in the set, means for applying to a first row electrode an ON-select voltage (Vr0WιSeιoN) such that the pixels connected to said first row electrode can be switched ON by the data signal, means for applying to at least one second row electrode an OFF-voltage
(VΓO .OFF) such that the pixels connected to said second row electrode are switched OFF regardless of the data signal, and means for applying to all remaining row electrodes in the set an unselect voltage level (Vrow.unsei), such that the pixels connected to these row electrodes remain in their present state (ON or OFF) regardless of the data signal.
6. A display driver according to claim 5, wherein said means for applying voltages comprise at least two switching circuits (71, 72), each being arranged for simultaneous supply of two of at least three different switching voltages, wherein each switching circuit (71, 72) is connected to a different set (rl, r3, r5 ; r2, r4, r6) of row electrodes and arranged to alternatingly supply these row electrodes with different pairs of voltages.
7. A display driver according to claim 6, wherein one of the voltages (Vrow,seioN) in a first voltage pair is applied only to one row electrode (8), and is adapted to allow pixels to be switched ON by a data signal applied to the column electrodes (9).
8. A display driver according to one of claims 6 or 7, wherein one of the voltages
(VΓOW.OFF) in a second voltage pair is adapted to switch pixels OFF regardless of a data signal applied to the column electrodes (9).
9. A display device comprising a driver circuit according to one of claims 5 - 8.
10. A display device according to claim 9, further comprising a light guide (5) and a flexible element (7), and wherein said row and column electrodes (8, 9) are arranged to bring selected portions of the flexible element (7) into contact with the light guide in order to extract light from the light guide (5).
PCT/IB2004/050798 2003-06-05 2004-05-28 Display device addressing method WO2004109644A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969701A (en) * 1995-11-06 1999-10-19 Sharp Kabushiki Kaisha Driving device and driving method of matrix-type display apparatus for carrying out time-division gradation display
EP1193678A2 (en) * 2000-09-29 2002-04-03 Seiko Epson Corporation Driving method for electro-optical device, electro-optical device, and electronic apparatus
US6380689B1 (en) * 1999-10-06 2002-04-30 Pioneer Corporation Driving apparatus for active matrix type luminescent panel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969701A (en) * 1995-11-06 1999-10-19 Sharp Kabushiki Kaisha Driving device and driving method of matrix-type display apparatus for carrying out time-division gradation display
US6380689B1 (en) * 1999-10-06 2002-04-30 Pioneer Corporation Driving apparatus for active matrix type luminescent panel
EP1193678A2 (en) * 2000-09-29 2002-04-03 Seiko Epson Corporation Driving method for electro-optical device, electro-optical device, and electronic apparatus

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