WO2004112102A3 - Method for forming a sgoi by annealing near the sige alloy melting point - Google Patents

Method for forming a sgoi by annealing near the sige alloy melting point Download PDF

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Publication number
WO2004112102A3
WO2004112102A3 PCT/US2004/016747 US2004016747W WO2004112102A3 WO 2004112102 A3 WO2004112102 A3 WO 2004112102A3 US 2004016747 W US2004016747 W US 2004016747W WO 2004112102 A3 WO2004112102 A3 WO 2004112102A3
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WO
WIPO (PCT)
Prior art keywords
layer
forming
single crystal
heating step
sige
Prior art date
Application number
PCT/US2004/016747
Other languages
French (fr)
Other versions
WO2004112102A2 (en
Inventor
Stephen W Bedell
Huajie Chen
Anthony G Domenicucci
Keith E Fogel
Richard J Murphy
Devendra K Sadana
Original Assignee
Stephen W Bedell
Huajie Chen
Anthony G Domenicucci
Keith E Fogel
Richard J Murphy
Devendra K Sadana
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stephen W Bedell, Huajie Chen, Anthony G Domenicucci, Keith E Fogel, Richard J Murphy, Devendra K Sadana filed Critical Stephen W Bedell
Priority to EP04776135A priority Critical patent/EP1629524A2/en
Priority to JP2006533461A priority patent/JP4701181B2/en
Publication of WO2004112102A2 publication Critical patent/WO2004112102A2/en
Publication of WO2004112102A3 publication Critical patent/WO2004112102A3/en
Priority to IL172252A priority patent/IL172252A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer (16) on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320°C for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
PCT/US2004/016747 2003-05-30 2004-05-27 Method for forming a sgoi by annealing near the sige alloy melting point WO2004112102A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04776135A EP1629524A2 (en) 2003-05-30 2004-05-27 Method for forming a sgoi by annealing near the sige alloy melting point
JP2006533461A JP4701181B2 (en) 2003-05-30 2004-05-27 Method for manufacturing a semiconductor substrate material
IL172252A IL172252A (en) 2003-05-30 2005-11-29 High -quality sgoi by annealing near the alloy melting point

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/448,948 US7049660B2 (en) 2003-05-30 2003-05-30 High-quality SGOI by oxidation near the alloy melting temperature
US10/448,948 2003-05-30

Publications (2)

Publication Number Publication Date
WO2004112102A2 WO2004112102A2 (en) 2004-12-23
WO2004112102A3 true WO2004112102A3 (en) 2005-02-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/016747 WO2004112102A2 (en) 2003-05-30 2004-05-27 Method for forming a sgoi by annealing near the sige alloy melting point

Country Status (8)

Country Link
US (4) US7049660B2 (en)
EP (1) EP1629524A2 (en)
JP (1) JP4701181B2 (en)
KR (1) KR100763676B1 (en)
CN (1) CN1799136A (en)
IL (1) IL172252A (en)
TW (1) TWI282117B (en)
WO (1) WO2004112102A2 (en)

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TW201019375A (en) * 2008-10-02 2010-05-16 Sumitomo Chemical Co Semiconductor wafer, electronic device, and method for making a semiconductor wafer
KR20110097755A (en) * 2008-11-28 2011-08-31 스미또모 가가꾸 가부시키가이샤 Method for producing semiconductor substrate, semiconductor substrate, method for manufacturing electronic device, and reaction apparatus
US20110124146A1 (en) * 2009-05-29 2011-05-26 Pitera Arthur J Methods of forming high-efficiency multi-junction solar cell structures
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
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Also Published As

Publication number Publication date
TW200503077A (en) 2005-01-16
TWI282117B (en) 2007-06-01
IL172252A0 (en) 2006-04-10
US20040238885A1 (en) 2004-12-02
KR20060085169A (en) 2006-07-26
WO2004112102A2 (en) 2004-12-23
JP4701181B2 (en) 2011-06-15
US20040259334A1 (en) 2004-12-23
EP1629524A2 (en) 2006-03-01
US20080116483A1 (en) 2008-05-22
CN1799136A (en) 2006-07-05
US7473587B2 (en) 2009-01-06
IL172252A (en) 2010-12-30
KR100763676B1 (en) 2007-10-04
US7679141B2 (en) 2010-03-16
US7049660B2 (en) 2006-05-23
US20050208780A1 (en) 2005-09-22
JP2007502030A (en) 2007-02-01
US7348253B2 (en) 2008-03-25

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