WO2005001933A2

WO2005001933A2 - Multichip semi-conductor component and method for the production thereof

Info

Publication number: WO2005001933A2
Application number: PCT/EP2004/051154
Authority: WO
Inventors: Karlheinz Müller
Original assignee: Infineon Technologies Ag
Priority date: 2003-06-28
Filing date: 2004-06-17
Publication date: 2005-01-06
Also published as: WO2005001933A3

Abstract

The invention relates to a multichip semi-conductor component (1) comprising at least one group of chips which is made of at least two semi-conductor chips (2, 3) having a first and a second surface side, whereby the first surface sides thereof face each other. The adjacent surface sides of the semi-conductor chips (2, 3) respectively have a spatial structure (7) and the spatial structures (7) engage with each other in a positive fit in such a manner that the geometric arrangement of the surface sides of the semi-conductor chips (2, 3), facing each other, is distinct and the metal connection of the semi-conductor chips (2, 3) facing each other is reliably conductive. The semi-conductor chips (2, 3) are mounted by vibrating said semi-conductor chips (2, 3) on a machine system.

Description

Multichip semiconductor device and method for its production

The present invention relates to a multichip semiconductor element and to a method for producing the multichip semiconductor element. In microelectronics, silicon chips and others, e.g. GaAs chips and / or passive components are often connected to one another in a multiple arrangement - also mixed. The endeavor to design ever denser assemblies leads to the collection of these chips in ever more compact packages and the interconnection with the lowest possible line capacity.

There are many approaches to this topic, in technical jargon these methods are known as "flip chip", "face to face", "multi chip module (MCM)", "system in package" etc. One example is the website of the company "Binder Elektronik GmbH" htt: // www .binder-elektronik. De /. The following is published under the term "flip-chip technology": "The flip-chip can be used to achieve the greatest possible degree of miniaturization. The dimensions of the flip chip are limited to the size of the bare silicon chip. The bare chip is mounted upside down (face-down) on a substrate (e.g. a circuit board). One of the joining partners must have Bu ps, the landing areas on the substrate are arranged in mirror image to the chip contacts.

Flip-Chip Attach (FAC) describes a process introduced by IBM, in which a "solder bump" consists of a higher melting solder and in which the connection to the substrate can be realized with eutectic solder, whereby this Process can be integrated in ordinary SMD production lines.

There it is also described that for some applications it is necessary to avoid soldering chips, since, for example, the brackets must not be exposed to the temperatures required for soldering. In these cases the only connection technique left is the use of conductive glue or film. "

Due to the spatially increased "bumps", tension and microcracks of the afers and / or the chips can occur due to the required process pressure; the reliability and the yield are unsatisfactory. The process costs are often high because an additional equipment park is required.

DE 42 14 102 C2 describes a multichip semiconductor device and a method for its production. There, it is stated that a multichip semiconductor component consists of at least one group of chips, a first and a second chip lying opposite one another such that a first side of the first chip and a first side of the second chip face one another (face to face). , wherein the first side of the first chip and the first side of the second chip have first and second solder bumps formed thereon, and that leads are present whose outer sections protrude from an encapsulation of the chip group. Further explanations deal with the manufacture of such a multi-chip semiconductor component and with its chip structure and its connection variation options.

Nothing is said there about a multichip semiconductor module without internal connecting lines and the mutual adjustment of the chip modules to be connected to one another is not dealt with in the publication either.

The present invention is based on the object of creating a multichip semiconductor module, the individual of which Chip modules with standard technologies for manufacturing integrated circuit circuits can be easily produced and which can contain a large number of different chip modules. Furthermore, a method for producing such a multichip semiconductor module is to be specified.

This object is achieved with a multichip semiconductor module which has the features of claim 1. From claim 15, the steps for producing such a multi-chip semiconductor device are specified.

The advantages of the multichip semiconductor module according to the invention lie in an optimal connection of the individual chip modules, the simple manufacture and the high reliability. Only standard technologies are required for the assembly of the semiconductor chips. Many different semiconductor chips can be mounted on a base. An optimal metallic connection can be created between the semiconductor chips. Any number of small connections can be realized which only depend on the boundary condition which currents have to flow between the semiconductor chips. The choice of contact surfaces (pads) that are to be electrically connected to one another is arbitrary. The low risk of chip tension ensures high reliability.

A multichip semiconductor module with at least one chip group, which consists of at least two semiconductor chips, which have a first and a second surface side and whose first surface sides face each other, and in which the mutually facing surface sides of the semiconductor chips in each case have a spatial, is advantageous Have structure, and that the spatial structures interlock positively in such a way that the geometrical assignment of the facing surface sides of the

Semiconductor chips clearly and the metallic connection of the mutually facing semiconductor chips is safely conductive. A multichip semiconductor module is also advantageous, in which the spatial structure of the first surface of the one semiconductor chip consists of trenches and / or holes with walls that widen outwards, and the spatial structure of the surface of the further semiconductor chip consists of webs and / or columns exists, the walls of which are essentially perpendicular to the substrate.

A multichip semiconductor component is also advantageous, in which the webs and / or pillars of the further semiconductor chip engage in a form-fitting manner in the trenches and / or holes of the first semiconductor chip.

Another advantage is that the spatial

Structures consist of metallic conductive functional structures and metallic non-conductive adjustment structures.

In addition, it is advantageous that the height and width of the metallically non-conductive adjustment structures are dimensioned such that they engage in one another in a corresponding assembly step rather than the metallically conductive functional structures.

A simple construction is possible if the structures are worked out from a multilayer system using lithographic methods and the height of the adjustment structure can be adjusted by the thickness of the passivation layer.

It is also advantageous if the functional structure consists of a metallic multilayer structure such as Ti / TiN / AlCu or Ti / W / AlCu or Ti / Pt / AlCu after a sandwich or of an oxide / nitride multilayer structure with a metallic coating, the metallic one Plating should be made of gold. It is also advantageous if a solder is present for the phase formation and intimate metallic connection of the structures.

It is particularly favorable if the adjustment structures are arranged in the corners of the semiconductor chips.

The manufacture of a multichip semiconductor module is very advantageous if the semiconductor chips are mounted on a machine system by vibrating the semiconductor chips, the coarse threading using the adjustment structures and the precise positioning of the semiconductor chips due to the vibration of the semiconductor chips each other through the functional structures.

The invention is explained in more detail with the aid of the drawings, using exemplary embodiments.

Show it:

FIG. 1 shows a multichip semiconductor module with structures made of an oxide layer;

FIG. 2 shows a multichip semiconductor module with structures made of a metallic sandwich layer;

FIG. 3 shows an “upper” semiconductor chip with a structure made of partially metallized webs; FIG. 4 shows an “lower” semiconductor chip with a structure made of inclined-walled trenches;

FIG. 5 shows an “upper” semiconductor chip with a structure made of partially metallized prisms and

FIG. 6 shows an “upper” semiconductor chip with a structure made of partially metallized cylinders. FIG. 1 shows an already assembled multichip semiconductor component 1, which consists of an upper chip 2 and a lower chip 3. The terms upper chip 2 and lower chip 3 are chosen arbitrarily and have no meaning for the actual arrangement of the chips 2 and 3 in the multichip semiconductor module 1. These terms serve only for a simple explanation in the description of the exemplary embodiments with the aid of the drawings.

The multichip semiconductor module 1 shown in FIG. 1 corresponds to a chip combination in which a lower chip 3, which has already been completed using the customary process technologies, has been structured according to the invention by means of a multilayer system 4, as is also shown in FIG. First, a passivation layer 5 of a corresponding, uniform thickness is applied to a wafer or another carrier 6. The multilayer system 4 can be formed by a metallic layer or else by an oxide / nitride layer that is to be structured. This multilayer system 4 is applied to the wafer or other carrier 6 in a manner known per se by method steps which are known from standard chip production. The structuring is carried out by several steps, of which the desired geometric conditions of the structure 7 are determined in the multilayer system 4 by means of lithographic steps. Subsequent treatment of the multilayer system 4 mentioned determines the spatial conditions, ie the course and the depth of the future structure 7, of the lithographically defined structure 7. During the subsequent etching, the actual spatial structure 7 then arises, the shape of the structure 7 not only being determined two-dimensionally, but three-dimensionally, that is to say spatially, which results in trenches G. This means that both the course - that is, the two-dimensional geometric conditions - is generated, as well as the spatial design, for example the orientation, that is to say, if appropriate Sloping walls W of trenches G of structure 7. Whether the walls W run obliquely or straight, ie anisotropically or isotropically, depends on the design of the trenches G of the overall structure 7 and the etching parameters. Depending on the technology used, the layers (oxide or metal) can be left in the trenches JG or etched out.

The surface of the counterpart, here that of an upper chip 2, is structured in the same way. In order to be able to create a perfect metallic connection when the upper chip 2 is joined to the lower chip 3, which will be explained later, a metallic multilayer coating 8, a sandwich structure, is selected when the structure 7 of the upper chip 2 is constructed. This sandwich structure consists of a barrier 9 and a conductive layer 10. This sandwich structure 8 can for example consist of Ti / TiN / AlCu or Ti / W / AlCu or Ti / Pt / AlCu. After the coating, a gold coating Au is applied for better phase formation. Such a structure can be seen in FIG. 3, in which a structuring by means of webs is shown.

So-called upper chips 2 with the same structure, but with a different geometric design of the structure 7 can be seen from FIGS. 5 and 6. In Figure 5 four-sided columns 8 _{5 are shown} as part of the structure 7s. The columns 7 ₅ are provided with a gold coating Au, which improve the metallic compound represented by the structure 7 of the respective lower chip 3 is used that can be gathered from the structure shown 7 are made with grooves G by suitable shaped holes, although not here were shown.

In FIG. 6, the structure 7_ consists of cylindrical columns 8 ₆ , which is suitable both for a counter structure 7 on the lower chip 2, consisting of trenches G, and of holes. Here, too, a layer Au is exemplary on a column 8g made of gold as solder for better metallic connection.

In FIGS. 5 and 6, the elements are shown and described only insofar as they differ from FIGS. 1, 2, 3 and 4, and the different elements have an index for clarification, which corresponds to the figure numbering.

Back to FIG. 2 - there is shown a variant in the structure of the structures 7. The most important difference lies in the metallic transition of the connection of the upper chip 2 to the lower chip 3. In the exemplary embodiment according to FIG. 1, the cover surfaces 7 _{D of} the web-shaped structure 7 of the upper chip 2 contact a metallic counterpart, for example a connection pad 11 of the trench-shaped one Structure 7 of the lower chip 3. The intimate metallic connection of the contact surfaces 7 _D and 11 takes place, for example, by molten solder 12 or gold Au.

In the exemplary embodiment according to FIG. 2 that is now to be discussed, the webs 4 machined out of the multilayer system 4 after the etching of the structure 7 of the lower chip 3 already consist of metal. The counter structure 7 of the upper chip 2 has a structured barrier 8, 8 ₅ , 8 ₀ , each with a conductive coating Au, which here consists of gold, as described in FIGS. 3, 5 and 6. When the upper chip 2 is joined to the lower chip 3, the desired intimate metallic contact is produced on the walls of the structures 7.

For the assembly of the upper chips 2 with the lower chips 3, there are also electrically non-conductive adjustment structures J7 in addition to the previously described electrical functional structures F7. These are applied to the wafer or carrier 6 using the same structuring process as the previously described electrically conductive functional structures F7. However, you can Because they only provide an auxiliary guide when adjusting the upper chips 2 relative to the lower chips 3.

The depth and width of the adjustment structures J7 are dimensioned in such a way that they already interlock when the function structures F7 have not yet come into their mutual influence. With the aid of the passivation layer 5, the necessary height difference of the adjustment structures J7 to the functional structures F7 is set on the respective carrier 6. The height of an adjustment structure J7 can also be influenced by an oxide or nitride layer which is partially applied to the carrier 6 before the passivation. This makes it possible to implement adjustment structures J7 of different heights. The adjustment structures J7 can also be arranged in the corners of the chips 2 and 3 as angles or bevels, which need not be expressly shown here. Their position and size depends on the machine systems that are used to assemble chips 2 and 3 to form a multichip semiconductor module 1. The upper chips 2 are joined to the lower chips 3 by means of such machine systems with the aid of the adjustment structures J7 by vibrating the chips 2 and 3. By shaking and vibrating, the highest adjustment structures J7 are found first, then the somewhat lower adjustment structures J7 and then the functional structures F7 are in their correct position relative to one another and, after reaching this end position, can be intimately connected to one another by ultrasound, pressure and / or thermal treatment.

Claims

claims

1. Multi-chip semiconductor module with at least one chip group consisting of at least two semiconductor chips, which have a first and a second surface side and whose first surface sides face each other, characterized in that the mutually facing 0-surface sides of the semiconductor chips (2, 3 ) each have a spatial structure (7), and that the spatial

Structures (7) interlock positively in such a way that the geometrical assignment of the facing surface sides of the semiconductor chips (2, 3) is unambiguous and the metallic connection of the facing semiconductor chips (2, 3) is reliably conductive.

2. Multichip semiconductor device according to claim 1, characterized in that the spatial structure (7) of the first surface of the one semiconductor chip (3) consists of trenches (G) and / or holes with outwardly widening walls (W), and that the spatial structure of the surface of the further semiconductor chip (2) consists of webs (8) and / or columns (85, 8 _δ ), the walls (W) of which run essentially perpendicular to the substrate (β).

3. Multichip semiconductor device according to one of the preceding claims, characterized in that the webs (8) and / or columns (8 ₅ , 8 ₅ ) of the further semiconductor chip (2) in the trenches (G) and / or holes of the first semiconductor chip (3) intervene positively.

4. Multichip semiconductor device according to one of the preceding claims, characterized in that the spatial structures (7) consist of metallic conductive functional structures (F7) and metallic non-conductive alignment structures (J7).

5. Multichip semiconductor device according to one of the preceding claims, characterized in that the height and width of the metal-non-conductive adjustment structures (J7) are dimensioned such that they engage in one another in a corresponding assembly step rather than the metal-conductive functional structures (F7 ).

6. Multichip semiconductor device according to one of the preceding claims, characterized in that the metallic non-conductive adjustment structures (J7) are staggered in height and / or width, so that they engage in one another in the corresponding assembly steps according to their height.

7. Multichip semiconductor device according to one of the preceding claims, that the structures (7) are worked out from a multilayer system (4) using lithographic methods.

8. Multichip semiconductor device according to one of the preceding claims, characterized in that the height of the alignment structure (J7) is adjustable by the thickness of the passivation layer (5) or by further layers on the carrier (6).

9. Multi-chip semiconductor device according to one of the preceding claims, characterized in that the functional structure (F7) consists of a metallic multilayer structure such as Ti / TiN / AlCu or Ti / W / AlCu or Ti / Pt / AlCu after a sandwich.

10. Multichip semiconductor device according to one of the preceding claims, characterized in that the functional structure (F7) consists of an oxide / nitride multilayer structure with a metallic coating (Au).

11. Multichip semiconductor device according to one of the preceding claims, characterized in that the metallic coating (Au) consists of gold.

12. Multichip semiconductor module according to one of the preceding claims, characterized in that a solder (Au) is present for phase formation and intimate metallic connection of the structures (7).

13. Multi-chip semiconductor device according to one of the preceding claims, characterized in that any elements and / or parts of the structures (7) can be selected for the intimate metallic connection.

14. Multi-chip semiconductor device according to one of the preceding claims, characterized in that the adjustment structures (J7) are arranged in the corners of the semiconductor chips (2, 3).

15. A method for producing a multichip semiconductor module according to one of the preceding claims, characterized in that the semiconductor chips (2, 3) are mounted on a machine system by vibrating the semiconductor chips (2, 3).

16. A method for producing a multichip semiconductor module according to one of the preceding claims, characterized in that the coarse threading with the aid of the adjustment structures (J7) is carried out by the vibration of the semiconductor chips (2, 3) and that the exact positioning of the semiconductor chips (2 , 3) to each other through the functional structures (F7).