WO2005001933A3 - Multichip semi-conductor component and method for the production thereof - Google Patents

Multichip semi-conductor component and method for the production thereof Download PDF

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Publication number
WO2005001933A3
WO2005001933A3 PCT/EP2004/051154 EP2004051154W WO2005001933A3 WO 2005001933 A3 WO2005001933 A3 WO 2005001933A3 EP 2004051154 W EP2004051154 W EP 2004051154W WO 2005001933 A3 WO2005001933 A3 WO 2005001933A3
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WO
WIPO (PCT)
Prior art keywords
semi
conductor
chips
multichip
conductor chips
Prior art date
Application number
PCT/EP2004/051154
Other languages
German (de)
French (fr)
Other versions
WO2005001933A2 (en
Inventor
Karlheinz Mueller
Original Assignee
Infineon Technologies Ag
Karlheinz Mueller
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Karlheinz Mueller filed Critical Infineon Technologies Ag
Publication of WO2005001933A2 publication Critical patent/WO2005001933A2/en
Publication of WO2005001933A3 publication Critical patent/WO2005001933A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
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    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

Abstract

The invention relates to a multichip semi-conductor component (1) comprising at least one group of chips which is made of at least two semi-conductor chips (2, 3) having a first and a second surface side, whereby the first surface sides thereof face each other. The adjacent surface sides of the semi-conductor chips (2, 3) respectively have a spatial structure (7) and the spatial structures (7) engage with each other in a positive fit in such a manner that the geometric arrangement of the surface sides of the semi-conductor chips (2, 3), facing each other, is distinct and the metal connection of the semi-conductor chips (2, 3) facing each other is reliably conductive. The semi-conductor chips (2, 3) are mounted by vibrating said semi-conductor chips (2, 3) on a machine system.
PCT/EP2004/051154 2003-06-28 2004-06-17 Multichip semi-conductor component and method for the production thereof WO2005001933A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10329222 2003-06-28
DE10329222.5 2003-06-28

Publications (2)

Publication Number Publication Date
WO2005001933A2 WO2005001933A2 (en) 2005-01-06
WO2005001933A3 true WO2005001933A3 (en) 2005-08-04

Family

ID=33546707

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/051154 WO2005001933A2 (en) 2003-06-28 2004-06-17 Multichip semi-conductor component and method for the production thereof

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402509B2 (en) * 2005-03-16 2008-07-22 Intel Corporation Method of forming self-passivating interconnects and resulting devices
WO2007071004A1 (en) 2005-12-20 2007-06-28 Bce Inc. Apparatus and method for supporting multiple traffic categories at a single networked device
CN102157459B (en) * 2011-03-16 2012-08-22 北京大学 TSV (through silicon via) chip bonding structure
EP2785786B1 (en) 2011-12-01 2018-05-30 Ineos Europe AG Polymer blends
CN108630559B (en) * 2017-03-16 2020-09-08 中芯国际集成电路制造(上海)有限公司 Wafer bonding method and wafer bonding structure
DE102018125901A1 (en) * 2018-10-18 2020-04-23 Osram Opto Semiconductors Gmbh Method for producing an electronic component, semiconductor chip, electronic component and method for producing a semiconductor chip

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0439134A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
EP1122567A1 (en) * 2000-02-02 2001-08-08 Corning Incorporated Passive alignement using slanted wall pedestal
US20020006686A1 (en) * 2000-07-12 2002-01-17 Cloud Eugene H. Die to die connection method and assemblies and packages including dice so connected
WO2002060810A2 (en) * 2001-01-30 2002-08-08 The University Of Sheffield Micro-element substrate interconnection
DE10120917C1 (en) * 2001-04-27 2002-11-28 Infineon Technologies Ag Arrangement with at least two centered stacked semiconductor chips
US6495396B1 (en) * 2001-08-29 2002-12-17 Sun Microsystems, Inc. Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0439134A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
EP1122567A1 (en) * 2000-02-02 2001-08-08 Corning Incorporated Passive alignement using slanted wall pedestal
US20020006686A1 (en) * 2000-07-12 2002-01-17 Cloud Eugene H. Die to die connection method and assemblies and packages including dice so connected
WO2002060810A2 (en) * 2001-01-30 2002-08-08 The University Of Sheffield Micro-element substrate interconnection
DE10120917C1 (en) * 2001-04-27 2002-11-28 Infineon Technologies Ag Arrangement with at least two centered stacked semiconductor chips
US6495396B1 (en) * 2001-08-29 2002-12-17 Sun Microsystems, Inc. Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices

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