WO2005003971A3 - Queued locks using monitor-memory wait - Google Patents

Queued locks using monitor-memory wait Download PDF

Info

Publication number
WO2005003971A3
WO2005003971A3 PCT/US2004/019373 US2004019373W WO2005003971A3 WO 2005003971 A3 WO2005003971 A3 WO 2005003971A3 US 2004019373 W US2004019373 W US 2004019373W WO 2005003971 A3 WO2005003971 A3 WO 2005003971A3
Authority
WO
WIPO (PCT)
Prior art keywords
monitor
memory wait
locks
queued
queued locks
Prior art date
Application number
PCT/US2004/019373
Other languages
French (fr)
Other versions
WO2005003971A2 (en
Inventor
Per Hammarlund
James Crossland
Anil Aggarwal
Shivnandan Kaushik
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP2006515366A priority Critical patent/JP2007520769A/en
Priority to GB0519863A priority patent/GB2417805B/en
Priority to DE112004001133T priority patent/DE112004001133T5/en
Publication of WO2005003971A2 publication Critical patent/WO2005003971A2/en
Publication of WO2005003971A3 publication Critical patent/WO2005003971A3/en
Priority to HK06103651A priority patent/HK1081301A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526Mutual exclusion algorithms
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083Power or thermal control instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061Partitioning or combining of resources

Abstract

A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
PCT/US2004/019373 2003-06-27 2004-06-16 Queued locks using monitor-memory wait WO2005003971A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006515366A JP2007520769A (en) 2003-06-27 2004-06-16 Queued lock using monitor memory wait
GB0519863A GB2417805B (en) 2003-06-27 2004-06-16 Management of resources when suspending a thread in a hyperthreading processor
DE112004001133T DE112004001133T5 (en) 2003-06-27 2004-06-16 Queue locks with monitor memory wait
HK06103651A HK1081301A1 (en) 2003-06-27 2006-03-23 Management of resources when suspending a thread in a hyperthreading processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/608,708 US7213093B2 (en) 2003-06-27 2003-06-27 Queued locks using monitor-memory wait
US10/608,708 2003-06-27

Publications (2)

Publication Number Publication Date
WO2005003971A2 WO2005003971A2 (en) 2005-01-13
WO2005003971A3 true WO2005003971A3 (en) 2005-07-14

Family

ID=33540657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/019373 WO2005003971A2 (en) 2003-06-27 2004-06-16 Queued locks using monitor-memory wait

Country Status (9)

Country Link
US (3) US7213093B2 (en)
JP (2) JP2007520769A (en)
KR (1) KR100864747B1 (en)
CN (1) CN100337206C (en)
DE (1) DE112004001133T5 (en)
GB (1) GB2417805B (en)
HK (1) HK1081301A1 (en)
TW (1) TWI266987B (en)
WO (1) WO2005003971A2 (en)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
US7236918B2 (en) * 2003-12-31 2007-06-26 International Business Machines Corporation Method and system for selective compilation of instrumentation entities into a simulation model of a digital design
US8607241B2 (en) 2004-06-30 2013-12-10 Intel Corporation Compare and exchange operation using sleep-wakeup mechanism
US20060031201A1 (en) * 2004-08-06 2006-02-09 Microsoft Corporation Life moment tagging and storage
US7590738B2 (en) * 2004-10-27 2009-09-15 Hewlett-Packard Development Company, L.P. Method and system for processing concurrent events in a provisional network
US20070004501A1 (en) * 2005-06-29 2007-01-04 Christopher Brewer Multi-core processing in a wagering game machine
US20070067502A1 (en) * 2005-09-22 2007-03-22 Silicon Integrated Systems Corp. Method for preventing long latency event
US7958510B2 (en) * 2005-12-30 2011-06-07 Intel Corporation Device, system and method of managing a resource request
US8094158B1 (en) * 2006-01-31 2012-01-10 Nvidia Corporation Using programmable constant buffers for multi-threaded processing
US7802073B1 (en) * 2006-03-29 2010-09-21 Oracle America, Inc. Virtual core management
US7882381B2 (en) 2006-06-29 2011-02-01 Intel Corporation Managing wasted active power in processors based on loop iterations and number of instructions executed since last loop
US8276151B2 (en) * 2006-09-06 2012-09-25 International Business Machines Corporation Determination of running status of logical processor
US7899663B2 (en) * 2007-03-30 2011-03-01 International Business Machines Corporation Providing memory consistency in an emulated processing environment
US8140823B2 (en) * 2007-12-03 2012-03-20 Qualcomm Incorporated Multithreaded processor with lock indicator
US8145849B2 (en) * 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US8640141B2 (en) * 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US8612977B2 (en) 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8788795B2 (en) 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8880853B2 (en) 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8316218B2 (en) * 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8452947B2 (en) * 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8386822B2 (en) * 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8250396B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8015379B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Wake-and-go mechanism with exclusive system bus response
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8086437B2 (en) * 2008-04-02 2011-12-27 Microsoft Corporation Modeling and simulating software contention
US20100262966A1 (en) * 2009-04-14 2010-10-14 International Business Machines Corporation Multiprocessor computing device
US8082315B2 (en) * 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US8145723B2 (en) * 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8886919B2 (en) * 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources
US8230201B2 (en) * 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
CN101876942A (en) * 2009-04-30 2010-11-03 卓望数码技术(深圳)有限公司 Terminal software testing method and device
US8156275B2 (en) * 2009-05-13 2012-04-10 Apple Inc. Power managed lock optimization
US8364862B2 (en) * 2009-06-11 2013-01-29 Intel Corporation Delegating a poll operation to another device
US8464035B2 (en) 2009-12-18 2013-06-11 Intel Corporation Instruction for enabling a processor wait state
CN102483708B (en) * 2010-07-07 2016-01-20 松下电器产业株式会社 Processor
US8516577B2 (en) * 2010-09-22 2013-08-20 Intel Corporation Regulating atomic memory operations to prevent denial of service attack
US20120144218A1 (en) * 2010-12-03 2012-06-07 International Business Machines Corporation Transferring Power and Speed from a Lock Requester to a Lock Holder on a System with Multiple Processors
KR101510028B1 (en) * 2010-12-21 2015-04-08 인텔 코포레이션 System and method for power management
US8713262B2 (en) * 2011-09-02 2014-04-29 Nvidia Corporation Managing a spinlock indicative of exclusive access to a system resource
CN103136099B (en) * 2011-12-02 2017-08-25 腾讯科技(深圳)有限公司 Method, pseudo-terminal, background server and the system of test software
US20150143071A1 (en) * 2011-12-30 2015-05-21 Ravi L. Sahita Memory event notification
US8966494B2 (en) * 2012-03-16 2015-02-24 Arm Limited Apparatus and method for processing threads requiring resources
US8943505B2 (en) 2012-08-24 2015-01-27 National Instruments Corporation Hardware assisted real-time scheduler using memory monitoring
US20140075163A1 (en) 2012-09-07 2014-03-13 Paul N. Loewenstein Load-monitor mwait
US9141454B2 (en) * 2012-12-27 2015-09-22 Intel Corporation Signaling software recoverable errors
US9558132B2 (en) * 2013-08-14 2017-01-31 Intel Corporation Socket management with reduced latency packet processing
US10705961B2 (en) 2013-09-27 2020-07-07 Intel Corporation Scalably mechanism to implement an instruction that monitors for writes to an address
JP6227151B2 (en) * 2014-10-03 2017-11-08 インテル・コーポレーション A scalable mechanism for executing monitoring instructions for writing to addresses
US9760511B2 (en) * 2014-10-08 2017-09-12 International Business Machines Corporation Efficient interruption routing for a multithreaded processor
US9342384B1 (en) 2014-12-18 2016-05-17 Intel Corporation Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
US11023233B2 (en) 2016-02-09 2021-06-01 Intel Corporation Methods, apparatus, and instructions for user level thread suspension
US10185564B2 (en) 2016-04-28 2019-01-22 Oracle International Corporation Method for managing software threads dependent on condition variables
US11061730B2 (en) * 2016-11-18 2021-07-13 Red Hat Israel, Ltd. Efficient scheduling for hyper-threaded CPUs using memory monitoring
US10481936B2 (en) 2017-02-22 2019-11-19 Red Hat Israel, Ltd. Efficient virtual machine memory monitoring with hyper-threading
US11068407B2 (en) 2018-10-26 2021-07-20 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
US10884740B2 (en) 2018-11-08 2021-01-05 International Business Machines Corporation Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US11106608B1 (en) 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
US20220394023A1 (en) * 2021-06-04 2022-12-08 Winkk, Inc Encryption for one-way data stream
US11693776B2 (en) 2021-06-18 2023-07-04 International Business Machines Corporation Variable protection window extension for a target address of a store-conditional request

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0361176A2 (en) * 1988-09-29 1990-04-04 International Business Machines Corporation Method and apparatus for communicating data between multiple tasks in data processing systems
US5790851A (en) * 1997-04-15 1998-08-04 Oracle Corporation Method of sequencing lock call requests to an O/S to avoid spinlock contention within a multi-processor environment
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
WO2003058447A2 (en) * 2001-12-31 2003-07-17 Intel Corporation A method and apparatus for suspending execution of a thread until a specified memory access occurs

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274809A (en) * 1988-05-26 1993-12-28 Hitachi, Ltd. Task execution control method for a multiprocessor system with enhanced post/wait procedure
JPH01300365A (en) * 1988-05-30 1989-12-04 Nippon Telegr & Teleph Corp <Ntt> Exclusive control system for multi-processor system
JPH05225149A (en) * 1992-02-13 1993-09-03 Toshiba Corp Lock system
US5933627A (en) 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
CN1147785C (en) 1996-08-27 2004-04-28 松下电器产业株式会社 Multi-program-flow synchronous processor independently processing multiple instruction stream, soft controlling processing function of every instrunetion
JPH10149285A (en) * 1996-11-18 1998-06-02 Hitachi Ltd Method for controlling execution of instruction and information processor
US6512591B1 (en) * 1997-02-19 2003-01-28 Hewlett-Packard Company Multiple peripheral support for a single physical port in a host-based printing system
US6463527B1 (en) 1997-03-21 2002-10-08 Uzi Y. Vishkin Spawn-join instruction set architecture for providing explicit multithreading
US6035374A (en) * 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
GB2345555A (en) * 1999-01-05 2000-07-12 Ibm Controlling device access in a network
US6522649B1 (en) * 2000-04-07 2003-02-18 Omneon Video Networks Method of distributing video reference signals as isochronous network packets
JP4253796B2 (en) * 2001-11-08 2009-04-15 富士通株式会社 Computer and control method
US20030126379A1 (en) 2001-12-31 2003-07-03 Shiv Kaushik Instruction sequences for suspending execution of a thread until a specified memory access occurs
US20030126416A1 (en) 2001-12-31 2003-07-03 Marr Deborah T. Suspending execution of a thread in a multi-threaded processor
US7127561B2 (en) 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US6839816B2 (en) * 2002-02-26 2005-01-04 International Business Machines Corporation Shared cache line update mechanism
US7234143B2 (en) * 2002-06-20 2007-06-19 Hewlett-Packard Development Company, L.P. Spin-yielding in multi-threaded systems
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
JP4376692B2 (en) * 2004-04-30 2009-12-02 富士通株式会社 Information processing device, processor, processor control method, information processing device control method, cache memory
US7257679B2 (en) * 2004-10-01 2007-08-14 Advanced Micro Devices, Inc. Sharing monitored cache lines across multiple cores

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0361176A2 (en) * 1988-09-29 1990-04-04 International Business Machines Corporation Method and apparatus for communicating data between multiple tasks in data processing systems
US5790851A (en) * 1997-04-15 1998-08-04 Oracle Corporation Method of sequencing lock call requests to an O/S to avoid spinlock contention within a multi-processor environment
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
WO2003058447A2 (en) * 2001-12-31 2003-07-17 Intel Corporation A method and apparatus for suspending execution of a thread until a specified memory access occurs
GB2400947A (en) * 2001-12-31 2004-10-27 Intel Corp A method and apparatus for suspending execution of a thread until a specified memory access occurs
DE10297596T5 (en) * 2001-12-31 2004-12-02 Intel Corporation, Santa Clara Method and apparatus for suspending thread execution until specified memory access occurs

Also Published As

Publication number Publication date
GB2417805B (en) 2007-11-21
CN1577282A (en) 2005-02-09
DE112004001133T5 (en) 2006-05-11
US20070162774A1 (en) 2007-07-12
WO2005003971A2 (en) 2005-01-13
JP2010044770A (en) 2010-02-25
GB0519863D0 (en) 2005-11-09
KR100864747B1 (en) 2008-10-22
US7640384B2 (en) 2009-12-29
US7213093B2 (en) 2007-05-01
JP2007520769A (en) 2007-07-26
US20040267996A1 (en) 2004-12-30
TWI266987B (en) 2006-11-21
GB2417805A (en) 2006-03-08
US20080022141A1 (en) 2008-01-24
HK1081301A1 (en) 2006-05-12
TW200525348A (en) 2005-08-01
CN100337206C (en) 2007-09-12
US7328293B2 (en) 2008-02-05
KR20060029151A (en) 2006-04-04

Similar Documents

Publication Publication Date Title
WO2005003971A3 (en) Queued locks using monitor-memory wait
WO2005052756A3 (en) Remote web site security system
SG122058A1 (en) Remote maintenance system, monitoring center computer used for the same, monitoring system and method of communication for maintenance
GB2403042B (en) Modular monitoring, control and device management for use with process control systems
FR2837963B1 (en) ANTI-THEFT ANTI-THEFT ALARM SYSTEM WITH ACTIVE ASSISTANCE REQUEST AND ASSOCIATED METHOD
WO2004097637A3 (en) Lock and transaction management
GB2410154B (en) Method and system for monitoring a selected region of an airspace associated with local area networks of computing devices
AU2003227252A1 (en) Electronic locking system, locking management device, locking device management method, and program
DE60213551D1 (en) Easy-to-multi-communication conversion device, method and computer program product, as well as monitoring system
HK1119476A1 (en) Apparatus, system and method for reducing false alarms, invalid security deactivation and internal theft
AU2003261259A1 (en) Monitoring system and methods for monitoring processes and devices
WO2004068250A3 (en) Operating utility devices in a master-agent network environment
WO2007011419A3 (en) Status monitoring system and method
AU2001247351A1 (en) Method and system for dynamic network intrusion monitoring, detection and response
WO2005086760A3 (en) Monitoring and maintaining equipment and machinery
AU2002361483A8 (en) System and method for video content analysis-based detection, surveillance and alarm management
AU2001286374A1 (en) Computer security event management system
GB0224536D0 (en) System amd method of defining the security condition of a computer system
WO2005102408A3 (en) A telescoping perfusion management system
GB0800078D0 (en) A mobile security monitoring method and system and an alarm security node in the system
WO2004053667A3 (en) Identity management system for automatic user authentication
WO2007034394A3 (en) System and method for providing event summary information using an encoded ecg waveform
AU2754101A (en) System for monitoring, processing, and presenting sleep time data
AU2003242598A8 (en) Method, system and computer program for the secured management of network devices
AU2003209385A1 (en) Aircraft with security alarm system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 0519863.5

Country of ref document: GB

Ref document number: 0519863

Country of ref document: GB

WWE Wipo information: entry into national phase

Ref document number: 2006515366

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020057025081

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020057025081

Country of ref document: KR

RET De translation (de og part 6b)

Ref document number: 112004001133

Country of ref document: DE

Date of ref document: 20060511

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 112004001133

Country of ref document: DE

122 Ep: pct application non-entry in european phase
REG Reference to national code

Ref country code: DE

Ref legal event code: 8607