WO2005004212A1 - Growth method of nitride semiconductor epitaxial layers - Google Patents

Growth method of nitride semiconductor epitaxial layers Download PDF

Info

Publication number
WO2005004212A1
WO2005004212A1 PCT/KR2004/001665 KR2004001665W WO2005004212A1 WO 2005004212 A1 WO2005004212 A1 WO 2005004212A1 KR 2004001665 W KR2004001665 W KR 2004001665W WO 2005004212 A1 WO2005004212 A1 WO 2005004212A1
Authority
WO
WIPO (PCT)
Prior art keywords
nitride semiconductor
semiconductor epitaxial
epitaxial layer
layer
temperature
Prior art date
Application number
PCT/KR2004/001665
Other languages
French (fr)
Inventor
Euijoon Yoon
Hyunseok Na
Original Assignee
Seoul National University Industry Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seoul National University Industry Foundation filed Critical Seoul National University Industry Foundation
Priority to DE112004001230T priority Critical patent/DE112004001230B4/en
Priority to JP2006518548A priority patent/JP2007528587A/en
Priority to US10/563,854 priority patent/US7964483B2/en
Publication of WO2005004212A1 publication Critical patent/WO2005004212A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Definitions

  • the present invention relates to a method for growing a nitride semiconductor epitaxial layer, and more particularly, to a method for growing a nitride semiconductor epitaxial layer in which a substrate is used and which has no warpage and a low lattice defect density, whereby it is advantageous in fabricating optical devices and electronic devices of high efficiency.
  • U.S. Patent No. 4,855,249 discloses a technology in which an AIN buffer layer is grown on a sapphire substrate at low temperature and an Al x Ga ⁇ - x N (0 ⁇ x ⁇ 1) layer is then grown.
  • U.S. Patent No. 5,290,393 discloses a technology in which an Al ⁇ - x Ga x N (0 ⁇ x ⁇ 1) buffer layer is grown on a sapphire substrate at a temperature ranging between 200 ° C and 900 ° C and an AI ⁇ GaxN (0 ⁇ x ⁇ 1) layer is then grown at a temperature ranging between 900 ° C and 1150°C.
  • Patent No. 6,051 ,847 discloses a technology in which in a process wherein a buffer layer containing indium is grown on a sapphire substrate and the GaN based compound semiconductor layer is then grown on the buffer layer, indium contained in the buffer layer is diffused into a GaN based compound semiconductor layer. Meanwhile, in order to solve such mismatch, technologies using a substrate made of GaN have been proposed. However, these methods have a problem in that light emitting devices using the GaN substrate have not yet been commercialized due to difficulty in growing a GaN bulk and a high cost spent in the growth.
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for growing a nitride semiconductor epitaxial layer wherein a nitride semiconductor epitaxial layer with low defects for fabricating a nitride based optical device and electronic device of high efficiency can be grown by reducing warpage of a substrate due to stress.
  • a method for growing a nitride semiconductor epitaxial layer including the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature.
  • the first and third nitride semiconductor epitaxial layers are made of a material whose equilibrium vapor pressure of nitrogen is lower than that of the second nitride semiconductor epitaxial layer.
  • the method for growing the nitride semiconductor epitaxial layer according to the present invention additionally includes a step of separating a part including the first nitride semiconductor epitaxial layer and the other part including the third nitride semiconductor epitaxial layer from each other.
  • a method for growing a nitride semiconductor epitaxial layer including a first step of growing a first nitride semiconductor epitaxial layer containing indium at a first temperature, a second step of growing a second nitride semiconductor epitaxial layer whose equilibrium vapor pressure of nitrogen is higher than that of the first nitride semiconductor epitaxial layer, on the first nitride semiconductor epitaxial layer at a second temperature, and a third step of releasing nitrogen from the first nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature to convert the first nitride semiconductor epitaxial layer into a metal layer.
  • a layer which is located below the first nitride semiconductor epitaxial layer may be a substrate or a nitride semiconductor epitaxial layer.
  • stress caused by the mismatch between a substrate and nitride semiconductor epitaxial layers is absorbed by a metal layer, stress applied to the nitride semiconductor epitaxial layers is relatively reduced. Therefore, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.
  • the metal layer may be eleminated. Therefore, a GaN based substrate for growing the nitride semiconductor epitaxial layers can be obtained.
  • warpage of a substrate is reduced by providing an indium-containing metal layer. Therefore, a new direction for fabricating a large area substrate with a diameter larger than 2 inches is presented.
  • FIGS. 1 to 4 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a first embodiment of the present invention
  • Fig. 5 shows a change in the equilibrium vapor pressure of nitrogen in the nitride semiconductor epitaxial layers depending on a temperature
  • Figs. 6 and 7 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a second embodiment of the present invention
  • Fig. 8 is a view for explaining another embodiment of the present invention.
  • Figs. 1 to 4 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a first embodiment of the present invention.
  • Fig. 5 shows a change in the equilibrium vapor pressure of nitrogen in the nitride semiconductor epitaxial layers depending on a temperature.
  • a nitride semiconductor epitaxial layer 110 is grown on a substrate 100.
  • the substrate 100 may be any kind of substrate such as a semiconductor substrate, an oxide substrate or a boride substrate.
  • the substrate 100 may be a Si, SiC, GaAs or ZrB 2 substrate and preferably is an
  • the nitride semiconductor epitaxial layer 110 consists of a nitride semiconductor containing at least one of gallium and aluminum. It is preferred that the nitride semiconductor epitaxial layer 110 is formed using Al x Ga ⁇ - x N (0 ⁇ x ⁇ 1) and can have a thickness of ⁇ m or more. In a preferred embodiment,
  • the nitride semiconductor epitaxial layer 110 is GaN that is formed by two steps of growing a low-temperature buffer layer and growing a high-temperature layer on the low-temperature buffer layer. It is, however, to be understood that any other nitride semiconductors can be grown on the substrate 100.
  • a nitride semiconductor epitaxial layer 120 that can be converted to a metal phase if the temperature is raised is grown on the nitride semiconductor epitaxial layer 110.
  • the nitride semiconductor epitaxial layer 120 consists of a nitride semiconductor containing indium and preferably consists of ln x Ga ⁇ - x N (0.5 ⁇ x ⁇ 1).
  • a step of growing the nitride semiconductor epitaxial layer 120 can be performed at a relatively low temperature of 300 ° C
  • nitride semiconductor epitaxial layer 120 preferably an InN layer is grown. Then, in a state where the nitride semiconductor epitaxial layer 120 is kept, a nitride semiconductor epitaxial layer 130 is grown on the nitride semiconductor epitaxial layer 120, for example, at a temperature similar to a growth temperature in the step of growing the nitride semiconductor epitaxial layer 120, i.e., at a temperature of 300°C to 800 ° C in this embodiment.
  • nitride semiconductor epitaxial layer 130 is composed of a nitride semiconductor containing at least one of gallium and aluminum, preferably Al ⁇ Ga-1- ⁇ N (0 ⁇ x ⁇ 1) and is grown using GaN in this embodiment. Conversion of the nitride semiconductor epitaxial layer 120 into a metal layer is performed by releasing nitrogen from t he n itride semiconductor e pitaxial I ayer 120 using a difference in the equilibrium vapor pressure of nitrogen within the nitride semiconductor epitaxial layer 120 and the nitride semiconductor epitaxial layers 110 and 130.
  • the thickness of the nitride semiconductor epitaxial layer 120 is too thin, a metal layer for relieving stress cannot be formed due to interdiffusion with the nitride semiconductor epitaxial layers 110 and 130 at the top and bottom of the nitride semiconductor epitaxial layer 120. Meanwhile, if the thickness of the nitride semiconductor epitaxial layer 120 is too thick, the occurrence of stress and defects in the nitride semiconductor epitaxial layer 120 can be problematic. Accordingly, it is necessary to grow the nitride semiconductor epitaxial layer 120 with a thickness that allows the metal layer to exist during the time period when a subsequent thick nitride semiconductor epitaxial layer is grown.
  • the nitride semiconductor epitaxial layer 1 30 serves a s a seed for a nitride semiconductor epitaxial layer that will be formed subsequently. If the nitride semiconductor epitaxial layer 130 is too thin, crystalloid can be degraded when the nitride semiconductor epitaxial layer 120 is converted to a metal phase in a subsequent process. Also, there is a possibility that the nitride semiconductor epitaxial layer 130 cannot serve as a seed sufficiently due to a change in the lattice constant, etc. resulting from interdiffusion with the metal layer. Meanwhile, if the thickness of the nitride semiconductor epitaxial layer 130 is too thick, a process wherein nitrogen is released from the nitride semiconductor epitaxial layer 120 becomes slow.
  • the nitride semiconductor epitaxial layer 130 is grown in thickness of about 1nm to 100nm.
  • a temperature is raised so that the nitride semiconductor epitaxial layer 120 can be converted to a metal phase.
  • nitrogen escapes only from the nitride semiconductor epitaxial layer 120 made of InxGal-xN, due to a difference in the equilibrium vapor pressure of nitrogen.
  • the nitride semiconductor epitaxial layer 120 is converted to a metal layer 120a.
  • a temperature can be raised to about 900 ° C or more.
  • epitaxial layer 120 for example, InN layer can be converted to an In metal phase due to a difference in the equilibrium vapor pressure if a temperature is
  • the In metal keeps the liquid state after it is converted to the metal phase. As the boiling point of the In metal is about 2074 °C , the In metal is not boiled over
  • the nitride semiconductor epitaxial layers 110 and 130 formed using GaN have the equilibrium vapor pressure of nitrogen that is lower than InN.
  • nitrogen i s not released from the nitride semiconductor epitaxial layers 110 and 130, which thus keep the solid phase.
  • the nitride semiconductor epitaxial layer 120 is converted to the metal layer 120a.
  • the nitride semiconductor epitaxial layer 130 is patterned to have an appropriate shape, the nitride semiconductor epitaxial layer 120 can be converted to the metal layer 120a.
  • nitride semiconductor epitaxial layer 130 is patterned to have an appropriate shape, some of the surface of the nitride semiconductor epitaxial layer 120 is exposed to environment of the growth chamber. It is thus possible to make the process of converting to the metal layer faster since discharge of nitrogen becomes faster.
  • a nitride epitaxial layer 140 is grown o n the nitride semiconductor epitaxial layer 130 which acts as a seed layer while stress generated upon growth is mitigated through the metal layer 120a. As the metal layer 120a that is converted from the nitride semiconductor epitaxial layer 120 absorbs stress, it can reduce warpage of a nitride semiconductor epitaxial layer that is subsequently grown at a high temperature.
  • Figs. 6 and 7 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a second embodiment of the present invention.
  • a carrier substrate 150 is attached on the nitride semiconductor epitaxial layer 140, thus securing the mechanical force.
  • a part including the substrate 100 and the other part including the nitride semiconductor epitaxial layer 140 are separated from each other by removing the interposed metal layer 120a using an acid solution.
  • a complex p rocess s in order to separate the s ubstrate, a complex p rocess s uch as a separating p rocess by irradiation of laser beam and/or a mechanical polishing process has been used.
  • the substrate can be easily separated by selectively etching only the interposed metal layer in an acid solution.
  • an additional chemical mechanical polishing (CMP) process is not required after the substrate has been separated.
  • the other part including the nitride semiconductor epitaxial layer 140 can be used as a new substrate.
  • the substrate can be separated as a free standing substrate by selectively etching only the metal layer 120a without using the carrier substrate 150.
  • Fig. 8 is a view for explaining another embodiment of the present invention.
  • the metal layer 120a is formed directly on the substrate 100, but not on the nitride semiconductor epitaxial layer 110.
  • the metal layer 120a is formed and another nitride semiconductor epitaxial layer is then formed on the nitride semiconductor epitaxial layer 130 in the same manner as in the embodiment of Fig. 2, except that the growth of the nitride semiconductor epitaxial layer 110 is omitted.
  • the nitride semiconductor epitaxial layer 120 consists of a nitride semiconductor containing indium, preferably InxGal-xN (0.5 ⁇ x ⁇ 1), more preferably InN.
  • the nitride semiconductor epitaxial layer 130 is a nitride semiconductor containing at least one of gallium and aluminum, preferably Al x Ga ⁇ - x N (0 ⁇ x ⁇ 1), more preferably GaN. While the present invention has been described with reference to particular illustrative embodiments, it is not to be restricted by the embodiments. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.
  • the present invention can be applied to light emitting devices such as a light emitting diode and a laser diode by growing a plurality of nitride semiconductors layer including an active layer for generating light by recombination of electrons and holes, on the metal layer.

Abstract

The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial Iayer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby , it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.

Description

GROWTH METHOD OF NITRIDE SEMICONDUCTOR EPITAXIAL LAYERS
[Technical Field] The present invention relates to a method for growing a nitride semiconductor epitaxial layer, and more particularly, to a method for growing a nitride semiconductor epitaxial layer in which a substrate is used and which has no warpage and a low lattice defect density, whereby it is advantageous in fabricating optical devices and electronic devices of high efficiency.
[Background Art] In case of a nitride semiconductor epitaxial layer that is grown on a substrate, lots of crystal defects occur due to a mismatch of the lattice constant and a difference in the coefficient of thermal expansion. Warpage of the substrate is caused by internal stress. Moreover, the warpage of the substrate acts as hindrance in fabricating a large area substrate.
In order to overcome such mismatch between the s ubstrate and the nitride semiconductor epitaxial layer, U.S. Patent No. 4,855,249 discloses a technology in which an AIN buffer layer is grown on a sapphire substrate at low temperature and an AlxGaι-xN (0≤x<1) layer is then grown. Further, U.S. Patent No. 5,290,393 discloses a technology in which an Alι-xGaxN (0<x<1) buffer layer is grown on a sapphire substrate at a temperature ranging between 200°C and 900°C and an AI^GaxN (0<x<1) layer is then grown at a temperature ranging between 900 °C and 1150°C. Furthermore, U.S. Patent No. 6,051 ,847 discloses a technology in which in a process wherein a buffer layer containing indium is grown on a sapphire substrate and the GaN based compound semiconductor layer is then grown on the buffer layer, indium contained in the buffer layer is diffused into a GaN based compound semiconductor layer. Meanwhile, in order to solve such mismatch, technologies using a substrate made of GaN have been proposed. However, these methods have a problem in that light emitting devices using the GaN substrate have not yet been commercialized due to difficulty in growing a GaN bulk and a high cost spent in the growth.
[Disclosure] [Technical Problem] Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for growing a nitride semiconductor epitaxial layer wherein a nitride semiconductor epitaxial layer with low defects for fabricating a nitride based optical device and electronic device of high efficiency can be grown by reducing warpage of a substrate due to stress. [Technical Solution] To achieve the above object, according to one aspect of the present invention, there is provided a method for growing a nitride semiconductor epitaxial layer, including the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature. Furthermore, in the method for growing the nitride semiconductor epitaxial layer according to the present invention, the first and third nitride semiconductor epitaxial layers are made of a material whose equilibrium vapor pressure of nitrogen is lower than that of the second nitride semiconductor epitaxial layer. In addition, the method for growing the nitride semiconductor epitaxial layer according to the present invention additionally includes a step of separating a part including the first nitride semiconductor epitaxial layer and the other part including the third nitride semiconductor epitaxial layer from each other. According to another aspect of the present invention, there is also provided a method for growing a nitride semiconductor epitaxial layer, including a first step of growing a first nitride semiconductor epitaxial layer containing indium at a first temperature, a second step of growing a second nitride semiconductor epitaxial layer whose equilibrium vapor pressure of nitrogen is higher than that of the first nitride semiconductor epitaxial layer, on the first nitride semiconductor epitaxial layer at a second temperature, and a third step of releasing nitrogen from the first nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature to convert the first nitride semiconductor epitaxial layer into a metal layer. It is preferred that a layer which is located below the first nitride semiconductor epitaxial layer may be a substrate or a nitride semiconductor epitaxial layer. [Advantageous Effects] According to the present invention, since stress caused by the mismatch between a substrate and nitride semiconductor epitaxial layers is absorbed by a metal layer, stress applied to the nitride semiconductor epitaxial layers is relatively reduced. Therefore, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate. According to the present invention, after nitride semiconductor epitaxial layers comprising a metal layer have been grown, the metal layer may be eleminated. Therefore, a GaN based substrate for growing the nitride semiconductor epitaxial layers can be obtained. According to the present invention, warpage of a substrate is reduced by providing an indium-containing metal layer. Therefore, a new direction for fabricating a large area substrate with a diameter larger than 2 inches is presented.
[Description of Drawings] Figs. 1 to 4 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a first embodiment of the present invention; Fig. 5 shows a change in the equilibrium vapor pressure of nitrogen in the nitride semiconductor epitaxial layers depending on a temperature; Figs. 6 and 7 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a second embodiment of the present invention; and Fig. 8 is a view for explaining another embodiment of the present invention.
[Mode for Invention] The present invention will now be described in detail in connection with preferred embodiments with reference to the accompanying drawings. Figs. 1 to 4 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a first embodiment of the present invention. Fig. 5 shows a change in the equilibrium vapor pressure of nitrogen in the nitride semiconductor epitaxial layers depending on a temperature. Referring to Fig. 1 , a nitride semiconductor epitaxial layer 110 is grown on a substrate 100. The substrate 100 may be any kind of substrate such as a semiconductor substrate, an oxide substrate or a boride substrate. The substrate 100 may be a Si, SiC, GaAs or ZrB2 substrate and preferably is an
AI2O3 substrate. However, it is to be noted that any kind of substrate can be used if it is a single crystal substrate on which a nitride based semiconductor epitaxial layer can be grown, and thus the substrate 100 is not limited to the above. The nitride semiconductor epitaxial layer 110 consists of a nitride semiconductor containing at least one of gallium and aluminum. It is preferred that the nitride semiconductor epitaxial layer 110 is formed using AlxGaι-xN (0<x<1) and can have a thickness of \μm or more. In a preferred embodiment,
the nitride semiconductor epitaxial layer 110 is GaN that is formed by two steps of growing a low-temperature buffer layer and growing a high-temperature layer on the low-temperature buffer layer. It is, however, to be understood that any other nitride semiconductors can be grown on the substrate 100. Referring to Fig. 2, a nitride semiconductor epitaxial layer 120 that can be converted to a metal phase if the temperature is raised is grown on the nitride semiconductor epitaxial layer 110. The nitride semiconductor epitaxial layer 120 consists of a nitride semiconductor containing indium and preferably consists of lnxGaι-xN (0.5<x≤1). A step of growing the nitride semiconductor epitaxial layer 120 can be performed at a relatively low temperature of 300 °C
to 800 °C. Thus, after the nitride semiconductor epitaxial layer 110 consisting
of AlxGaι-χN (0<x<1) is grown at a growth temperature, the growth temperature is lowered, then the nitride semiconductor epitaxial layer 120, preferably an InN layer is grown. Then, in a state where the nitride semiconductor epitaxial layer 120 is kept, a nitride semiconductor epitaxial layer 130 is grown on the nitride semiconductor epitaxial layer 120, for example, at a temperature similar to a growth temperature in the step of growing the nitride semiconductor epitaxial layer 120, i.e., at a temperature of 300°C to 800°C in this embodiment. The
nitride semiconductor epitaxial layer 130 is composed of a nitride semiconductor containing at least one of gallium and aluminum, preferably AlχGa-1-χN (0<x<1) and is grown using GaN in this embodiment. Conversion of the nitride semiconductor epitaxial layer 120 into a metal layer is performed by releasing nitrogen from t he n itride semiconductor e pitaxial I ayer 120 using a difference in the equilibrium vapor pressure of nitrogen within the nitride semiconductor epitaxial layer 120 and the nitride semiconductor epitaxial layers 110 and 130. If the thickness of the nitride semiconductor epitaxial layer 120 is too thin, a metal layer for relieving stress cannot be formed due to interdiffusion with the nitride semiconductor epitaxial layers 110 and 130 at the top and bottom of the nitride semiconductor epitaxial layer 120. Meanwhile, if the thickness of the nitride semiconductor epitaxial layer 120 is too thick, the occurrence of stress and defects in the nitride semiconductor epitaxial layer 120 can be problematic. Accordingly, it is necessary to grow the nitride semiconductor epitaxial layer 120 with a thickness that allows the metal layer to exist during the time period when a subsequent thick nitride semiconductor epitaxial layer is grown. The nitride semiconductor epitaxial layer 1 30 serves a s a seed for a nitride semiconductor epitaxial layer that will be formed subsequently. If the nitride semiconductor epitaxial layer 130 is too thin, crystalloid can be degraded when the nitride semiconductor epitaxial layer 120 is converted to a metal phase in a subsequent process. Also, there is a possibility that the nitride semiconductor epitaxial layer 130 cannot serve as a seed sufficiently due to a change in the lattice constant, etc. resulting from interdiffusion with the metal layer. Meanwhile, if the thickness of the nitride semiconductor epitaxial layer 130 is too thick, a process wherein nitrogen is released from the nitride semiconductor epitaxial layer 120 becomes slow. Thus, there is a possibility that the speed of conversion to a metal layer may be slow. For this reason, the nitride semiconductor epitaxial layer 130 is grown in thickness of about 1nm to 100nm. Referring to Fig. 3, a temperature is raised so that the nitride semiconductor epitaxial layer 120 can be converted to a metal phase. As described above, nitrogen escapes only from the nitride semiconductor epitaxial layer 120 made of InxGal-xN, due to a difference in the equilibrium vapor pressure of nitrogen. Thus, the nitride semiconductor epitaxial layer 120 is converted to a metal layer 120a. At this time, a temperature can be raised to about 900°C or more. Referring to Fig. 5, the nitride semiconductor
epitaxial layer 120, for example, InN layer can be converted to an In metal phase due to a difference in the equilibrium vapor pressure if a temperature is
900°C or more. As the melting point of an In metal is about 156.6°C , the In
metal keeps the liquid state after it is converted to the metal phase. As the boiling point of the In metal is about 2074 °C , the In metal is not boiled over
even in a subsequent growth temperature but keeps the liquid phase. On the other hand, the nitride semiconductor epitaxial layers 110 and 130 formed using GaN have the equilibrium vapor pressure of nitrogen that is lower than InN. Thus, nitrogen i s not released from the nitride semiconductor epitaxial layers 110 and 130, which thus keep the solid phase. In the above, in a state where the nitride semiconductor epitaxial layer 130 covers the entire surface of the nitride semiconductor epitaxial layer 120, the nitride semiconductor epitaxial layer 120 is converted to the metal layer 120a. However, after the nitride semiconductor epitaxial layer 130 is patterned to have an appropriate shape, the nitride semiconductor epitaxial layer 120 can be converted to the metal layer 120a. If the nitride semiconductor epitaxial layer 130 is patterned to have an appropriate shape, some of the surface of the nitride semiconductor epitaxial layer 120 is exposed to environment of the growth chamber. It is thus possible to make the process of converting to the metal layer faster since discharge of nitrogen becomes faster. Referring n ext to Fig. 4, a nitride epitaxial layer 140 is grown o n the nitride semiconductor epitaxial layer 130 which acts as a seed layer while stress generated upon growth is mitigated through the metal layer 120a. As the metal layer 120a that is converted from the nitride semiconductor epitaxial layer 120 absorbs stress, it can reduce warpage of a nitride semiconductor epitaxial layer that is subsequently grown at a high temperature. Figs. 6 and 7 are cross-sectional views showing a method for growing a nitride semiconductor epitaxial layer according to a second embodiment of the present invention. Referring to Fig. 6 and Fig. 7, after the step of Fig. 4 has been performed, a carrier substrate 150 is attached on the nitride semiconductor epitaxial layer 140, thus securing the mechanical force. A part including the substrate 100 and the other part including the nitride semiconductor epitaxial layer 140 are separated from each other by removing the interposed metal layer 120a using an acid solution. In a conventional method, in order to separate the s ubstrate, a complex p rocess s uch as a separating p rocess by irradiation of laser beam and/or a mechanical polishing process has been used. In the present invention, however, the substrate can be easily separated by selectively etching only the interposed metal layer in an acid solution. Also, if the interface between the metal layer 120a and the nitride semiconductor epitaxial layer 130 is in an atomic layer level, an additional chemical mechanical polishing (CMP) process is not required after the substrate has been separated. After separated, the other part including the nitride semiconductor epitaxial layer 140 can be used as a new substrate. Alternatively, the substrate can be separated as a free standing substrate by selectively etching only the metal layer 120a without using the carrier substrate 150. Fig. 8 is a view for explaining another embodiment of the present invention. The metal layer 120a is formed directly on the substrate 100, but not on the nitride semiconductor epitaxial layer 110. In this embodiment, the metal layer 120a is formed and another nitride semiconductor epitaxial layer is then formed on the nitride semiconductor epitaxial layer 130 in the same manner as in the embodiment of Fig. 2, except that the growth of the nitride semiconductor epitaxial layer 110 is omitted. Even in this embodiment, the nitride semiconductor epitaxial layer 120 consists of a nitride semiconductor containing indium, preferably InxGal-xN (0.5<x<1), more preferably InN. The nitride semiconductor epitaxial layer 130 is a nitride semiconductor containing at least one of gallium and aluminum, preferably AlxGaι-xN (0<x<1), more preferably GaN. While the present invention has been described with reference to particular illustrative embodiments, it is not to be restricted by the embodiments. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.
[Industrial Applicability] The present invention can be applied to light emitting devices such as a light emitting diode and a laser diode by growing a plurality of nitride semiconductors layer including an active layer for generating light by recombination of electrons and holes, on the metal layer.

Claims

1. Growth method of nitride semiconductor epitaxial layer comprising: a first step of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature; a second step of growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature; and a third step of releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature.
2. The growth method of nitride semiconductor epitaxial layer of claim 1, wherein the first and third nitride semiconductor epitaxial layers are made of a material whose equilibrium vapor pressure of nitrogen is lower than that of the second nitride semiconductor epitaxial layer.
3. The growth method of nitride semiconductor epitaxial layer of claim 1 , the second nitride semiconductor epitaxial layer is converted into a metal layer in the third step.
4. The growth method of nitride semiconductor epitaxial layer of claim 1, further comprising: a fourth step of growing a fourth nitride semiconductor epitaxial layer on the third nitride semiconductor epitaxial layer after releasing nitrogen from the second nitride semiconductor epitaxial layer.
5. The growth method of nitride semiconductor epitaxial layer of claim 1 , wherein the second nitride semiconductor epitaxial layer is made of lnxGaι-xN (0.5<x<1).
6. The growth method of nitride semiconductor epitaxial layer of claim 1, wherein the first and third nitride semiconductor epitaxial layers are made of
AlχGaι-xN (0<x<1).
7. The growth method of nitride semiconductor epitaxial layer of claim 1 , wherein the first temperature in the first step is in a range of 300 °C to 800 °C.
8. The growth method of nitride semiconductor epitaxial layer of claim 1 , wherein the second temperature in the second step is in a range of 300 °C to
800 °C.
9. The growth method of nitride semiconductor epitaxial layer of claim 1 , wherein the third nitride semiconductor epitaxial layer has a thickness in a range of 1nm to 100nm.
10. The growth method of nitride semiconductor epitaxial layer of claim
I , wherein the third temperature in the third step is 900 °C or more.
11. The growth method of nitride semiconductor epitaxial layer of claim 1 , wherein the first nitride semiconductor epitaxial layer is grown on a substrate.
12. The growth method of nitride semiconductor epitaxial layer of claim
I I, wherein the first nitride semiconductor epitaxial layer comprises a buffer layer grown at a relatively low temperature and an un-doped GaN layer grown on the buffer layer.
13. The growth method of nitride semiconductor epitaxial layer of claim 1 , further comprising: a step of patterning the third nitride semiconductor epitaxial layer, prior to the third step.
14. The growth method of nitride semiconductor epitaxial layer of claim 3, further comprising: a step of separating a part including the first nitride semiconductor epitaxial layer from the other part including the third nitride semiconductor epitaxial layer.
15. Growth method of nitride semiconductor epitaxial layer comprising: growing a buffer layer on a substrate and an un-doped GaN layer on the buffer layer; growing InN layer on the un-doped GaN layer; growing a GaN layer on the InN layer; converting the InN layer into a metal layer; and growing AlxlnyGaι-yN (0<x<1 , 0<y<1) on the GaN layer.
16. Growth method of nitride semiconductor epitaxial layer comprising: a first step of growing a first nitride semiconductor epitaxial layer containing indium at a first temperature; a second step of growing a second nitride semiconductor epitaxial layer whose equilibrium vapor pressure of nitrogen is higher than that of the first nitride semiconductor epitaxial layer, on the first nitride semiconductor epitaxial layer at a second temperature; and a third step of releasing nitrogen from the first nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature to convert the first nitride semiconductor epitaxial layer into a metal layer.
17. The growth method of nitride semiconductor epitaxial layer of claim 16, wherein the first nitride semiconductor epitaxial layer is grown on a substrate.
18. The growth method of nitride semiconductor epitaxial layer of claim
16, wherein the first nitride semiconductor epitaxial layer is grown on a compound semiconductor epitaxial layer grown on a substrate.
19. The growth method of nitride semiconductor epitaxial layer of claim
17, the first nitride semiconductor epitaxial layer is made of lnxGaι-xN (0.5<x≤1 ) and the second nitride semiconductor epitaxial layer is made of GaN.
PCT/KR2004/001665 2003-07-08 2004-07-07 Growth method of nitride semiconductor epitaxial layers WO2005004212A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112004001230T DE112004001230B4 (en) 2003-07-08 2004-07-07 Growth methods for nitride semiconductor epitaxial layers
JP2006518548A JP2007528587A (en) 2003-07-08 2004-07-07 Method for growing nitride semiconductor epitaxial layer
US10/563,854 US7964483B2 (en) 2003-07-08 2004-07-07 Growth method for nitride semiconductor epitaxial layers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2003-0046119 2003-07-08
KR10-2003-0046119A KR100531178B1 (en) 2003-07-08 2003-07-08 Growth method of nitride epitaxial layer using conversion of nitride interlayer into metallic phase

Publications (1)

Publication Number Publication Date
WO2005004212A1 true WO2005004212A1 (en) 2005-01-13

Family

ID=36746286

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2004/001665 WO2005004212A1 (en) 2003-07-08 2004-07-07 Growth method of nitride semiconductor epitaxial layers

Country Status (6)

Country Link
US (1) US7964483B2 (en)
JP (1) JP2007528587A (en)
KR (1) KR100531178B1 (en)
CN (1) CN100447948C (en)
DE (1) DE112004001230B4 (en)
WO (1) WO2005004212A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1750311A2 (en) 2005-08-01 2007-02-07 Avago Technologies ECBU IP (Singapore) Pte. Ltd. Gallium nitride device substrate comprising a gallium nitride based buffer layer and method of manufacturing the same
US8486771B2 (en) 2008-09-24 2013-07-16 Soitec Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US8836081B2 (en) 2008-10-30 2014-09-16 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749906B2 (en) 2006-02-22 2010-07-06 Intel Corporation Using unstable nitrides to form semiconductor structures
US20100098960A1 (en) * 2007-06-18 2010-04-22 Dominguez Juan E Magnetic insulator nanolaminate device for integrated silicon voltage regulators
JP2010147117A (en) * 2008-12-17 2010-07-01 Mitsubishi Electric Corp Manufacturing method of nitride semiconductor device
JP5022396B2 (en) * 2009-03-10 2012-09-12 株式会社沖データ Manufacturing method of semiconductor composite device
US9564320B2 (en) * 2010-06-18 2017-02-07 Soraa, Inc. Large area nitride crystal and method for making it
US8513798B2 (en) 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
CN101980383B (en) * 2010-09-27 2012-12-05 湘能华磊光电股份有限公司 Gallium nitride based Group III-V compound semiconductor LED epitaxial slice and method for growing same
CN103748662B (en) 2011-06-28 2016-11-09 圣戈班晶体及检测公司 Semiconductor substrate and forming method
JP5839479B2 (en) * 2012-04-05 2016-01-06 日本電信電話株式会社 Nitride semiconductor layer manufacturing method and nitride semiconductor growth substrate
CN103094421A (en) * 2013-01-28 2013-05-08 华中科技大学 Method for improving quality of aluminumnitride (AlN) of face a by utilizing of aluminium nitride indium (AlInN) self-imaging pattern
JP2016171196A (en) 2015-03-12 2016-09-23 株式会社東芝 Semiconductor device manufacturing method
US11466384B2 (en) 2019-01-08 2022-10-11 Slt Technologies, Inc. Method of forming a high quality group-III metal nitride boule or wafer using a patterned substrate
US11721549B2 (en) 2020-02-11 2023-08-08 Slt Technologies, Inc. Large area group III nitride crystals and substrates, methods of making, and methods of use
US11705322B2 (en) 2020-02-11 2023-07-18 Slt Technologies, Inc. Group III nitride substrate, method of making, and method of use

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000074495A (en) * 1999-05-21 2000-12-15 양계모 Method for fabricating a nitride compound semiconductor
JP2001168045A (en) * 1999-12-08 2001-06-22 Sony Corp Method of manufacturing nitride-based iii-v compound layer and method of manufacturing substrate using it

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175468A (en) * 1984-02-21 1985-09-09 Matsushita Electric Ind Co Ltd Manufacture of gallium nitride semiconductor device
JPS62119196A (en) * 1985-11-18 1987-05-30 Univ Nagoya Method for growing compound semiconductor
US5290393A (en) * 1991-01-31 1994-03-01 Nichia Kagaku Kogyo K.K. Crystal growth method for gallium nitride-based compound semiconductor
US5679152A (en) * 1994-01-27 1997-10-21 Advanced Technology Materials, Inc. Method of making a single crystals Ga*N article
DE19640594B4 (en) * 1996-10-01 2016-08-04 Osram Gmbh module
JPH10107006A (en) * 1996-10-02 1998-04-24 Hitachi Ltd Vapor phase etching method of gallium nitride compound semiconductor
US6051847A (en) * 1997-05-21 2000-04-18 Matsushita Electric Industrial Co., Ltd. Gallium nitride compound-based semiconductor light emitting device and process for producing gallium nitride compound-based semiconductor thin film
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
JP2000012979A (en) * 1998-06-26 2000-01-14 Nichia Chem Ind Ltd Method for manufacturing nitride semiconductor substrate
JP2000323797A (en) * 1999-05-10 2000-11-24 Pioneer Electronic Corp Nitride semiconductor laser and its manufacture
JP3438675B2 (en) * 1999-10-22 2003-08-18 日亜化学工業株式会社 Method for growing nitride semiconductor
JP4408509B2 (en) * 1999-12-24 2010-02-03 株式会社アルバック Method for forming group III nitride thin film
US6447604B1 (en) * 2000-03-13 2002-09-10 Advanced Technology Materials, Inc. Method for achieving improved epitaxy quality (surface texture and defect density) on free-standing (aluminum, indium, gallium) nitride ((al,in,ga)n) substrates for opto-electronic and electronic devices
DE10051465A1 (en) 2000-10-17 2002-05-02 Osram Opto Semiconductors Gmbh Method for producing a GaN-based semiconductor component
JP2002009003A (en) * 2000-06-23 2002-01-11 Ricoh Co Ltd Semiconductor substrate, its manufacturing method, and light emitting device
US6750158B2 (en) * 2001-05-18 2004-06-15 Matsushita Electric Industrial Co., Ltd. Method for producing a semiconductor device
JP4852795B2 (en) * 2001-05-30 2012-01-11 住友電気工業株式会社 Method for producing compound semiconductor
US6455340B1 (en) * 2001-12-21 2002-09-24 Xerox Corporation Method of fabricating GaN semiconductor structures using laser-assisted epitaxial liftoff

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000074495A (en) * 1999-05-21 2000-12-15 양계모 Method for fabricating a nitride compound semiconductor
JP2001168045A (en) * 1999-12-08 2001-06-22 Sony Corp Method of manufacturing nitride-based iii-v compound layer and method of manufacturing substrate using it

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1750311A2 (en) 2005-08-01 2007-02-07 Avago Technologies ECBU IP (Singapore) Pte. Ltd. Gallium nitride device substrate comprising a gallium nitride based buffer layer and method of manufacturing the same
EP1750311A3 (en) * 2005-08-01 2008-05-28 Avago Technologies ECBU IP (Singapore) Pte. Ltd. Gallium nitride device substrate comprising a gallium nitride based buffer layer and method of manufacturing the same
US8039869B2 (en) 2005-08-01 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Gallium nitride device substrate containing a lattice parameter altering element
US8486771B2 (en) 2008-09-24 2013-07-16 Soitec Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US8836081B2 (en) 2008-10-30 2014-09-16 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
US9368344B2 (en) 2008-10-30 2016-06-14 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US9312339B2 (en) 2010-12-23 2016-04-12 Soitec Strain relaxation using metal materials and related structures

Also Published As

Publication number Publication date
DE112004001230B4 (en) 2012-12-13
DE112004001230T5 (en) 2006-08-17
JP2007528587A (en) 2007-10-11
KR20050006409A (en) 2005-01-17
US7964483B2 (en) 2011-06-21
CN100447948C (en) 2008-12-31
US20060228901A1 (en) 2006-10-12
CN1820353A (en) 2006-08-16
KR100531178B1 (en) 2005-11-28

Similar Documents

Publication Publication Date Title
US7964483B2 (en) Growth method for nitride semiconductor epitaxial layers
US10879065B2 (en) III-V compound semiconductors in isolation regions and method forming same
US10586891B2 (en) Light emitting device with improved extraction efficiency
US8803189B2 (en) III-V compound semiconductor epitaxy using lateral overgrowth
US6100104A (en) Method for fabricating a plurality of semiconductor bodies
JP5371430B2 (en) Semiconductor substrate, method for manufacturing a self-supporting semiconductor substrate by hydride vapor phase epitaxy, and mask layer used therefor
JP4591276B2 (en) Manufacturing method of semiconductor light emitting device
JP6307547B2 (en) Semiconductor light emitting device and method including light extraction structure
TWI440073B (en) Method for fabricating circuit structure
JP2010056458A (en) Method of manufacturing light emitting element
CN100505164C (en) Fabrication process of nitride semiconductor substrate and composite material substrate
JP2007106665A (en) Gallium nitride device substrate containing lattice parameter altering element
JPH10321911A (en) Method for manufacturing epitaxial layer of compound semiconductor on single-crystal silicon and light-emitting diode manufactured therewith
US20070298592A1 (en) Method for manufacturing single crystalline gallium nitride material substrate
CN115579437A (en) Epitaxial chip structure
CN109755358B (en) Vertical structure device and preparation method thereof
US20050090032A1 (en) Method of manufacturing nitride semiconductor light emitting device
KR100952015B1 (en) Fabrication method for a semiconductor device
US8552465B2 (en) Method for reducing stress in epitaxial growth
KR20120131292A (en) Method for fabricating a light emitting device
KR20100020936A (en) Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate
KR101679397B1 (en) Method for fabricating vertical light emitting device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480019440.6

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006518548

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2006228901

Country of ref document: US

Ref document number: 10563854

Country of ref document: US

RET De translation (de og part 6b)

Ref document number: 112004001230

Country of ref document: DE

Date of ref document: 20060817

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 112004001230

Country of ref document: DE

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607

WWP Wipo information: published in national office

Ref document number: 10563854

Country of ref document: US

122 Ep: pct application non-entry in european phase