WO2005004459A3 - Method and apparatus for delayed recursion decoder - Google Patents
Method and apparatus for delayed recursion decoder Download PDFInfo
- Publication number
- WO2005004459A3 WO2005004459A3 PCT/US2004/020376 US2004020376W WO2005004459A3 WO 2005004459 A3 WO2005004459 A3 WO 2005004459A3 US 2004020376 W US2004020376 W US 2004020376W WO 2005004459 A3 WO2005004459 A3 WO 2005004459A3
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- WO
- WIPO (PCT)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/395—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04756074A EP1645112A4 (en) | 2003-06-24 | 2004-06-24 | Method and apparatus for delayed recursion decoder |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/603,388 | 2003-06-24 | ||
US10/603,388 US7206363B2 (en) | 2003-06-24 | 2003-06-24 | Method and apparatus for delayed recursion decoder |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005004459A2 WO2005004459A2 (en) | 2005-01-13 |
WO2005004459A3 true WO2005004459A3 (en) | 2006-06-08 |
Family
ID=33539721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/020376 WO2005004459A2 (en) | 2003-06-24 | 2004-06-24 | Method and apparatus for delayed recursion decoder |
Country Status (3)
Country | Link |
---|---|
US (2) | US7206363B2 (en) |
EP (1) | EP1645112A4 (en) |
WO (1) | WO2005004459A2 (en) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7206363B2 (en) | 2003-06-24 | 2007-04-17 | Intersymbol Communications, Inc. | Method and apparatus for delayed recursion decoder |
KR100689039B1 (en) * | 2005-02-01 | 2007-03-09 | 삼성전자주식회사 | Analog viterbi decoder using circulating type decoding units which are connected in parallel |
US8831074B2 (en) | 2005-10-03 | 2014-09-09 | Clariphy Communications, Inc. | High-speed receiver architecture |
US7590927B1 (en) * | 2005-11-14 | 2009-09-15 | Link —A—Media Devices Corporation | Soft output viterbi detector with error event output |
US8271863B2 (en) * | 2006-10-18 | 2012-09-18 | Marvell World Trade Ltd. | Forward decision aided nonlinear Viterbi detector |
US9209937B2 (en) * | 2007-06-28 | 2015-12-08 | Telefonaktiebolaget L M Ericsson (Publ) | Reliable decoding of a high-speed shared control channel |
KR101284833B1 (en) | 2007-06-29 | 2013-07-10 | 한국과학기술원 | Apparatus and Method for Detection Maximum Likelihood of Multiple Input Multipke Output |
US8102938B2 (en) * | 2008-04-22 | 2012-01-24 | Finisar Corporation | Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator |
US8358729B2 (en) * | 2008-08-22 | 2013-01-22 | Finisar Corporation | Baseband phase-locked loop |
JP2010068029A (en) * | 2008-09-08 | 2010-03-25 | Sumitomo Electric Ind Ltd | Optical transceiver |
US8510642B2 (en) * | 2009-09-25 | 2013-08-13 | Stmicroelectronics, Inc. | System and method for map detector for symbol based error correction codes |
US9048941B2 (en) * | 2010-01-22 | 2015-06-02 | Mentor Graphics Corporation | Characteristic response extraction for non-linear transmit channels |
US8631309B2 (en) * | 2011-05-04 | 2014-01-14 | Pmc-Sierra, Inc. | Forward error correction with extended effective block size |
WO2013006028A1 (en) * | 2011-07-01 | 2013-01-10 | Mimos Berhad | A method to improve signal quality in a communication network |
US9286894B1 (en) * | 2012-01-31 | 2016-03-15 | Google Inc. | Parallel recognition |
US8681889B2 (en) | 2012-06-20 | 2014-03-25 | MagnaCom Ltd. | Multi-mode orthogonal frequency division multiplexing receiver for highly-spectrally-efficient communications |
US8781008B2 (en) | 2012-06-20 | 2014-07-15 | MagnaCom Ltd. | Highly-spectrally-efficient transmission using orthogonal frequency division multiplexing |
US8605832B1 (en) | 2012-06-20 | 2013-12-10 | MagnaCom Ltd. | Joint sequence estimation of symbol and phase with high tolerance of nonlinearity |
US9166834B2 (en) | 2012-06-20 | 2015-10-20 | MagnaCom Ltd. | Method and system for corrupt symbol handling for providing high reliability sequences |
US9088400B2 (en) | 2012-11-14 | 2015-07-21 | MagnaCom Ltd. | Hypotheses generation based on multidimensional slicing |
US8811548B2 (en) | 2012-11-14 | 2014-08-19 | MagnaCom, Ltd. | Hypotheses generation based on multidimensional slicing |
US9118519B2 (en) | 2013-11-01 | 2015-08-25 | MagnaCom Ltd. | Reception of inter-symbol-correlated signals using symbol-by-symbol soft-output demodulator |
US8804879B1 (en) | 2013-11-13 | 2014-08-12 | MagnaCom Ltd. | Hypotheses generation based on multidimensional slicing |
US9130637B2 (en) | 2014-01-21 | 2015-09-08 | MagnaCom Ltd. | Communication methods and systems for nonlinear multi-user environments |
US9496900B2 (en) | 2014-05-06 | 2016-11-15 | MagnaCom Ltd. | Signal acquisition in a multimode environment |
US8891701B1 (en) | 2014-06-06 | 2014-11-18 | MagnaCom Ltd. | Nonlinearity compensation for reception of OFDM signals |
US9246523B1 (en) | 2014-08-27 | 2016-01-26 | MagnaCom Ltd. | Transmitter signal shaping |
US9276619B1 (en) | 2014-12-08 | 2016-03-01 | MagnaCom Ltd. | Dynamic configuration of modulation and demodulation |
US9191247B1 (en) | 2014-12-09 | 2015-11-17 | MagnaCom Ltd. | High-performance sequence estimation system and method of operation |
US10243591B2 (en) | 2016-08-30 | 2019-03-26 | International Business Machines Corporation | Sequence detectors |
KR20180086853A (en) * | 2017-01-24 | 2018-08-01 | 한국전자통신연구원 | Method and apparatus for overlap-resistent dynamic routing |
US10608673B2 (en) * | 2017-12-22 | 2020-03-31 | Massachusetts Institute Of Technology | Decoding signals by guessing noise |
GB201918218D0 (en) | 2019-12-11 | 2020-01-22 | Maynooth Univ | A method of decoding a codeword |
US11431368B2 (en) | 2020-03-16 | 2022-08-30 | Massachusetts Institute Of Technology | Noise recycling |
WO2021252066A1 (en) | 2020-06-08 | 2021-12-16 | Massachusetts Institute Of Technology | Universal guessing random additive noise decoding (grand) decoder |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6070263A (en) * | 1998-04-20 | 2000-05-30 | Motorola, Inc. | Circuit for use in a Viterbi decoder |
US6161210A (en) * | 1998-04-03 | 2000-12-12 | Lucent Technologies Inc. | List Viterbi algorithms for tailbiting convolutional codes |
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JP2996615B2 (en) * | 1996-01-08 | 2000-01-11 | 松下電器産業株式会社 | Viterbi decoding apparatus and method |
FI102230B1 (en) * | 1997-02-28 | 1998-10-30 | Nokia Telecommunications Oy | Reception procedure and recipients |
KR19980079114A (en) * | 1997-04-30 | 1998-11-25 | 배순훈 | Method and apparatus for decoding trellis code data |
US6327317B1 (en) * | 1999-09-10 | 2001-12-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Combined equalization and decoding techniques |
EP1249112B1 (en) * | 2000-01-17 | 2009-03-25 | Broadcom Corporation | High-speed transmission system for optical channels |
US7933341B2 (en) * | 2000-02-28 | 2011-04-26 | Broadcom Corporation | System and method for high speed communications using digital signal processing |
US7245638B2 (en) * | 2000-07-21 | 2007-07-17 | Broadcom Corporation | Methods and systems for DSP-based receivers |
US7564866B2 (en) * | 2000-07-21 | 2009-07-21 | Broadcom Corporation | Methods and systems for digitally processing optical data signals |
US7127664B2 (en) * | 2000-09-18 | 2006-10-24 | Lucent Technologies Inc. | Reconfigurable architecture for decoding telecommunications signals |
US7251297B2 (en) * | 2000-11-22 | 2007-07-31 | Broadcom Corporation | Method and system to identify and characterize nonlinearities in optical communications channels |
EP1213884B1 (en) * | 2000-12-04 | 2007-03-14 | STMicroelectronics N.V. | Process and device of sucessive value estimations of numerical symbols, in particular for the equalization of a data communication channel of information in mobile telephony |
US20030115061A1 (en) * | 2001-09-11 | 2003-06-19 | Broadcom Corporation | MPSK equalizer |
US7131055B2 (en) * | 2003-02-25 | 2006-10-31 | Intel Corporation | Fast bit-parallel Viterbi decoder add-compare-select circuit |
US7787522B2 (en) * | 2003-04-11 | 2010-08-31 | Telefonaktiebolaget Lm Ericsson (Publ) | Joint multi-code detectors in CDMA communications system |
US7206363B2 (en) | 2003-06-24 | 2007-04-17 | Intersymbol Communications, Inc. | Method and apparatus for delayed recursion decoder |
US7117426B2 (en) * | 2003-12-01 | 2006-10-03 | Mediatek Inc. | Branch metric computation and add-compare-select operation in viterbi decoders |
-
2003
- 2003-06-24 US US10/603,388 patent/US7206363B2/en not_active Expired - Fee Related
-
2004
- 2004-06-24 WO PCT/US2004/020376 patent/WO2005004459A2/en active Application Filing
- 2004-06-24 EP EP04756074A patent/EP1645112A4/en not_active Withdrawn
-
2007
- 2007-04-17 US US11/736,515 patent/US8085883B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6161210A (en) * | 1998-04-03 | 2000-12-12 | Lucent Technologies Inc. | List Viterbi algorithms for tailbiting convolutional codes |
US6070263A (en) * | 1998-04-20 | 2000-05-30 | Motorola, Inc. | Circuit for use in a Viterbi decoder |
Non-Patent Citations (4)
Title |
---|
BOO ET AL: "High-performance VLSI architecture for the Viterbi algorithm", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 45, no. 2, February 1997 (1997-02-01), pages 168 - 176, XP000694663 * |
FORNEY G.D., JR.: "TheViterbi algorithm", PROCEEDINGS OF THE IEEE, vol. 61, no. 3, March 1973 (1973-03-01), pages 268 - 278, XP000573242 * |
LIU: "Algorithm-based low-power and high-performance multimedia signal processing", PROCEEDINGS OF THE IEEE, vol. 86, no. 6, June 1998 (1998-06-01), pages 1155 - 1202, XP000834194 * |
RAGHUPATHY: "A transformation for computational latency reduction in turbo-MAP decoding", PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS,1999, ISCAS'99, vol. 4, 30 May 1999 (1999-05-30) - 2 June 1999 (1999-06-02), pages 402 - 405, XP002176459 * |
Also Published As
Publication number | Publication date |
---|---|
EP1645112A4 (en) | 2007-04-25 |
US20070274418A1 (en) | 2007-11-29 |
US8085883B2 (en) | 2011-12-27 |
US7206363B2 (en) | 2007-04-17 |
EP1645112A2 (en) | 2006-04-12 |
WO2005004459A2 (en) | 2005-01-13 |
US20040264555A1 (en) | 2004-12-30 |
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