WO2005006406A3 - Methods of incorporating germanium within cmos process - Google Patents
Methods of incorporating germanium within cmos process Download PDFInfo
- Publication number
- WO2005006406A3 WO2005006406A3 PCT/US2004/007126 US2004007126W WO2005006406A3 WO 2005006406 A3 WO2005006406 A3 WO 2005006406A3 US 2004007126 W US2004007126 W US 2004007126W WO 2005006406 A3 WO2005006406 A3 WO 2005006406A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cmos process
- methods
- incorporating
- deposition
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/958—Passivation layer
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04718583.0A EP1631980B1 (en) | 2003-06-10 | 2004-03-08 | Methods of incorporating germanium within cmos process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/458,165 | 2003-06-10 | ||
US10/458,165 US6887773B2 (en) | 2002-06-19 | 2003-06-10 | Methods of incorporating germanium within CMOS process |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005006406A2 WO2005006406A2 (en) | 2005-01-20 |
WO2005006406A3 true WO2005006406A3 (en) | 2005-06-16 |
Family
ID=34061872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/007126 WO2005006406A2 (en) | 2003-06-10 | 2004-03-08 | Methods of incorporating germanium within cmos process |
Country Status (3)
Country | Link |
---|---|
US (1) | US6887773B2 (en) |
EP (1) | EP1631980B1 (en) |
WO (1) | WO2005006406A2 (en) |
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US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
JP5416212B2 (en) | 2008-09-19 | 2014-02-12 | 台湾積體電路製造股▲ふん▼有限公司 | Device formation by epitaxial layer growth |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
CN102379046B (en) | 2009-04-02 | 2015-06-17 | 台湾积体电路制造股份有限公司 | Devices formed from a non-polar plane of a crystalline material and method of making the same |
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US20120025195A1 (en) * | 2010-07-28 | 2012-02-02 | Massachusetts Institute Of Technology | Confined Lateral Growth of Crystalline Material |
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US9127345B2 (en) | 2012-03-06 | 2015-09-08 | Asm America, Inc. | Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent |
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FR3007589B1 (en) * | 2013-06-24 | 2015-07-24 | St Microelectronics Crolles 2 | PHOTONIC INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE |
US9218963B2 (en) | 2013-12-19 | 2015-12-22 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US10571631B2 (en) | 2015-01-05 | 2020-02-25 | The Research Foundation For The State University Of New York | Integrated photonics including waveguiding material |
US9874693B2 (en) | 2015-06-10 | 2018-01-23 | The Research Foundation For The State University Of New York | Method and structure for integrating photonics with CMOs |
US10976491B2 (en) | 2016-11-23 | 2021-04-13 | The Research Foundation For The State University Of New York | Photonics interposer optoelectronics |
US10698156B2 (en) | 2017-04-27 | 2020-06-30 | The Research Foundation For The State University Of New York | Wafer scale bonded active photonics interposer |
WO2019195441A1 (en) | 2018-04-04 | 2019-10-10 | The Research Foundation For The State University Of New York | Heterogeneous structure on an integrated photonics platform |
US10816724B2 (en) | 2018-04-05 | 2020-10-27 | The Research Foundation For The State University Of New York | Fabricating photonics structure light signal transmission regions |
US11550099B2 (en) | 2018-11-21 | 2023-01-10 | The Research Foundation For The State University Of New York | Photonics optoelectrical system |
TWI829761B (en) | 2018-11-21 | 2024-01-21 | 紐約州立大學研究基金會 | Photonics structure with integrated laser |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5861059A (en) * | 1995-08-23 | 1999-01-19 | Nec Corporation | Method for selective growth of silicon epitaxial film |
US6271144B1 (en) * | 1997-06-25 | 2001-08-07 | France Telecom | Process for etching a polycrystalline Si(1-x)Ge(x) layer or a stack of polycrystalline Si(1-x)Ge(x) layer and of a polycrystalline Si layer, and its application to microelectronics |
Family Cites Families (6)
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---|---|---|---|---|
JPH04162431A (en) | 1990-10-24 | 1992-06-05 | Fujitsu Ltd | Manufacture of semiconductor device |
FR2749973B1 (en) * | 1996-06-13 | 1998-09-25 | France Telecom | PROCESS FOR ETCHING THE GRID IN MOS TECHNOLOGY USING A SION-BASED HARD MASK |
EP1192646B1 (en) * | 1999-06-25 | 2008-08-13 | Massachusetts Institute Of Technology | Cyclic thermal anneal for dislocation reduction |
FR2812764B1 (en) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | METHOD FOR MANUFACTURING SUBSTRATE OF SUBSTRATE-SELF-INSULATION OR SUBSTRATE-ON-VACUUM AND DEVICE OBTAINED |
EP1328975B1 (en) * | 2000-10-19 | 2011-04-27 | Quantum Semiconductor, LLC | Method of fabricating heterojunction photodiodes integrated with cmos |
US6887773B2 (en) * | 2002-06-19 | 2005-05-03 | Luxtera, Inc. | Methods of incorporating germanium within CMOS process |
-
2003
- 2003-06-10 US US10/458,165 patent/US6887773B2/en not_active Expired - Lifetime
-
2004
- 2004-03-08 EP EP04718583.0A patent/EP1631980B1/en not_active Expired - Lifetime
- 2004-03-08 WO PCT/US2004/007126 patent/WO2005006406A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5861059A (en) * | 1995-08-23 | 1999-01-19 | Nec Corporation | Method for selective growth of silicon epitaxial film |
US6271144B1 (en) * | 1997-06-25 | 2001-08-07 | France Telecom | Process for etching a polycrystalline Si(1-x)Ge(x) layer or a stack of polycrystalline Si(1-x)Ge(x) layer and of a polycrystalline Si layer, and its application to microelectronics |
Also Published As
Publication number | Publication date |
---|---|
WO2005006406A2 (en) | 2005-01-20 |
EP1631980B1 (en) | 2018-08-15 |
US6887773B2 (en) | 2005-05-03 |
US20040092104A1 (en) | 2004-05-13 |
EP1631980A2 (en) | 2006-03-08 |
EP1631980A4 (en) | 2008-10-01 |
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