WO2005006406A3 - Methods of incorporating germanium within cmos process - Google Patents

Methods of incorporating germanium within cmos process Download PDF

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Publication number
WO2005006406A3
WO2005006406A3 PCT/US2004/007126 US2004007126W WO2005006406A3 WO 2005006406 A3 WO2005006406 A3 WO 2005006406A3 US 2004007126 W US2004007126 W US 2004007126W WO 2005006406 A3 WO2005006406 A3 WO 2005006406A3
Authority
WO
WIPO (PCT)
Prior art keywords
cmos process
methods
incorporating
deposition
layer
Prior art date
Application number
PCT/US2004/007126
Other languages
French (fr)
Other versions
WO2005006406A2 (en
Inventor
Iii Lawrence C Gunn
Giovanni Capellini
Maxime J Rattier
Thierry J Pinguet
Original Assignee
Luxtera Inc
Iii Lawrence C Gunn
Giovanni Capellini
Maxime J Rattier
Thierry J Pinguet
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Luxtera Inc, Iii Lawrence C Gunn, Giovanni Capellini, Maxime J Rattier, Thierry J Pinguet filed Critical Luxtera Inc
Priority to EP04718583.0A priority Critical patent/EP1631980B1/en
Publication of WO2005006406A2 publication Critical patent/WO2005006406A2/en
Publication of WO2005006406A3 publication Critical patent/WO2005006406A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/958Passivation layer

Abstract

Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.
PCT/US2004/007126 2003-06-10 2004-03-08 Methods of incorporating germanium within cmos process WO2005006406A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04718583.0A EP1631980B1 (en) 2003-06-10 2004-03-08 Methods of incorporating germanium within cmos process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/458,165 2003-06-10
US10/458,165 US6887773B2 (en) 2002-06-19 2003-06-10 Methods of incorporating germanium within CMOS process

Publications (2)

Publication Number Publication Date
WO2005006406A2 WO2005006406A2 (en) 2005-01-20
WO2005006406A3 true WO2005006406A3 (en) 2005-06-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/007126 WO2005006406A2 (en) 2003-06-10 2004-03-08 Methods of incorporating germanium within cmos process

Country Status (3)

Country Link
US (1) US6887773B2 (en)
EP (1) EP1631980B1 (en)
WO (1) WO2005006406A2 (en)

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Also Published As

Publication number Publication date
WO2005006406A2 (en) 2005-01-20
EP1631980B1 (en) 2018-08-15
US6887773B2 (en) 2005-05-03
US20040092104A1 (en) 2004-05-13
EP1631980A2 (en) 2006-03-08
EP1631980A4 (en) 2008-10-01

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