WO2005008729A3 - Method and apparatus for scrambling cell content in an integrated circuit - Google Patents

Method and apparatus for scrambling cell content in an integrated circuit Download PDF

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Publication number
WO2005008729A3
WO2005008729A3 PCT/US2004/022146 US2004022146W WO2005008729A3 WO 2005008729 A3 WO2005008729 A3 WO 2005008729A3 US 2004022146 W US2004022146 W US 2004022146W WO 2005008729 A3 WO2005008729 A3 WO 2005008729A3
Authority
WO
WIPO (PCT)
Prior art keywords
scan chain
register
transmitted
configuration register
data
Prior art date
Application number
PCT/US2004/022146
Other languages
French (fr)
Other versions
WO2005008729A2 (en
Inventor
Alain Vergnes
Original Assignee
Atmel Corp
Alain Vergnes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0308405A external-priority patent/FR2857535A1/en
Application filed by Atmel Corp, Alain Vergnes filed Critical Atmel Corp
Priority to EP04777926A priority Critical patent/EP1652217A4/en
Publication of WO2005008729A2 publication Critical patent/WO2005008729A2/en
Publication of WO2005008729A3 publication Critical patent/WO2005008729A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Abstract

Address sub-decoder (200) receives peripheral select (114), read/write signal (117), and address bus (110). Address sub-decoder (200) is connected to configuration register (202) by enable write line (206). Configuration register (202) is connected to processing logic by descrambling unit (310). Scrambling unit (300) is coupled to data bus (116) and configuration register (202). Scrambling unit (300) is configured to receive data, or scrambling unit input, from data bus (116) and to scrambled data is transmitted to configuration register (202). If normal operations are halted and the register content read out by scan chain system (126), only scrambled data will be transmitted through scan register output (214) and scan chain output (132), protecting register content. Clock (118), processing logic (204), scan chain control (128) and scan chain input (130) are transmitted to peripheral (108) along scan chain (134).
PCT/US2004/022146 2003-07-09 2004-07-08 Method and apparatus for scrambling cell content in an integrated circuit WO2005008729A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04777926A EP1652217A4 (en) 2003-07-09 2004-07-08 Method and apparatus for scrambling cell content in an integrated circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0308405A FR2857535A1 (en) 2003-07-09 2003-07-09 Sequential cell data scrambling system for e.g. microcontroller, has scrambling unit receiving input from data bus to produce output transmitted to cell, and descrambling unit producing output identical to input of scrambling unit
FR0308405 2003-08-09
US10/861,683 US20050033961A1 (en) 2003-07-09 2004-06-04 Method and apparatus for scrambling cell content in an integrated circuit
US10/861,683 2004-06-04

Publications (2)

Publication Number Publication Date
WO2005008729A2 WO2005008729A2 (en) 2005-01-27
WO2005008729A3 true WO2005008729A3 (en) 2007-03-15

Family

ID=34081982

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/022146 WO2005008729A2 (en) 2003-07-09 2004-07-08 Method and apparatus for scrambling cell content in an integrated circuit

Country Status (2)

Country Link
EP (1) EP1652217A4 (en)
WO (1) WO2005008729A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442628A (en) * 1993-11-15 1995-08-15 Motorola, Inc. Local area network data processing system containing a quad elastic buffer and layer management (ELM) integrated circuit and method of switching
US5745479A (en) * 1995-02-24 1998-04-28 3Com Corporation Error detection in a wireless LAN environment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4465901A (en) * 1979-06-04 1984-08-14 Best Robert M Crypto microprocessor that executes enciphered programs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442628A (en) * 1993-11-15 1995-08-15 Motorola, Inc. Local area network data processing system containing a quad elastic buffer and layer management (ELM) integrated circuit and method of switching
US5745479A (en) * 1995-02-24 1998-04-28 3Com Corporation Error detection in a wireless LAN environment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1652217A4 *

Also Published As

Publication number Publication date
EP1652217A4 (en) 2009-05-13
WO2005008729A2 (en) 2005-01-27
EP1652217A2 (en) 2006-05-03

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