WO2005013479A1

WO2005013479A1 - Amplifier circuit

Info

Publication number: WO2005013479A1
Application number: PCT/IB2004/051326
Authority: WO
Inventors: Godefridus J. G. M. Geelen
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-08-04
Filing date: 2004-07-29
Publication date: 2005-02-10
Also published as: TW200518449A

Abstract

An amplifier circuit for use in an analog-to-digital converter, the circuit comprising a track-and-hold stage (11) having an input (Vin) and an output, the output being connected to an input of one or more amplifiers (12, 14) the circuit being characterized in that the output of at least one of said one or more amplifiers (12, 14) is provided with switch means (34) configured to disable said at least one amplifier (12, 14) during a tracking mode of said track-and-hold stage (11), and to enable said at least one amplifier (12, 14) during a hold mode of said track-and-hold stage (11).

Description

Amplifier circuit

This invention relates to an amplifier circuit and, more particularly, but not exclusively to a chain of cascaded amplifier circuit for use in an analog-to-digital converter or the like. High speed Nyquist analog-to-digital converters (ADCs) play a decise role in the overall performance of many imaging, video and digital communications systems, and have been successfully developed using a number of different architectures. For example, US patent number 5,798,747 describes sample-and-hold amplifier circuit for use in an analog-to-digital converter, wherein the circuit includes an operational amplifier, the output of which is disconnected from a hold capacitor during both the sampling and hold modes of the circuit. We have now devised an improved arrangement. In accordance with the present invention, there is provided an amplifier circuit comprising a track-and-hold stage having an input and an output, the output being connected to an input of one or more amplifiers; the circuit being characterized in that the output of at least one of said one or more amplifiers is provided with switch means configured to disable said at least one amplifier during a tracking mode of said track-and-hold stage, and to enable said at least one amplifier during a hold mode of said track-and-hold stage. The present invention also extends to an analog-to-digital converter comprising a circuit as defined above, wherein a plurality of cascaded amplifiers is provided, the output of one or more of which is provided with switch means for disabling a respective amplifier during the tracking mode and enabling said respective amplifier during the hold mode. Preferably, the outputs of the amplifiers are applied to one or more folding stages. Beneficially, the output signal from the folding stages is applied to a quantizer prior to being digitally coded. Preferably, the amplifiers comprise a differential pair with a resistive load. Beneficially, the switch means, during the tracking mode operates to short circuit the resistive load and thereby disable the respective amplifier. The switch means preferably comprises a MOS transistor. Thus, in order to support an increased sampling speed, the present invention provides a switch (or the like) at the output of the or each amplifier. The switch is configured such that, during track mode of the track and hold circuit, the switch is closed such that the amplifier is disabled, whereas during hold mode, the switch is opened and the amplifier is enabled. These and other aspects of the present invention will be apparent from and elucidated with reference to the embodiment described hereinafter.

Fig. 1 is a schematic block diagram illustrating the configuration of a typical analog-to-digital converter in accordance with the prior art; Fig. 2 is a schematic diagram illustrating the architecture of a folding analog- to-digital converter; Fig. 3 a is a schematic diagram illustrating an amplifier according to the prior art; Fig. 3 b is a schematic diagram illustrating an amplifier according to an exemplary embodiment of the present invention; Fig. 4 is a graphic representation of the output signals from 32 folding amplifiers according to the prior art (simulated sampling frequency Fs = 100 MS/s); and Fig. 5 is a graphical representation of the output signals from 32 folding amplifiers according to an exemplary embodiment of the present invention (simulated sampling frequency Fs = 100 MS/s).

As stated above, high speed Nyquist analog-to-digital converters (ADC's) play a decisive role in the overall performance of many imaging, video and digital communications systems, and have been successfully developed using a number of different architectures. The folding architecture is one approach widely used to avoid the complexity of earlier flash ADC's. It has the speed advantage of the flash ADC, while the number of comparators is greatly reduced with analog preprocessing. Cascaded folding further reduces the number of comparators. Fig. 1 illustrates the configuration of a typical ADC with folding circuit. The folded signal is generated directly from the analog signal; in order words, the digital output from the coarse quantizer is not necessary in the folded signal generation. The LSB data can be obtained in parallel with the MSB data in the folding architecture, so the conversion speed of the folding ADC is higher than that of the traditional two-step approach. Referring to Fig. 2 of the drawings, a typical architecture of a folding ADC is illustrated, and comprises a reference ladder 10, a track-and-hold circuit 11, the output of which is connected to a first amplifier stage 12. The architecture further comprises a second amplifier stage 14, a first folder stage 16, a second folder stage 18, a fine quantizer 20, and a digital coding stage 22. A coarse quantizer 24 is provided between the output of the second amplifier stage and the digital coding stage 22. A resistive ladder 10 between two clean reference voltages generates 18 tap voltages. A first array 12 of differential amplifiers measures the difference between the (differential) input signal, coming from the track-and-hold circuit 11, and the (differential) tap voltages resulting in 18 output signals who's zero crossings are determined by the input signal. This array 12 is followed by a second array 14 of differential amplifiers with resistive interpolation at the output resulting in 36 output signals. A first 16 and second 18 folding stage, each with a fold factor of 3, convert these 36 signals into 4 signals with a foldfactor of 9. Resistive interpolation with a factor of 8 results in 32 folded signals which are fed to the fine quantizer JO consisting of 32 comparators. The output of the comparators form a thermometer code from which the 5 LSB's are determined in the digital encoder 22. In the coarse quantizer 24, output signals are generated that indicate in which fold the input signal was. From these signals the 3 MSB's are determined in the encoder 22. Resistive averaging is applied at the output of the amplifiers to improve INL/DNL. Dummy amplifiers are added at the top and the bottom of the amplifier arrays 12, 14 so that averaging works well over the whole signal range. A Track-and-Hold (T/H) 11 stage is provided in the front for high signal bandwidth. In order to achieve high sample rates it only consists of a switch, a hold capacitor and a source follower to drive the first array 12 of amplifiers. The switch is an Nmos transistor clocked with a bootstrapped clocksignal to make charge injection and Ron independent of the input signal. All amplifiers consist of a differential pair with resistive load as shown in Fig. 3 a. Each stage amplifies the signal to reduce the influence of the offset from the following stages. Thus, the signal path after the T/H 11 consists of a chain of amplifiers in cascade, and it will be apparent that the speed of such a converter is determined by the settling behavior of such a chain of amplifiers. Fig. 4 shows typical input signals of the fine quantizer 20. This quantizer 20 has to decide which signals are positive and which are negative. The most critical signals are the signals that settle to a value close to zero because they have to settle with 1 LSB in order to determine the correct zero crossings. It is this accurate settling with a large input step that limits the speed to about 150 Msample/s for known 8b folding ADCs. Thus, in accordance with an exemplary embodiment of the invention, in order to avoid this critical speed bottleneck, a switch 34 is provided at the output of each amplifier as shown in Fig. 3b. During track mode of the T/H stage 11, this switch 34 is closed and forces all outputs to zero, i.e. it disables the amplifier. In hold mode, the switch 34 is opened and the output signals now settle as shown in Fig. 5. Now the critical signals only have to make a step of about 1 LSB, and it is unnecessary to wait until all signals are settled. From this plot it can be concluded that the maximum sampling frequency and conversion speed, can be much higher compared to Fig. 4. This increase in sample frequency and conversion speed has no current or area penalty. Thus, the exemplary embodiment of the invention as described above, applies to a chain of cascaded amplifiers that have to settle to a certain voltage. As an example, an 8b folding analog-to-digital converter (ADC) is used. Sample rates of up to 150Msample/s have been reported using known ADC configurations, whereas the ADC discussed herein can be shown to reach a sample rate of 500MSample/s and an effective resolution bandwidth (ERBW) of 400MHz. This result is obtained with a folding/interpolating/averaging architecture with a Track-and-Hold (T/H) in front and present switches at the output of the gain/fold stages. The arrangement described herein is designed in a standard 0J5μm single-poly four-metal 3JV digital CMOS process. It should be noted that the above-mentioned embodiment illustrates rather than limits the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An amplifier circuit comprising a track-and-hold stage (11) having an input (Vin) and an output, the output being connected to an input of one or more amplifiers (12, 14); the circuit being characterized in that the output of at least one of said one or more amplifiers (12, 14) is provided with switch means (34) configured to disable said at least one amplifier (12,14) during a tracking mode of said track-and-hold stage (11), and to enable said at least^'one amplifier (12,14) during a hold mode of said track-and-hold stage (11).

2. An analog-to-digital converter comprising a circuit according to claim 1, wherein a plurality of cascaded amplifiers (12,14) is provided, the output of one or more of which is provided with switch means (34) for disabling a respective amplifier (12, 14) during the tracking mode and enabling said respective amplifier (12,14) during the hold mode.

3. An analog-to-digital converter according to claim 1, wherein the outputs of said amplifiers (12,14) are applied to one or more folding stages (16,18).

4. An analog-to-digital converter according to claim 3, wherein the output signal from the folding stages (16,18) is applied to a quantizer (20) prior to being digitally coded.

5. An analog-to -digital converter according to any one of claims 2 to 4, wherein the amplifiers (12,14) comprise a differential pair (30) with a resistive load (32).

6. An analog-to -digital converter according to claim 5, wherein the switch means (34), during said tracking mode operates to short circuit the resistive load (32) and thereby disable the respective amplifier (12,14).

7. An analog-to -digital converter according to any one of claims 2 to 6, wherein said switch means (34) comprises a MOS transistor.

8. An integrated circuit including an analog-to-digital converter according to any of the claims 2-7.