WO2005020088A3 - Decoupled store address and data in a multiprocessor system - Google Patents

Decoupled store address and data in a multiprocessor system Download PDF

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Publication number
WO2005020088A3
WO2005020088A3 PCT/US2004/026814 US2004026814W WO2005020088A3 WO 2005020088 A3 WO2005020088 A3 WO 2005020088A3 US 2004026814 W US2004026814 W US 2004026814W WO 2005020088 A3 WO2005020088 A3 WO 2005020088A3
Authority
WO
WIPO (PCT)
Prior art keywords
write request
shared memory
request address
write
data
Prior art date
Application number
PCT/US2004/026814
Other languages
French (fr)
Other versions
WO2005020088A2 (en
Inventor
Steven L Scott
Gregory J Faanes
Original Assignee
Cray Inc
Steven L Scott
Gregory J Faanes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/643,586 external-priority patent/US7334110B1/en
Priority claimed from US10/643,585 external-priority patent/US7543133B1/en
Priority claimed from US10/643,754 external-priority patent/US8307194B1/en
Priority claimed from US10/643,741 external-priority patent/US7437521B1/en
Priority claimed from US10/643,742 external-priority patent/US7743223B2/en
Priority claimed from US10/643,758 external-priority patent/US7577816B2/en
Application filed by Cray Inc, Steven L Scott, Gregory J Faanes filed Critical Cray Inc
Priority to EP04781494A priority Critical patent/EP1665054A2/en
Publication of WO2005020088A2 publication Critical patent/WO2005020088A2/en
Publication of WO2005020088A3 publication Critical patent/WO2005020088A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Abstract

In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a memory location in shared memory. A write request is issued to the shared memory, wherein the write request includes the write request address. The write request address is noted in the shared memory and addresses in subsequent load and store requests are compared in share memory to the write request address. The write data is transferred to the shared memory and matched, within the shared memory, to the write request address. The write data is then stored into the shared memory as a function of the write request address.
PCT/US2004/026814 2003-08-18 2004-08-18 Decoupled store address and data in a multiprocessor system WO2005020088A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04781494A EP1665054A2 (en) 2003-08-18 2004-08-18 Decoupled store address and data in a multiprocessor system

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US10/643,586 US7334110B1 (en) 2003-08-18 2003-08-18 Decoupled scalar/vector computer architecture system and method
US10/643,741 2003-08-18
US10/643,585 US7543133B1 (en) 2003-08-18 2003-08-18 Latency tolerant distributed shared memory multiprocessor computer
US10/643,754 US8307194B1 (en) 2003-08-18 2003-08-18 Relaxed memory consistency model
US10/643,741 US7437521B1 (en) 2003-08-18 2003-08-18 Multistream processing memory-and barrier-synchronization method and apparatus
US10/643,758 2003-08-18
US10/643,588 US7529906B2 (en) 2003-08-18 2003-08-18 Sharing memory within an application using scalable hardware resources
US10/643,586 2003-08-18
US10/643,585 2003-08-18
US10/643,742 US7743223B2 (en) 2003-08-18 2003-08-18 Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US10/643,754 2003-08-18
US10/643,758 US7577816B2 (en) 2003-08-18 2003-08-18 Remote translation mechanism for a multinode system
US10/643,742 2003-08-18

Publications (2)

Publication Number Publication Date
WO2005020088A2 WO2005020088A2 (en) 2005-03-03
WO2005020088A3 true WO2005020088A3 (en) 2005-05-12

Family

ID=47921259

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/026814 WO2005020088A2 (en) 2003-08-18 2004-08-18 Decoupled store address and data in a multiprocessor system

Country Status (3)

Country Link
US (1) US7529906B2 (en)
EP (2) EP1665054A2 (en)
WO (1) WO2005020088A2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7743223B2 (en) 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7421565B1 (en) * 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US20050273571A1 (en) * 2004-06-02 2005-12-08 Lyon Thomas L Distributed virtual multiprocessor
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US7363463B2 (en) * 2005-05-13 2008-04-22 Microsoft Corporation Method and system for caching address translations from multiple address spaces in virtual machines
US8909946B2 (en) 2005-11-15 2014-12-09 Microsoft Corporation Efficient power management of a system with virtual machines
TWI438698B (en) 2005-12-19 2014-05-21 Internat Frontier Tech Lab Inc Can identify the authenticity of the card
US8615643B2 (en) 2006-12-05 2013-12-24 Microsoft Corporation Operational efficiency of virtual TLBs
US8694712B2 (en) * 2006-12-05 2014-04-08 Microsoft Corporation Reduction of operational costs of virtual TLBs
US7788464B2 (en) * 2006-12-22 2010-08-31 Microsoft Corporation Scalability of virtual TLBs for multi-processor virtual machines
US20080270739A1 (en) * 2007-04-27 2008-10-30 Hamilton Eric W Management of copy-on-write fault
DE102009060668A1 (en) * 2009-12-28 2011-06-30 Fresenius Medical Care Deutschland GmbH, 61352 Apparatus and method for monitoring extracorporeal blood treatment
KR20150136075A (en) * 2013-03-28 2015-12-04 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. Shared memory system
US10884774B2 (en) 2014-06-16 2021-01-05 Hewlett Packard Enterprise Development Lp Virtual node deployments of cluster-based applications modified to exchange reference to file systems

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5446915A (en) 1993-05-25 1995-08-29 Intel Corporation Parallel processing system virtual connection method and apparatus with protection and flow control
JP2625385B2 (en) 1994-06-30 1997-07-02 日本電気株式会社 Multiprocessor system
US5845331A (en) 1994-09-28 1998-12-01 Massachusetts Institute Of Technology Memory system including guarded pointers
US6101590A (en) * 1995-10-10 2000-08-08 Micro Unity Systems Engineering, Inc. Virtual memory system with local and global virtual address translation
US5860146A (en) 1996-06-25 1999-01-12 Sun Microsystems, Inc. Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces
US5897664A (en) 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
US6105113A (en) * 1997-08-21 2000-08-15 Silicon Graphics, Inc. System and method for maintaining translation look-aside buffer (TLB) consistency
US6490671B1 (en) * 1999-05-28 2002-12-03 Oracle Corporation System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system
US7356026B2 (en) 2000-12-14 2008-04-08 Silicon Graphics, Inc. Node translation and protection in a clustered multiprocessor system
US6925547B2 (en) 2000-12-14 2005-08-02 Silicon Graphics, Inc. Remote address translation in a multiprocessor system
US6684305B1 (en) * 2001-04-24 2004-01-27 Advanced Micro Devices, Inc. Multiprocessor system implementing virtual memory using a shared memory, and a page replacement method for maintaining paged memory coherence
US6922766B2 (en) * 2002-09-04 2005-07-26 Cray Inc. Remote translation mechanism for a multi-node system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ABTS D ET AL: "o many states, so little time: verifying memory coherehnce in the Cray X1", PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM, 2003. PROCEEDINGS. INTERNATIONAL APRIL 22-26, 2003, PISCATAWAY, NJ, USA,IEEE, 22 April 2003 (2003-04-22), pages 11 - 20, XP010645295, ISBN: 0-7695-1926-1 *
HENNESSY J L, PATTERSON D A: "Computer Architecture. A quantative approach", June 2002, MORGAN KAUFMANN, XP002318184 *

Also Published As

Publication number Publication date
US7529906B2 (en) 2009-05-05
EP1665054A2 (en) 2006-06-07
WO2005020088A2 (en) 2005-03-03
US20050044339A1 (en) 2005-02-24
EP2284711A1 (en) 2011-02-16

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