WO2005024842B1 - Eeprom emulation in flash memory - Google Patents

Eeprom emulation in flash memory

Info

Publication number
WO2005024842B1
WO2005024842B1 PCT/US2004/029202 US2004029202W WO2005024842B1 WO 2005024842 B1 WO2005024842 B1 WO 2005024842B1 US 2004029202 W US2004029202 W US 2004029202W WO 2005024842 B1 WO2005024842 B1 WO 2005024842B1
Authority
WO
WIPO (PCT)
Prior art keywords
pointer
bit
data
flash memory
sets
Prior art date
Application number
PCT/US2004/029202
Other languages
French (fr)
Other versions
WO2005024842A1 (en
Inventor
Venkatapathi R Nallapa
Original Assignee
Ballard Power Systems
Venkatapathi R Nallapa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ballard Power Systems, Venkatapathi R Nallapa filed Critical Ballard Power Systems
Publication of WO2005024842A1 publication Critical patent/WO2005024842A1/en
Publication of WO2005024842B1 publication Critical patent/WO2005024842B1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Abstract

An efficient emulation of EEPROM employing flash memory employs a fixed location for an address pointer in flash memory and such that an erase operation is required only once every nth update where n is the number of bits at the fixed location, thus avoiding the need to erase the sector on every update and avoiding delays associated with linked lists for determining the address of the most up-to-date information. Use of bit shifting provides fast determination of the desired address.

Claims

AMENDED CLAIMS [received by the International Bureau on 10 March 2005 (10.03.05); claims 1-3, 8-11, 13, 17 are amended; claims 4-7, 12, 14-16, 18-21 are unchanged; (5 pages)]
1. A method of storing data, the method comprising: storing a first set of data to a first set of contiguous memory locations of a flash memory; setting a single first bit of a pointer at a fixed set of memory locations of the flash memory, the first bit indicating an address of the first set of contiguous memory locations of the flash memory; storing a second set of data to a second set of contiguous memory locations of the flash memory; setting at least a single second bit of the pointer, the second bit being a next successive bit in the pointer to the first bit, the second bit indicating an address of the second set of contiguous memory locations of the flash memory; and erasing at least the pointer after a last bit in the pointer has been set.
2. The method of claim 1 wherein a position in the pointer of the first bit indicates an offset to the first set of contiguous memory locations and wherein a position in the pointer of the second bit indicates an offset to the second set of contiguous memory locations.
3. The method of claim 1 wherein setting a single first bit of a pointer comprises setting a least significant bit of the pointer and wherein setting a single second bit of the pointer comprises setting a next successive bit in the pointer with respect to the least significant bit in the pointer.
4. The method of claim 1 , further comprising: storing a number of additional sets of data to respective ones of a number of additional sets of contiguous memory locations of the flash memory; and setting at least a number of additional bits of the pointer, each of the bits indicating an address of a respective one of the additional sets of contiguous memory locations of the flash memory;
5. The method of claim 4 wherein the pointer is a word and the bits in the pointer are set consecutively from a least significant bit to a most significant bit.
6. The method of claim 1 wherein erasing at least the pointer after a last bit in the pointer has been set comprises erasing a sector of the flash memory, the sector containing the pointer, the first set of contiguous memory locations and the second set of contiguous memory locations.
7. The method of claim 1 further comprising: determining a most recent one of the sets of data upon a power up event, and retrieving the most recent one of the sets of data upon the power up event.
8. The method of claim 7, further comprising: storing successive sets of data to respective ones of the locations of the flash memory; for each of the sets of data, setting one respective bit of the pointer stored in the flash memory before storing a next one of the sets of data, the one bit indicative of the location in the flash memory at which the respective set of data is stored; and after the last bit in the pointer has been set, erasing a sector of the flash memory containing the pointer and the stored sets of data.
9. The method of claim 8 wherein setting one respective bit of the pointer stored in the flash memory before storing a next one of the sets of data comprises setting a single bit whose position in the pointer indicates a defined offset to the location of the respective set of data in the flash memory.
10. The method of claim 8 wherein the pointer is a word and determining a most recent one of the sets of data upon a power up event comprises: bit shifting the pointer in an order from the last bit in the pointer to the first bit in the pointer.
11. The method of claim 8 wherein setting one respective bit of the pointer stored in the flash memory before storing a next one of the. sets of data comprises for each of a first one of the sets of data through an nth one of the sets of data, setting a single corresponding bit from a first bit to an nth bit whose position in the pointer indicates a defined offset to the location of the respective set of data in the flash memory.
12. The method of claim 8 wherein storing successive sets of data to respective ones of the locations of the flash memory comprises storing a set of data stored in a random access memory upon each of a number of successive power down events.
13. The method of claim 1 , further comprising: determining a most recent one of the sets of data upon an occurrence of a power up event by bit shifting the pointer in an order from the last bit in the pointer to the first bit in the pointer.
14. A processor-readable media storing instructions for causing a processor to store data according to any of claims 1 through 16.
15. An apparatus to emulate an electrically erasable programmable read only memory using a flash memory, the apparatus comprising: a flash memory; means for storing successive sets of data to respective ones of a number of locations of contiguous memory of the flash memory; means for setting at least one respective bit of a number of bits of a pointer stored in the flash memory for each of the sets of data, before storing a next one of the sets of data, the at least one bit indicative of the location in the flash memory at which the respective set of data is stored; and means for erasing a sector of the flash memory containing the pointer and the stored sets of data after a last bit in the pointer has been set.
16. The apparatus of claim 15 wherein the means comprises a processor configured to store successive sets of data to respective ones of a number of locations of contiguous memory of the flash memory; to set at least one respective bit of a number of bits of a pointer stored in the flash memory for each of the sets of data, before storing a next one of the sets of data, the at least one bit indicative of the location in the flash memory at which the respective set of data is stored; and to erase a sector of the flash memory containing the pointer and the stored sets of data after a last bit in the pointer has been set.
17. The apparatus of claim 16 wherein the processor is further configured to determine a most recent one of the sets of data upon an occurrence of a power up event by bit shifting the pointer in an order from the last bit in the pointer to the first bit in the pointer.
18. The apparatus of claim 15 wherein the flash memory stores a data structure, the data structure comprising: a plurality of sets of contiguous memory; and a pointer at a fixed location, the pointer comprising a number of bits, each bit indicative of a defined location of a respective one of the sets of contiguous memory.
19. The apparatus of claim 18 wherein the pointer comprises sixteen bits, each bit identifying an offset to a respective one of the sets of contiguous memory.
20. The apparatus of claim 19 wherein the offset is a multiple of a position of the bit in the pointer and a defined offset value.
21. The apparatus of claim 18 wherein a single sector of the flash memory contains both the plurality of sets of contiguous memory and the pointer.
7 e
PCT/US2004/029202 2003-09-09 2004-09-08 Eeprom emulation in flash memory WO2005024842A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/658,124 2003-09-09
US10/658,124 US7058755B2 (en) 2003-09-09 2003-09-09 EEPROM emulation in flash memory

Publications (2)

Publication Number Publication Date
WO2005024842A1 WO2005024842A1 (en) 2005-03-17
WO2005024842B1 true WO2005024842B1 (en) 2005-05-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/029202 WO2005024842A1 (en) 2003-09-09 2004-09-08 Eeprom emulation in flash memory

Country Status (2)

Country Link
US (1) US7058755B2 (en)
WO (1) WO2005024842A1 (en)

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Also Published As

Publication number Publication date
US20050055496A1 (en) 2005-03-10
US7058755B2 (en) 2006-06-06
WO2005024842A1 (en) 2005-03-17

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