WO2005033949A1

WO2005033949A1 - Semiconductor memory device

Info

Publication number: WO2005033949A1
Application number: PCT/JP2004/014905
Authority: WO
Inventors: Masahiro Nakanishi; Tomoaki Izumi; Tetsushi Kasahara; Kazuaki Tamura; Kiminori Matsuno
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2003-10-03
Filing date: 2004-10-01
Publication date: 2005-04-14

Abstract

In a semiconductor memory device using a nonvolatile memory, such as EEPROM, even in an event that data stored in the nonvolatile memory cannot be correctly read due to a power supply interruption or the like, a recovery program is activated to quickly recover the function as of a memory device. For this purpose, after the activation of the recovery program stored in a ROM, a program (FW2) stored in the EEPROM is transferred to a RAM, and thereafter, a CPU performs a processing based on the program (FW2) transferred to the RAM.

Description

Description Semiconductor memory device Technical field

The present invention relates to a memory device using a non-volatile semiconductor memory, and more specifically, a control program is divided and stored in a mask ROM in the semiconductor memory device and a part of the recordable non-volatile memory. Semiconductor memory device. Background art

As a conventional semiconductor memory device, Japanese Unexamined Patent Publication No. Hei 11-94855 (Reference 1) discloses a read-only memory (hereinafter, referred to as a ROM) including a mask ROM and the like, and an EEPROM, which is a main storage unit of the semiconductor memory device. A technique is disclosed in which a control program is divided and stored in different areas.

FIG. 1 is a block diagram showing a configuration of a conventional semiconductor memory device as described above. This semiconductor memory device is connected to the host system 501. This semiconductor memory device has a controller 502A and an EEPROM 503 as modules. The controller 502A is a module having a host interface 504, a CPU 505, a RAM 506, an EEPROM interface 507, and a ROM 508. The RAM 506 is a memory that can be written and read at any time. The ROM 508 is a read-only mask memory that holds the program FW1. The ROM 508 also holds a main program and a transfer program for transferring the extension program FW2 recorded in the EEPROM 503 to the controller 502A. Extension program FW2 is semi-conductive This is a program added according to the function expansion of the body memory device.

Here, the program FW1 held in the ROM 508 includes a transfer program for transferring the extension program FW2 in the EEPROM 503 to the RAM 506 in addition to the original main program. On the other hand, the EPROM 503 is a module including a programmable ROM that can be electrically recorded and erased, and is connected to the controller 502A via a memory bus. The EEPROM 503 stores general data input from the host system 501, and also stores an extension program FW2 in a partial area 509. When the general data II expansion program FW2 is transferred to the controller 502A, the CPU 505 executes the transfer program for the EEPROM 507.

The operation of the conventional semiconductor memory device configured as described above will be described with reference to FIG. First, when the power of the semiconductor memory device is turned on, the CPU 505 activates a transfer program in the program FW1 stored in the ROM 508. At this time, the extension program FW2 stored in the area 509 of the EEPROM 503 is read and transferred to the RAM 506 via the EEPROM interface 507. Thereafter, the CPU 505 controls the controller 502A by using the main program stored in the ROM 508 and the extension program FW2 transferred to the RAM 506. The controller 502A reads data from the EEPROM 503 via the host interface 504 and the EEPROM interface 507 in response to a data read / write instruction from the host system 501, or reads data from the EEPROM 503. Is written.

Thus, the program as the semiconductor memory device is divided into the program FW1 and the extension program FW2. Then, by retaining the extension program FW2 in the area 509 of the EEPROM 503, the function of the semiconductor memory device can be extended only by rewriting the extension program FW2 in the area 509 (for example, (Purging up) can be executed in a short period of time.

However, in the conventional semiconductor memory device as described above, when an abnormal state of the EE PROM 503, for example, when the data cannot be read correctly at the next start-up due to the influence of power cutoff or the like, the expansion program There was a problem that FW2 could not be transferred correctly to RAM 506.

Here, the phenomenon that the data cannot be read correctly at the next startup due to the influence of the power supply cutoff or the like in the semiconductor memory device will be described with reference to FIG. FIG. 2 is a configuration diagram of a nonvolatile memory array built in the EEPROM 503. Here, a part of the arrangement of the memory cells for storing the data bits, ie, the transistor Tr, is shown in an enlarged manner. A global bit line A (abbreviated as GBL-A in the drawing) is connected to a local bit line (LBL) via a select transistor Tr.A and a select transistor Tr.C. A single bit line (LBL) is connected from the global pit line B (GBL-B) via a selection transistor Tr.B and a selection transistor Tr.D. A large number of memory cells are connected in matrix form to the local bit lines. The memory cell in the bit line direction is selected by the selection transistor Tr, and one memory cell on the bit line is selected by selecting one gate line at the same time. 256 memory cells are connected in parallel per bit line per bit line. Note that a unit of one bit line is called one string. In each memory cell, an assist gate AG-E is connected to the gate of the assist transistor ATr in the odd-numbered column, and an assist gate AG-〇 is connected to the gate of the assist transistor ATr in the even-numbered column.

First, the basic operation of reading data will be described. For reading, a positive potential is applied to the word line, and whether the data value is 0 or 1 is determined based on the presence or absence of a current flowing in the memory cell. When reading the memory cell MA, a positive voltage is applied to each gate of the selection transistor Tr.A and the selection transistor Tr.D, and a positive voltage is applied to the word line A. At this time, the selection transistor Tr.B and the selection transistor The potential of the transistors Tr, C and the unselected word lines is 0 V. Furthermore, a positive voltage is applied to assist gate AG-E, and 0 V is applied to assist gate AG- AG. In this state, the memory cell MA is selected, and the memory cell MB is not selected. In reading data held in a memory cell, an electric potential is applied to a drain of the memory cell, and data in the memory cell is determined based on whether or not a current flows. When reading data from the memory cell MA, as shown in FIG. 2, a potential is applied to the global bit line GBL-B, and the memory cell MA and the selection transistor Tr are passed through the selection transistor Tr.D. Determine whether or not current flows through the path A. This current value depends on the threshold voltage (hereinafter, referred to as Vth) of the memory cell. When data is written, V th becomes high, and when data is erased, V th becomes low.

Next, the cause of erroneous data reading will be described. This occurs when data is not correctly erased due to a power shutdown or the like during data erasure. In other words, to erase data overnight, erase is performed by applying a negative voltage to the read line and lowering Vth of the memory cell. In this case, the operation of lowering Vth to a value of 0 is performed. However, if the erasing operation is aborted due to a power shutdown or the like during this operation, the Vth of the memory cell may become negative. This phenomenon causes the misreading described below.

The erroneous reading will be described. As described above, when reading data from a memory cell, a positive voltage is applied to the gate (word line) of the selected memory cell, and 0 V is applied to the word line of an unselected memory cell. I do. At this time, if V th of the non-selected memory cell becomes 0 V or less (negative value), a current path like the broken line shown in FIG. 2 is generated. This is called an unselected leak. If Vth of the selected memory cell MA is in the write state and no current flows, and if Vth of the non-selected memory cell MC is negative, the current normally flows through the memory cell MA. Since there is no data, it is determined that the data is written. However, since V th of the unselected memory cell MC is negative, current flows, and it is determined that the memory cell is in the erased state. Will be determined.

When such a state exists, all the memory cells on the same string are determined to be in an erased state. In other words, data is not actually erased, but erroneous reading is performed as if already written data has been erased. Due to the phenomenon described above, the expansion program FW2 may not be read correctly from the EEPROM 503 immediately after the startup. Disclosure of the invention

A semiconductor memory device according to the present invention includes a memory module including a nonvolatile memory capable of electrically erasing and recording data, a controller module performing control for reading and writing data in a nonvolatile memory, and a program holding a program. And a read-only ROM to read. The controller module includes a RAM that can be written and read at any time, and a CPU that controls the operation of the controller module based on the ROM and a program stored in the RAM. When the program processed by the CPU includes an extension program in addition to the main program for operating the controller module, the main program is recorded in ROM, and the extension program is stored in a part of the memory module. To record. A restoration program for restoring the abnormal state of the nonvolatile memory and a transfer program for transferring the extension program to the RAM are recorded in the ROM.

With this configuration, even when an abnormal state occurs in the nonvolatile memory for storing data, the recovery program stored in the ROM is first executed when the semiconductor memory device is started, so that the data in the nonvolatile memory can be stored. Can be read correctly. Brief Description of Drawings

FIG. 1 is a block diagram showing a structural example of a conventional semiconductor memory device. FIG. 2 is a configuration diagram of an EEPROM memory array used in a semiconductor memory device.

FIG. 3 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing an execution procedure of the CPU in the controller after the device is started.

FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to Embodiment 2 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment A semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIG. 3 and FIG. FIG. 3 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment. This semiconductor memory device is connected to the host system 501. This semiconductor memory device is configured to include a controller 502B and an EPROM 503. These functional blocks are

—Integrated into the board as a tool.

The controller 502B has a host interface 504, a CPU 505, a RAM 506, an EPROM interface 507, and a ROM 101 in the same module. Therefore, the controller 502B is also called a controller module.

The ROM 101 is a read-only memory and holds the program FW1. The program FW1 includes a main program, a transfer program for transferring the extension program FW2 recorded in the EEPROM 503 to the controller 502B, and a recovery program for the EEPROM 503.

EEPROM 503 is one of the nonvolatile memories. The area 102 of the EEPROM 503 is a partial memory area of the EEPROM, and stores the program F This area stores the extension program FW2 other than Wl. General data input from the host system 501 is recorded in another area of the EE PROM 503. The functions of the other blocks are the same as those of the conventional semiconductor memory device. The configuration of the nonvolatile memory array built in the EEPROM 503 is the same as that shown in FIG.

The operation of the semiconductor memory device according to the present embodiment will be described with reference to FIG. FIG. 4 is a flowchart showing an execution procedure of the CPU 505 immediately after the startup of the semiconductor memory device. When the power is turned on in step S1, the device starts. In the next step S2, the program FW1 in the ROM 101 is read and the controller 502B is started. Then, the process proceeds to step S3 to search for a memory cell in which Vth has become negative due to power-off during erasing or the like, and forcibly set the transistor of the memory cell in which Vth has become negative to a positive potential. By doing so, a leak current can be prevented, and as a result, erroneous reading can be avoided. This process is executed by the recovery program (Step S3) that restores the EEPROM in the program FW1.

Next, the process proceeds to step S4 to check whether the search has been completed for all transistors. If not completed, return to step S3 and repeat this process. When the processing for all the transistors is completed, the process proceeds from step S4 to S5 to read the transfer program stored in ROM 101. That is, the extension program FW2 is transferred from the EEPROM 503 to the RAM 506 via the EEPROM interface 507. Next, in step S6, the process proceeds to a normal processing loop.

Regarding the transfer of the extension program FW2, a dedicated control circuit may be incorporated in the module of the controller 502B or the module including the EEPROM 503, and the control circuit may transfer the extension program FW2. Note that the working RAM of the CPU 505 is built in the CPU 505 itself. As described above, according to the first embodiment, when the device is started, the restoration program stored in the ROM 101 is first read and executed, and then the transfer program is read and executed. FW 2 can be correctly transferred to RAM 506.

(Example 2)

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of the semiconductor memory device according to the second embodiment. In FIG. 5, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description of the functions will be omitted. The difference from the first embodiment is that the ROM section for storing the recovery program in the program FW1 is provided in the memory module including the EEPROM 201. In the second embodiment, the controller 502C is a controller module having a host interface 504, a CPU 505, a RAM 506, an EPROM interface 507, and a ROM 508.

In the EEPROM 201 which is a non-volatile memory, a CPU 203 and a ROM 204 as a control unit are provided in addition to an EE PROM 202 which is a non-volatile memory array. The ROM section 204 stores an EPROM recovery program. Further, an area 205 of the extension program FW2 is provided in the EE PROM section 202. When the device is started, the CPU 505 instructs the CPU 203 to start a recovery program via the EEPROM interface 507, and the CPU 203 based on the recovery program stored in the ROM 20. Perform recovery processing. During that time, the CPU unit 203 outputs a ready signal as a busy state, and stops the processing of the CPU 505. When the recovery program ends, the ready signal is set to the ready state. At this time, the CPU 505 stores the extension program FW2 obtained from the EEP ROM 201 in the RAM 506.

Notify the ready signal to the controller 502C via the memory bus It does not matter. As for the transfer of the extension program FW2, a dedicated control circuit may be built in the controller 502C or the EEPROM 201, and the control circuit may transfer the extension program FW2. The working RAM of the CPU 505 is assumed to be built in the CPU 505 itself.

As described above, according to the second embodiment of the present invention, at the time of startup, the CPU 505 starts processing when the recovery processing by the recovery program stored in the ROM unit 204 is completed, and the expansion program FW2 Transfer to the RAM 506, the operation by the extension program FW2 can be executed.

Industrial potential

The semiconductor memory device of the present invention can be used for purging in addition to recording general data, such as a mobile phone, a portable audio player for recording and reproducing audio signals, a portable PDA, a voice recorder, and an in-vehicle AV device. Anything that can load the program of YON-UP and has an EEPROM can be used. It is especially useful for portable electronic devices that are prone to battery drain and erroneous operation.

Claims

O 2005/033949 10 Claims

1. Memory modules including nonvolatile memory that can electrically erase and record data,

A controller module for performing control for reading and writing data in the nonvolatile memory;

A read-only ROM for holding a program, and a semiconductor memory device comprising:

The controller module includes:

A RAM that can be written and read at any time, and a CPU that controls the operation of the controller module based on the R〇M and the program held in the RAM.

When the program processed by the CPU includes an extension program in addition to the main program for operating the controller module, the main program is recorded in the ROM, and the extension program is stored in the memory module. Record in some areas,

A semiconductor memory device, wherein a restoration program for restoring an abnormal state of the nonvolatile memory and a transfer program for transferring the extension program to the RAM are recorded in the ROM.

2. The semiconductor memory device according to claim 1, wherein the ROM is provided in the controller module.

3. The semiconductor memory device according to claim 1, wherein the ROM is provided in the memory module.

4. A control circuit is provided in the controller module or the memory module, and a transfer operation corresponding to the transfer program is performed by the control circuit. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is executed.

5. The memory module is

A nonvolatile memory comprising a nonvolatile memory array, and a control unit for controlling writing and reading of the nonvolatile memory,

When the program processed by the CPU includes an extension program in addition to a main program for operating the controller module, the main program is recorded in the ROM, and the extension program is stored in the non-volatile memory. Record in some areas,

4. The semiconductor memory device according to claim 3, wherein a restoration program for restoring an abnormal state of the nonvolatile memory, and a transfer program for transferring the extension program to the RAM are recorded in the R〇M in advance. .

6. The memory module comprises:

A control unit that controls writing and reading of the nonvolatile memory in addition to the nonvolatile memory including the nonvolatile memory array;

3. The semiconductor memory device according to claim 2, wherein the ROM stores at least a program of the control unit.

7. The controller module is

7. The semiconductor memory device according to claim 6, wherein an operation based on the restoration program is started when power is turned on.

8. The semiconductor memory device according to claim 1, wherein the extension program is a program corresponding to a function extension of the semiconductor memory device.

9. The abnormal state of the non-volatile memory is determined by the 2. The semiconductor memory device according to claim 1, wherein data cannot be read correctly.