WO2005036596A3 - Method and apparatus of etch process control in fabrications of microstructures - Google Patents

Method and apparatus of etch process control in fabrications of microstructures Download PDF

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Publication number
WO2005036596A3
WO2005036596A3 PCT/US2004/027760 US2004027760W WO2005036596A3 WO 2005036596 A3 WO2005036596 A3 WO 2005036596A3 US 2004027760 W US2004027760 W US 2004027760W WO 2005036596 A3 WO2005036596 A3 WO 2005036596A3
Authority
WO
WIPO (PCT)
Prior art keywords
amount
etching
fabrications
microstructures
etch chamber
Prior art date
Application number
PCT/US2004/027760
Other languages
French (fr)
Other versions
WO2005036596A2 (en
Inventor
Hongqin Shi
Gregory P Schaadt
Original Assignee
Reflectivity Inc
Hongqin Shi
Gregory P Schaadt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Reflectivity Inc, Hongqin Shi, Gregory P Schaadt filed Critical Reflectivity Inc
Publication of WO2005036596A2 publication Critical patent/WO2005036596A2/en
Publication of WO2005036596A3 publication Critical patent/WO2005036596A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00531—Dry etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/12—Gaseous compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0102—Surface micromachining
    • B81C2201/0105—Sacrificial layer
    • B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108

Abstract

The present invention provides a method for removing sacrificial materials in fabrications of microstructures using a selected spontaneous vapor phase chemical etchants. During the etching process, an amount of the etchant is fed into an etch chamber for removing the sacrificial material. Additional amount of the etchant are fed into the etch chamber according to a detection of an amount or an amount of an etching product so as to maintaining a substantially constant etching rate of the sacrificial materials inside the etch chamber. Accordingly, an etching system is provided for removing the sacrificial materials based on the disclosed etching method.
PCT/US2004/027760 2003-09-17 2004-08-25 Method and apparatus of etch process control in fabrications of microstructures WO2005036596A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/666,671 US7645704B2 (en) 2003-09-17 2003-09-17 Methods and apparatus of etch process control in fabrications of microstructures
US10/666,671 2003-09-17

Publications (2)

Publication Number Publication Date
WO2005036596A2 WO2005036596A2 (en) 2005-04-21
WO2005036596A3 true WO2005036596A3 (en) 2005-12-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/027760 WO2005036596A2 (en) 2003-09-17 2004-08-25 Method and apparatus of etch process control in fabrications of microstructures

Country Status (3)

Country Link
US (1) US7645704B2 (en)
TW (1) TW200512830A (en)
WO (1) WO2005036596A2 (en)

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US8021513B2 (en) * 2006-08-23 2011-09-20 Tokyo Electron Limited Substrate carrying apparatus and substrate carrying method
JP5898549B2 (en) 2012-03-29 2016-04-06 株式会社Ｓｃｒｅｅｎホールディングス Substrate processing method and substrate processing apparatus
JP6231893B2 (en) * 2014-01-27 2017-11-15 キヤノン株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
US10551165B2 (en) * 2015-05-01 2020-02-04 Adarza Biosystems, Inc. Methods and devices for the high-volume production of silicon chips with uniform anti-reflective coatings

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Also Published As

Publication number Publication date
WO2005036596A2 (en) 2005-04-21
US20050059254A1 (en) 2005-03-17
TW200512830A (en) 2005-04-01
US7645704B2 (en) 2010-01-12

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