WO2005038636A1 - Low-power direct digital synthesizer with analog interpolation - Google Patents
Low-power direct digital synthesizer with analog interpolation Download PDFInfo
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- WO2005038636A1 WO2005038636A1 PCT/US2004/034241 US2004034241W WO2005038636A1 WO 2005038636 A1 WO2005038636 A1 WO 2005038636A1 US 2004034241 W US2004034241 W US 2004034241W WO 2005038636 A1 WO2005038636 A1 WO 2005038636A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
- G06F2211/902—Spectral purity improvement for digital function generators by adding a dither signal, e.g. noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00032—Dc control of switching transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
Definitions
- the present invention relates generally to electronics circuits, and more specifically to a direct digital synthesizer (DDS).
- DDS direct digital synthesizer
- clock signals with frequencies that are unrelated may be needed for various functions. For example, a clock signal with a first frequency may be needed for a digital signal processing subsystem, another clock signal with a second frequency may be needed for a sampled analog subsystem, and so on.
- clock signals with unrelated frequencies may be generated in various manners.
- a clock generator with a single phase locked loop (PLL) is operated at a high frequency.
- the clock signal from this generator is divided in frequency by different integer values to obtain multiple output clock signals with different frequencies.
- This design places stringent requirements on the PLL in terms of performance and power consumption, h another conventional design, a separate PLL is provided for each subsystem requiring a clock signal with a different frequency. This design is undesirable because multiple PLLs for multiple clock signals normally consume a large amount of power and occupy a large area.
- an MN counter is used to divide an input clock signal (e.g., from a PLL) by a divider value to obtain an output clock signal with the desired frequency.
- the divider value is a ratio of two integer values M and N (i.e., N M), where M ⁇ 2 • N for proper operation of the MN counter and N/M may be an integer or non-integer value.
- the desired frequency is obtained by dividing the input clock signal in frequency by
- MNA counter An MN counter with analog interpolation (referred to herein as an "MNA counter") capable of generating an output clock signal having improved jitter performance is described herein.
- the jitter performance is minimally affected by IC process variations and system offsets using the design techniques described herein.
- the MNA counter includes an MN counter, a dither generator, an inverse unit, a multiplier, a delay generator, and a current generator.
- the dither generator provides a dither signal used to suppress spurious signals in the output clock signal caused by periodic jitter.
- the MN counter receives an input clock signal, the dither signal, and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal.
- the counter signal has a frequency determined by the input clock frequency and the M and N values, and includes a pulse whenever the modulo-N accumulator wraps around.
- the inverse unit provides a Q value that is an inverse of M.
- the multiplier (which may be implemented with multiple pipelined stages to achieve higher operating speeds) multiplies the accumulator value with the Q value and provides an L-bit control signal.
- the current generator provides a reference current for the delay generator.
- the delay generator receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.
- the delay generator may be implemented with a differential design that utilizes two banks of capacitors.
- the capacitors in each bank may be implemented with binary decoding or thermal decoding and are selectable by the L-bit control signal.
- the selected capacitors in one bank are charged by one current source, and the selected capacitors in the other bank are discharged by another current source.
- the differential signal is defined by the two voltages on the selected capacitors in the two banks.
- the variable delay is determined by the amount of time taken for the two voltages to cross each other. Details of the delay generator are described below.
- the current generator may be implemented with a replica delay generator and a current locked loop.
- the replica delay generator has the same design as the delay generator and is configured to provide a predetermined amount of delay (e.g., one half input clock period of delay) when the proper reference current is received.
- the current locked loop adjusts the reference current so that the predetermined amount of delay is obtained.
- the capacitors for the replica delay generator are matched to the capacitors for the delay generator, and the capacitors for both delay generators are arranged in a two-dimensional array using a common centroid layout to achieve good matching. Low-power is achieved by enabling the replica delay generator a sufficient number of (e.g., two) input clock cycles prior to each output clock edge transition, then disabling the replica delay generator after the transition is complete.
- FIG. 1 shows a clock generation subsystem
- FIG. 2 shows a conventional DDS with an MN counter
- FIG. 3 shows a timing diagram for various types of DDS
- FIG. 4 shows an innovative DDS with an MNA counter
- FIG. 5 shows an MN counter within the MNA counter
- FIG. 6 shows a multiplier within the MNA counter
- FIG. 7 shows a delay generator within the MNA counter
- FIG. 8 A shows a current locked loop for the MNA counter
- FIG. 8B shows a timing diagram for the current locked loop
- FIG. 9 shows a capacitor bank and a decoder within the delay generator
- FIG. 10 shows one capacitor unit within the capacitor bank
- FIG. 11 shows a capacitor array for the delay generator and replica delay generator
- FIG. 12 shows a wireless device in a wireless communication system.
- FIG. 1 shows a block diagram of a clock generation subsystem, 100 that includes a phase locked loop (PLL) 110 and a direct digital synthesizer (DDS) 120.
- PLL 110 receives a reference signal (Ref) and generates an input clock signal (CLKin).
- the input clock signal has its frequency and or phase locked to that of the reference signal.
- PLL 110 may be implemented with a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO), and a divider, as is known by one skilled in the art.
- DDS 120 receives the input clock signal and generates an output clock signal (CLKout) having a frequency that is a fraction of the input clock frequency.
- FIG. 1 shows a block diagram of a clock generation subsystem, 100 that includes a phase locked loop (PLL) 110 and a direct digital synthesizer (DDS) 120.
- PLL 110 receives a reference signal (Ref) and generates an input clock signal (CLKin).
- MN counter 220 receives the input clock signal and the M and N values, each of which is an integer one or greater, and generates the output clock signal having a frequency that is N/M times that of the input clock signal.
- a summer 224 receives and adds M to an accumulator value (ACC) from a register 222 and provides a first combined value (VI) to a summer 226 and to a '1' input of a multiplexer (MUX) 228.
- Summer 226 receives and subtracts N from the first combined value and provides a second combined value (V2) to a '0' input of multiplexer 228.
- Summer 226 also provides a one-bit inverted overflow signal (OVFb) to an inverter 230 and to a select input of multiplexer 228.
- OVFb inverted overflow signal
- the OVFb signal is logic low if there is an overflow (described below) and logic high otherwise.
- Multiplexer 228 provides the first combined value if there is no overflow and the second combined value if there is an overflow.
- Register 222 receives and stores the value from multiplexer 228.
- Inverter 230 receives and inverts the OVFb signal and provides the output clock signal.
- MN counter 220 operates as follows. Register 222, summers 224 and 226, and multiplexer 228 collectively implement a modulo-N accumulator that stores a value ranging from 0 to N - 1.
- the accumulator For each input clock cycle, the accumulator accumulates M with the current accumulator value and provides the first combined value, which is stored back in register 222 if an overflow has not occurred.
- An overflow occurs whenever the first combined value exceeds N and is indicated by the OVFb signal being at logic low.
- N is subtracted from the first combined value and the result is stored in register 222.
- a pulse is provided on the output clock signal when an overflow occurs.
- FIG. 3 shows a timing diagram that illustrates the operation of MN counter 220.
- register 222 is reset and the accumulator value (ACC) is equal to zero.
- a value of eight is then subtracted from the first combined value, and a value of one is stored in register 222.
- the same computation proceeds for each subsequent input clock cycle.
- a clock pulse is provided on the output clock signal whenever an overflow occurs and eight is subtracted from the first combined value.
- the output clock signal has a frequency that is 3/8 times the input clock frequency and is generated by dividing the input clock signal in frequency by 3, then by 3, then by 2, and so on.
- the average period of the output clock signal is 8T CLKin /3, as desired, where Tcu ⁇ n is one input clock period.
- the output clock signal has instantaneous periods of 3TcLKin, 3T( ⁇ in > and 2TcL in, which give a worst-case cycle-to-cycle jitter of Tc LK i n -
- the jitter has a periodicity of 8Tc LKm since the jitter follows a pattern that repeats every eight input clock periods. This periodic jitter results in spurs appearing in the spectrum of the output clock signal.
- the spurs can have relatively large amplitude and may be detrimental for some applications (e.g., high quality audio) that require spectrally pure clock signals.
- An MN counter with analog interpolation can be used to reduce jitter and spurs.
- the MNA counter attempts to reduce jitter by shifting the position of the leading edges (e.g., rising edges) of the output clock signal such that all output clock periods are the same. This is achieved by determining the amount of phase shift needed for each output clock cycle to obtain the desired output clock period and then advancing the leading edge accordingly.
- the output clock signal from the ideal MNA counter is shown having a period of 8T CLKin /3 for each clock cycle.
- the amount of phase shift to achieve the ideal output clock period can be expressed as:
- phase shift can be generated exactly and if the leading edges can be advanced by this phase shift without errors, then all of the output clock cycles will have equal period and the ideal MNA counter will have zero jitter.
- a delay generator can be used to generate the desired phase shift for the MNA counter.
- the delay generator can be designed to generate phase shifts in discrete steps. Higher accuracy can be attained for the delay generator with greater circuit complexity, more die area, and higher power consumption. Thus, there is a trade-off between the accuracy of the delay generator and other system considerations.
- a fraction of 1/3 is estimated as 3/8
- a fraction of 2/3 is estimated as 5/8.
- the output clock period is 21T CLKin /8 , then 22T CLKin /8 , then 21T CLKin /8 , and so on, as shown in FIG. 3.
- the worst-case cycle-to-cycle jitter is T CLKjn /8 with the 3- bit delay generator.
- a phase shift to advance the output clock edge (i.e., a negative phase shift) can be obtained by operating the delay generator one input clock cycle early and generating a delay that is complementary to the negative phase shift.
- the delay may be expressed as:
- FIG. 4 shows a block diagram of an MNA counter 400 that may be used for DDS 120 in FIG. 1.
- an MN counter 420 receives the input clock signal (CLKin), the M and N values, and a dither signal from a dither generator 440.
- the dither signal is used to suppress large amplitude spurious signals in the output clock signal caused by periodic jitter.
- MN counter 420 performs accumulation of M with a modulo-N accumulator to implement an "M divided by N" operation, as described above.
- MN counter 420 provides an accumulator value (ACC) and a counter signal (Ce2).
- the counter signal has the desired frequency and is derived based on an overflow signal within MN counter 420.
- a D flip-flop (D-FF) 422 receives and delays the Ce2 signal by one input clock cycle and provides a delayed counter signal (Cel).
- Another D flip-flop (D-FF) 424 receives and delays the Cel signal by one input clock cycle and provides another delayed counter signal (Cout).
- the Cel and Ce2 signals are early with respect to the Cout signal by one and two input clock cycles, respectively, as indicated by the "el" and "e2" designations. Since the phase shift needs to be generated before the overflow occurs, as shown in FIG. 3, the counter signal from MN counter 420 is delayed by two input clock cycles to obtain the Cout signal.
- the Cel and Ce2 signals are used to enable generation of the desired delay prior to the Cout signal.
- Dither generator 440 generates the dither signal and is described below.
- a multiplier 460 receives the ACC value, the Q value, and the Ce2 signal. Multiplier 460 multiplies the ACC value with the Q value, when enabled by the Ce2 signal, and provides a P value for an L-bit control signal.
- the P value corresponds to the term (1-F ; /2 L ) in equation (4).
- the P value is obtained by quantizing the product of ACCj and Q using L bits (with rounding for the least significant bit) and inverting all of the L bits.
- the P value is indicative of the amount of delay (if any) required for the current output clock cycle.
- a delay generator 470 receives the P value and the Cel and Ce2 signals and generates the output clock signal (CLKout). The output clock signal has each leading edge shifted by the delay indicated by the P value.
- a current generator 480 generates the reference currents, I re and I ref , for delay generator 470.
- FIG. 5 shows a block diagram of an embodiment of MN counter 420 within MNA counter 400.
- N is not a power of 2
- two full adders operate serially to perform accumulation of M using a modulo-N accumulator, as described above for FIG. 2.
- high-speed circuitry is used to implement the two full adders.
- a carry-save adder (CSA) 524 receives and combines M, the dither signal, and the accumulator value (ACC) (i.e., three input terms) and provides two output terms.
- a CSA 526 receives and sums the two output terms from CSA 524 and subtracts N and provides two output terms.
- a carry lookahead adder (CLA) 528a combines the two output terms from CSA 524 and provides the first combined value (VI) to a multiplexer 530.
- a CLA 528b combines the two output terms from CSA 526 and provides the second combined value (V2) to multiplexer 530.
- CLA 528b also provides the Ce2 signal.
- Multiplexer 530 provides either the VI or V2 value to a register 522 depending on the Ce2 signal.
- MN counter 420 can be operated at a high operating speed because of the use of carry-save adders and carry lookahead adders. However, other designs may also be used for MN counter 420.
- Dither generator 440 provides the one-bit dither signal that is used to randomize the jitter and reduce the amplitude of the spurs caused by periodic jitter from MN counter 420.
- the dither signal can be generated based on a pseudo-random number (PN) sequence.
- PN pseudo-random number
- Dither generator 440 may thus be implemented with a linear feedback shift register (LFSR) that is configured to implement a polynomial generator for a PN sequence.
- LFSR linear feedback shift register
- a 26-bit LFSR that implements a polynomial generator x 25 + x 24 + x 20 + 1 may be used for dither generator 440.
- the dither signal comprises a repeating pseudo-random sequence of +1 and -1 and does not introduce an average frequency offset to the output clock frequency.
- Other designs for generating the one-bit dither signal may be used without affecting the scope of the embodiments herein.
- Inverse unit 450 may be implemented with a serial division algorithm, a look-up table, or some other manner.
- FIG. 6 shows a block diagram of an embodiment of multiplier 460 within MNA counter 400 in FIG. 4.
- Multiplier 460 operates when an overflow occurs in MN counter 420, which may be infrequent for some values of M and N. Although the activity rate may be low, the execution window for multiplier 460 is equal to the input clock rate, which may be relatively high. To support a high input clock frequency, multiplier 460 is implemented as a three-stage pipelined multiplier.
- latches 612a and 612b latch the ACC and Q values, respectively, with the Ce2 signal. Latches 612a and 612b inhibit the ACC value from rippling through multiplier 460 if no overflow occurs in MN counter 420.
- a partial product tree generator 614 performs multiplication of the ACC and Q values by generating partial product terms and accumulating these terms in multiple accumulation stages. Partial product tree generator 614 provides two partial product terms.
- D flip-flops 622a and 622b store the two partial product terms from partial product tree generator 614.
- a carry-select adder 624 combines the two partial product terms from D flip-flops 622a and 622b and provides the final result.
- the partial product accumulation is divided into two pipeline stages to support higher operating speed for multiplier 460.
- the multiplication can be partitioned into more than two stages for even higher operating speed.
- a D flip-flop 632a stores the most significant bits (MSB) of the final result from carry-select adder 624 and a D flip-flop 632b stores the least significant bit (LSB) of the final result.
- An AND gate 634 performs a logical AND of the LSB from D flip-flop 632b with a Round Enable signal.
- a CSA 636 combines the MSB of the final result from D flip-flop 632a with the output of AND gate 634 and provides the combined result to a D flip-flop 638. The rounding of the final result can reduce truncation errors by 1/2 LSB.
- D flip-flop 638 provides the P value, which is approximately equal to ACC/M and quantized to L bits.
- Multiplier 460 may also be implemented with other designs (e.g., a look-up table that is indexed by the accumulator value).
- a delay generator can generate a number of discrete delays by charging and discharging a bank of capacitors. Different delays can be obtained by turning on (i.e., selecting) different combination of capacitors in the bank.
- the delay generated by the delay generator can be expressed as:
- Equation (5) shows that the delay is dependent on three parameters that are in turn dependent on the IC manufacturing process. Since accurate generation of the delay is needed to achieve good jitter performance, techniques are described herein to mitigate the effects of C ⁇ oa d, V SW mg, and Ic h on jitter performance.
- FIG. 7 shows a block diagram of a delay generator 470 within MNA counter 400 in FIG. 4.
- Delay generator 470 uses a differential design to provide good rejection of power supply noise and to mitigate the effects of circuit component mismatches.
- Delay generator 470 also uses a reference current from a current locked loop (CLL) to accurately generate the charging current.
- CLL current locked loop
- Delay generator 470 includes two banks of capacitors, 710 and 720.
- Bank 710 includes S capacitors 712a through 712s, each having one end coupled to circuit ground and the other end coupled to a node V p via switches 714a through 714s, respectively. S is dependent on the number of bits (L) and the design for delay generator 470.
- Bank 720 includes S capacitors 722a through 722s, each having one end coupled to circuit ground and the other end coupled to a node V n via switches 724a through 724s, respectively.
- a switch 732 has one end coupled to node V p and the other end coupled to circuit ground.
- a switch 734 has one end coupled to node V p and the other end coupled to one end of a current source 736. The other end of current source 736 couples to a supply voltage (V DD ).
- a switch 742 has one end coupled to node V n and the other end coupled to V DD -
- a switch 744 has one end coupled to node V n and the other end coupled to one end of a current source 746. The other end of current source 746 couples to circuit ground.
- a comparator 750 has a non-inverting input coupled to node V p , an inverting input coupled to node V n , and an output that provides the output clock signal.
- a decoder 770 receives the P value from multiplier 460 and generates control signals for switches 714 and 724 to select the desired capacitors and deselect the remaining capacitors.
- Current source 736 receives the reference current I re from current generator 480 provides a charging current of I dg .
- Current source 746 receives the reference current I refh from current generator 480 and provides a discharging current of I dg .
- Current sources 736 and 746 may be implemented with constant-g m current sources or some other types of current sources.
- Capacitors 712 and 722, switches 714 and 724, and decoder 770 may be implemented as described below.
- Delay generator 470 operates as follows. When the Ce2 signal is activated due to an overflow in MN counter 420, switches 714, 724, 732, and 742 are all turned on for one input clock cycle, capacitors 712 in bank 710 are discharged to circuit ground by switch 732, capacitors 722 in bank 720 are precharged to V DD by switch 742, node V p is at circuit ground, node V n is at V DD , and the output clock signal is at logic low. One input clock cycle later, switches 732 and 742 are turned off and only selected ones of switches 714 and 724 in banks 710 and 720 are turned on by the P value from multiplier 460.
- the selected capacitors in banks 710 and 720 are those with their associated switches turned on.
- switches 734 and 744 are turned on by the Cel signal
- the selected capacitors in bank 710 are charged toward V DD by current source 736
- the selected capacitors in bank 720 are discharged toward circuit ground by current source 746
- the voltage on node V p rises
- the voltage on node V n drops.
- a differential signal is defined by the voltages on nodes V p and V n .
- the output clock signal transitions to logic high.
- the leading edge of the output clock signal is thus determined by the amount of delay provided by delay generator 470.
- the enable signals for delay generator 470 are delayed appropriately to line up with the arrival of the P signal from multiplier 460.
- the output clock signal provided by delay generator 470 within MNA counter 400 does not have 50% duty cycle.
- the M value may be doubled, and the output signal from comparator 750 may be divided by two (2) to obtain the output clock signal.
- the maximum N M ratio is then limited to 0.5 for proper operation of the MNA counter.
- the delay generated by delay generator 470 may be expressed as:
- the factor VD D /2 is the voltage swing for the capacitors in each bank with the differential design and corresponds to V SWmg in equation (5).
- the factor 2 L • C ⁇ is the total capacitance for all capacitors in one bank.
- the factor [1- ACC ; /M] corresponds to the P value from multiplier 460.
- the factor C dg 2 L • C ⁇ jj • [1 - ACC; / M] is the capacitance for all selected capacitors in one bank and corresponds to C ⁇ oa d in equation (5).
- FIG. 8A shows a block diagram of a current locked loop 480a, which is one embodiment of bias current generator 480 in FIG. 4.
- a divide-by-2 unit 812 receives and divides the input clock signal (CLKin) by two and provides a divided clock signal (CLK2). Unit 812 uses the trailing edges of the input clock signal to perform the divide-by-2.
- An AND gate 814 performs a logical AND of the CLKin signal and the CLK2 signal and provides a reference clock signal (R).
- a replica delay generator 870 delays the CLK2 signal by one half input clock period and provides a delayed clock signal (V).
- the CLK2 signal may be provided to a dummy AND gate matched to AND gate 814, and the output of the dummy AND gate can be provided to delay generator 870.
- a phase-frequency detector (PFD) 830 compares the phase of the reference clock signal and the phase of the delayed clock signal and provides a phase error.
- PFD 830 may be implemented with an early-late detector that is known in the art.
- a charge pump 832 converts the phase error into a current.
- a loop filter implemented with a single capacitor 834, filters the current from charge pump 832 and also converts the current into a voltage.
- Capacitor 834 can be a small capacitor if the input clock rate is high.
- a voltage-to-current (V-to-I) converter 840 converts the voltage on capacitor 834 back into a current using current mirrors and provides the reference currents I re ⁇ and I ref to replica delay generator 870.
- Replica delay generator 870 adjusts its delay based on the reference currents I ref p and I ref o such that the delayed clock signal is time-aligned with the reference clock signal.
- V-to-I converter 840 also provides the reference currents I ref and e g, to current sources 736 and 746 within delay generator 470.
- FIG. 8B shows a timing diagram for current locked loop 480a.
- the reference clock signal is the input clock signal divided by two and delayed by one half input clock period.
- Replica delay generator 870 generates a delay of one half input clock period for the divided clock signal when the correct reference current is received from V-to-I converter 840.
- the current lock loop adjusts the reference current such that the leading edges of the reference clock signal and the delayed clock signal are time- aligned.
- the closed loop transfer function H(s) for current locked loop 480a may be expressed as:
- Equation (7) indicates that current locked loop 480a is a single pole system that is unconditionally stable. However, similar to a delay locked loop, the current locked loop can false lock to a zero time period or a double time period. False lock can be prevented by ensuring that the forward gain is not too large.
- One method of achieving this is to control the charge pump current I cp (e.g., from 5 ⁇ A to 40 ⁇ A, in 5 ⁇ A steps).
- a large charge pump current I cp may be used initially to achieve fast locking.
- a small current may be used thereafter to prevent the current locked loop from overshooting.
- the gain K v2 i is adjusted such that delay generator 870 is capable of producing one half input clock period of delay for the entire range of input clock frequencies and over all process corners.
- the gain K dg is controlled by the size of the capacitors in delay generator 870.
- Replica delay generator 870 has the same design as delay generator 470.
- the delay generated by replica delay generator 870 may be expressed as: ⁇ _ C ⁇ rdg -V ⁇ DP _ T -*- CLKin p_ o ⁇ J-delay.rbg ⁇ T n ⁇ ⁇ _ > TM ⁇ > J-rdg ' Z
- C r d g is the capacitance and I rdg is the charging current for replica delay generator 870.
- Replica delay generator 870 is designed to provide a delay of Tc LK i n /2 with capacitance C rdg and current I rdg .
- Delay generator 470 is designed to provide a delay of Tc K in with capacitance 2 L • C ⁇ and current I dg .
- the capacitance to current (C/I) ratio for replica delay generator 870 is thus one half of the C/I ratio for delay generator 470, since the same voltage swing VD D is used for both generators.
- the accuracy of delay generator 470 is dependent on the matching between the capacitance of delay generator 470 and the capacitance of replica delay generator 870.
- Current locked loop 480a thus removes the effects of the supply voltage V DD and the charging current I dg , and the accuracy of delay generator 470 is not impacted by these two parameters.
- the capacitors for delay generator 470 and replica delay generator 870 may be implemented in various manners.
- binary decoding is used for the capacitors in each of banks 710 and 720 in FIG. 7.
- each bank includes L capacitors having binary weighted capacitance of C un it, 2C un it, 4C un it, .. • and 2 • C ⁇ jjt .
- Each capacitor is selected or deselected based on a respective bit of the P value from multiplier 460.
- thermal decoding is used for the capacitors in each bank to improve linearity.
- 2 capacitors are provided for each bank, and each capacitor has the same capacitance of C un i t -
- the 2 L capacitors can be matched more easily because they all have the same dimension. Consequently, smaller matching error is encountered and greater linearity is achieved.
- the selected capacitors may be dispersed (e.g., randomly selected) among the 2 L capacitors to reduce gradient linearity error (if any), which is a systematic error across an IC die caused by manufacturing.
- FIG. 9 shows a diagram of an embodiment of capacitor bank 710 and decoder 770.
- Bank 710 includes 64 capacitors arranged in a 4x16 array with four rows and sixteen columns. Each capacitor has a capacitance of C un i t - Decoder 770 receives the 6-bit P value and generates the controls for the 64 capacitors.
- a thermal decoder 912 receives the four MSBs of the P value and provides to a D flip-flop 922 sixteen column controls for the sixteen columns of the 4x16 array.
- FIG. 10 shows a diagram for one capacitor unit 718x among 2 L capacitor units for capacitor bank 710 for an implementation using thermal decoding.
- Capacitor cell 718x is for one row of one column of the 4x16 array shown in FIG. 9.
- Capacitor cell 718x includes a capacitor 712x, anN-channel transistor 714x, and a logic unit 716x.
- Capacitor 712x is one of capacitors 712 in bank 710 and has a capacitance of C un i t
- N-channel transistor 714x is for one of switches 714 in bank 710.
- Logic unit 716x receives a control for row i and controls for column j and j+1 from decoder 770 and generates a gate signal for N-channel transistor 714x based on the three input controls.
- 64 control signals would be needed.
- the capacitors in the 4x16 array are selected one column at a time. For example, to select nine capacitors, all four capacitors in the first and second columns are selected, and one capacitor in the third column is selected.
- N- channel transistor 714x couples capacitor 712x to node V p .
- the size of N-channel transistor 714x can affect the jitter reduction capability of MNA counter 400.
- a small- size N-channel transistor 714x can provide better jitter performance.
- the accuracy of delay generator 470 is dependent on the matching between the capacitors for delay generator 470 and replica delay generator 870.
- the capacitors for both delay generators 470 and 870 can be implemented as one array arranged in a two-dimensional (2-D) common centroid layout.
- FIG. 11 shows a diagram of an exemplary implementation of a capacitor array 1100 for delay generator 470 and replica delay generator 870 using a 2-D interdigitated, common centroid layout.
- delay generator 470 has 6-bit accuracy
- the 64 capacitors for each of banks 710 and 720 are arranged into four rows, as described above.
- Capacitor array 1100 includes twelve rows - four rows for the capacitors in bank 710, four rows for the capacitors in bank 720, and four rows for the capacitors in replica delay generator 870.
- capacitor array 1100 includes six sections 1110a through 111 Of.
- Section 1110a includes capacitor row 3 for both banks 710 and 720
- section 1110b includes capacitor rows 1 and 3 for replica delay generator 870
- section 1110c includes capacitor row 1 for both banks
- section lllOd includes capacitor row 0 for both banks
- section lllOe includes capacitor rows 0 and 2 for replica delay generator 870
- section ll lOf includes capacitor row 2 for both banks.
- the capacitors in rows 0, 1, 2, and 3 for bank 710 are coupled to node V p when enabled.
- the capacitors in rows 0, 1, 2, and 3 for bank 720 are coupled to node V n when enabled.
- the capacitors for replica delay generator 870 are always on and no controls are needed, as indicated in FIG. 11.
- the capacitors in the rows for replica delay generator 870 are coupled to two corresponding nodes V, p and V m within the generator 870.
- the MNA counter design described herein provides good performance and other advantages.
- the differential design allows for a reduction in the size of the capacitors in delay generators 470 and 870.
- the smaller capacitor size results in less power being consumed to generate the desired delay.
- a smaller area is required to implement the smaller-size capacitors.
- the current locked loop removes the dependency on voltage swing and charging current, which improves the accuracy of the delay generator.
- the current locked loop and multiplier may be turned on one or two input clock cycles before they are needed (e.g., using the Cel and Ce2 signals) and turned off thereafter.
- FIG. 12 shows a block diagram of a wireless device 1200 in a wireless communication system.
- Wireless device 1200 may be a cellular phone, a terminal, a handset, or some other devices or designs.
- the wireless communication system may be a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a multiple-input multiple-output (M O) system, an orthogonal frequency division multiplexing (OFDM) system, an orthogonal frequency division multiple access (OFDMA) system, and so on.
- CDMA Code Division Multiple Access
- GSM Global System for Mobile Communications
- M O multiple-input multiple-output
- OFDM orthogonal frequency division multiplexing
- OFDMA orthogonal frequency division multiple access
- signals transmitted by base stations are received by an antenna 1212, routed through a duplexer (D) 1214, and provided to a receiver unit (RCVR) 1216.
- Receiver unit 1216 conditions (e.g., filters, amplifies, and frequency downconverts) the received signal and digitizes the conditioned signal to provide samples, which are provided to a digital signal processor (DSP) 1220 for further processing.
- DSP digital signal processor
- DSP digital signal processor
- data to be transmitted from wireless device 1200 is provided by DSP 1220 to a transmitter unit (TMTR) 1218.
- Transmitter unit 1218 conditions (e.g., filters, amplifies, and frequency upconverts) the data and generates a modulated signal, which is routed through duplexer 1214 and transmitted via antenna 1212 to the base stations.
- DSP 1220 includes various processing units such as, for example, an internal controller 1222, a processor 1224, a memory unit 1226, a bus control unit 1228, and an audio processor 1236, all of which are coupled via a bus 1238.
- DSP 1220 further includes a PLL 1230 that receives a reference signal (e.g., from a temperature compensated crystal oscillator (TCXO)) and generates a master clock for DSP 1220.
- PLL 1230 may generate various clock signals (e.g., by dividing the master clock with different integer values) for the processing units within DSP 1220 and possibly for processing units external to DSP 1220 (e.g., a main controller 1240 and a main memory unit 1242).
- An MNA counter 1234 receives the master clock and generates a first low- jitter clock signal for audio processor 1236.
- An MNA counter 1234 receives the master clock and generates a second low-jitter clock signal for another processing unit (e.g., analog-to-digital converters within receiver unit 1216).
- the first and second low-jitter clock signals have different frequencies.
- one MNA counter may be used to generate each different clock frequency that is not an integer multiple of the master clock.
- MNA counters 1232 and 1234 may each be implemented with MNA counter 400 in FIG. 4.
- DSP 1220 may include various processing units and perform various functions, which may be dependent on the specific design of DSP 1220 and the communication system.
- FIG. 12 shows an exemplary design of a wireless device in which the MNA counter described herein may be implemented and used.
- the MNA counter described herein may also be implemented in other electronic devices.
- the direct digital synthesizer with analog interpolation may be implemented in an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a micro-controller, a microprocessor, and other electronic units.
- ASIC application specific integrated circuit
- DSP digital signal processor
- DSPD digital signal processing device
- PLD programmable logic device
- FPGA field programmable gate array
- the MNA counter may be implemented within the one or multiple integrated circuit (IC) dies and in the one or multiple ICs. For example, all units of the MNA counter may be implemented on one IC die.
- the digital portion of the MNA counter (e.g., MN counter 420, dither generator 440, inverse unit 450, multiplier 460, and D flip-flops 422 and 424 in FIG. 4) may be implemented on one IC die and the analog portion of the MNA counter (e.g., delay generator 470 and current generator 480) may be implemented on another IC die.
- the analog portion of the MNA counter e.g., delay generator 470 and current generator 480
- the MNA counter may also be fabricated with various IC process technologies such as CMOS, NMOS, BJT, and so on.
- the MNA counter may also be fabricated using different device size technologies (e.g., 0.13 mm, 30 nm, and so on).
- Portions of the MNA counter (e.g., inverse unit 450 and multiplier 460) may be implemented in software.
- the modules e.g., procedures, functions, and so on) may be used to perform some of the functions described herein.
- the software codes may be stored in a memory unit (e.g., memory unit 1226 or 1242 in FIG. 12) and executed by a processor (e.g., processor 1224 or controller 1240).
- the memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.
Abstract
Description
Claims
Priority Applications (2)
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BRPI0415416-9A BRPI0415416A (en) | 2003-10-14 | 2004-10-14 | low power digital direct synthesizer with analog interpolation |
IL174937A IL174937A (en) | 2003-10-14 | 2006-04-11 | Low-power direct digital synthesizer with analog interpolation |
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US10/684,797 | 2003-10-14 | ||
US10/684,797 US6958635B2 (en) | 2003-10-14 | 2003-10-14 | Low-power direct digital synthesizer with analog interpolation |
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PCT/US2004/034241 WO2005038636A1 (en) | 2003-10-14 | 2004-10-14 | Low-power direct digital synthesizer with analog interpolation |
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US (2) | US6958635B2 (en) |
KR (1) | KR100825240B1 (en) |
BR (1) | BRPI0415416A (en) |
IL (1) | IL174937A (en) |
SG (1) | SG147438A1 (en) |
TW (1) | TW200524287A (en) |
WO (1) | WO2005038636A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10346768B2 (en) | 2009-12-23 | 2019-07-09 | Aea Integration, Inc. | System and method for automated building services design |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060095221A1 (en) * | 2004-11-03 | 2006-05-04 | Teradyne, Inc. | Method and apparatus for controlling variable delays in electronic circuitry |
JP2008131560A (en) * | 2006-11-24 | 2008-06-05 | Yokogawa Electric Corp | Frequency divider circuit |
US7667504B2 (en) * | 2007-05-22 | 2010-02-23 | International Business Machines Corporation | Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals |
DE102007031127A1 (en) | 2007-06-29 | 2009-01-02 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Phase locked loop circuit for frequency synthesizer, has control unit connected to divisor and designed for controlling divisor exhibiting comparator function and multiplexer designed for phase quantization and output feedback signal |
EP2063534B1 (en) * | 2007-11-23 | 2012-02-01 | STMicroelectronics Srl | Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process |
US8242850B2 (en) * | 2008-08-28 | 2012-08-14 | Resonance Semiconductor Corporation | Direct digital synthesizer for reference frequency generation |
US7724097B2 (en) * | 2008-08-28 | 2010-05-25 | Resonance Semiconductor Corporation | Direct digital synthesizer for reference frequency generation |
US8836257B2 (en) * | 2008-10-09 | 2014-09-16 | Bsh Home Appliances Corporation | Household appliance including a fan speed controller |
CN103017800B (en) * | 2011-09-27 | 2015-09-02 | 比亚迪股份有限公司 | For method and the device of orthogonal intersection code signal of decoding |
US8508267B1 (en) * | 2012-01-24 | 2013-08-13 | Texas Instruments Incorporated | Loop filter for current-controlled-oscillator-based phase locked loop |
US8831158B2 (en) | 2012-03-29 | 2014-09-09 | Broadcom Corporation | Synchronous mode tracking of multipath signals |
CN103856186B (en) * | 2012-12-05 | 2016-12-21 | 戴泺格集成电路(天津)有限公司 | Duty ratio adjusting circuit and control method |
JP6142567B2 (en) * | 2013-02-22 | 2017-06-07 | ノーリツプレシジョン株式会社 | Pulse motor driving device and pulse motor driving method |
US8884663B2 (en) * | 2013-02-25 | 2014-11-11 | Advanced Micro Devices, Inc. | State machine for low-noise clocking of high frequency clock |
CN103269218A (en) * | 2013-04-19 | 2013-08-28 | 西安交通大学 | Implementation method for arbitrary fractional divider based on FPGA/CPLD |
JP6254394B2 (en) * | 2013-09-09 | 2017-12-27 | 株式会社メガチップス | Synchronous system and frequency divider |
US9698792B1 (en) * | 2016-11-22 | 2017-07-04 | Nxp B.V. | System and method for clocking digital logic circuits |
US10459477B2 (en) * | 2017-04-19 | 2019-10-29 | Seagate Technology Llc | Computing system with power variation attack countermeasures |
CN109085879A (en) * | 2017-06-13 | 2018-12-25 | 北京航天计量测试技术研究所 | A kind of high-precision DDS frequency synthesizer for the multi-functional calibration platform of electricity |
US10373671B1 (en) * | 2018-04-09 | 2019-08-06 | Micron Technology, Inc. | Techniques for clock signal jitter generation |
CN110618729A (en) * | 2018-06-19 | 2019-12-27 | 迈普通信技术股份有限公司 | Baud rate generator, communication equipment and generation method of Baud rate clock signal |
US10797594B1 (en) * | 2019-12-09 | 2020-10-06 | Psemi Corporation | Shared comparator for charge pumps |
CN111600604A (en) * | 2020-07-24 | 2020-08-28 | 山东北斗院物联科技有限公司 | Method and system for generating digital chip peripheral clock |
CN114115436B (en) * | 2021-10-21 | 2023-06-13 | 湖南艾科诺维科技有限公司 | Multi-path parallel DDS bidirectional linear sweep frequency method, system and medium based on FPGA platform |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4494243A (en) * | 1981-11-26 | 1985-01-15 | Itt Industries, Inc. | Frequency divider presettable to fractional divisors |
US4652832A (en) * | 1985-07-05 | 1987-03-24 | Motorola, Inc. | Frequency resolution in a digital oscillator |
US5481230A (en) * | 1994-11-14 | 1996-01-02 | Tektronix, Inc. | Phase modulator having individually placed edges |
US6188261B1 (en) * | 1998-01-26 | 2001-02-13 | Nippon Telegraph And Telephone Corporation | Programmable delay generator and application circuits having said delay generator |
US6239616B1 (en) * | 1997-01-21 | 2001-05-29 | Xilinx, Inc. | Programmable delay element |
US6243784B1 (en) * | 1996-06-28 | 2001-06-05 | Lsi Logic Corporation | Method and apparatus for providing precise circuit delays |
US6434707B1 (en) * | 1999-06-07 | 2002-08-13 | Motorola, Inc. | Low phase jitter clock signal generation circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5907253A (en) * | 1997-11-24 | 1999-05-25 | National Semiconductor Corporation | Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element |
US6064272A (en) * | 1998-07-01 | 2000-05-16 | Conexant Systems, Inc. | Phase interpolated fractional-N frequency synthesizer with on-chip tuning |
DE19840241C1 (en) * | 1998-09-03 | 2000-03-23 | Siemens Ag | Digital PLL (Phase Locked Loop) frequency synthesizer |
US6236278B1 (en) * | 2000-02-16 | 2001-05-22 | National Semiconductor Corporation | Apparatus and method for a fast locking phase locked loop |
FI108380B (en) * | 2000-03-10 | 2002-01-15 | Nokia Corp | MÕngbrÕkdivisorf ÷ rskalare |
US6404289B1 (en) * | 2000-12-22 | 2002-06-11 | Atheros Communications, Inc. | Synthesizer with lock detector, lock algorithm, extended range VCO, and a simplified dual modulus divider |
US6836526B2 (en) * | 2003-02-25 | 2004-12-28 | Agency For Science, Technology And Research | Fractional-N synthesizer with two control words |
-
2003
- 2003-10-14 US US10/684,797 patent/US6958635B2/en not_active Expired - Lifetime
-
2004
- 2004-10-14 BR BRPI0415416-9A patent/BRPI0415416A/en not_active IP Right Cessation
- 2004-10-14 WO PCT/US2004/034241 patent/WO2005038636A1/en active Application Filing
- 2004-10-14 SG SG200807659-8A patent/SG147438A1/en unknown
- 2004-10-14 KR KR1020067009426A patent/KR100825240B1/en active IP Right Grant
- 2004-10-14 TW TW093131215A patent/TW200524287A/en unknown
-
2005
- 2005-07-20 US US11/186,451 patent/US7098708B2/en not_active Expired - Fee Related
-
2006
- 2006-04-11 IL IL174937A patent/IL174937A/en not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4494243A (en) * | 1981-11-26 | 1985-01-15 | Itt Industries, Inc. | Frequency divider presettable to fractional divisors |
US4652832A (en) * | 1985-07-05 | 1987-03-24 | Motorola, Inc. | Frequency resolution in a digital oscillator |
US5481230A (en) * | 1994-11-14 | 1996-01-02 | Tektronix, Inc. | Phase modulator having individually placed edges |
US6243784B1 (en) * | 1996-06-28 | 2001-06-05 | Lsi Logic Corporation | Method and apparatus for providing precise circuit delays |
US6239616B1 (en) * | 1997-01-21 | 2001-05-29 | Xilinx, Inc. | Programmable delay element |
US6188261B1 (en) * | 1998-01-26 | 2001-02-13 | Nippon Telegraph And Telephone Corporation | Programmable delay generator and application circuits having said delay generator |
US6434707B1 (en) * | 1999-06-07 | 2002-08-13 | Motorola, Inc. | Low phase jitter clock signal generation circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10346768B2 (en) | 2009-12-23 | 2019-07-09 | Aea Integration, Inc. | System and method for automated building services design |
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US7098708B2 (en) | 2006-08-29 |
SG147438A1 (en) | 2008-11-28 |
TW200524287A (en) | 2005-07-16 |
KR100825240B1 (en) | 2008-04-25 |
US20050077934A1 (en) | 2005-04-14 |
IL174937A0 (en) | 2006-08-20 |
BRPI0415416A (en) | 2006-12-05 |
US6958635B2 (en) | 2005-10-25 |
KR20060096106A (en) | 2006-09-06 |
IL174937A (en) | 2010-12-30 |
US20050253632A1 (en) | 2005-11-17 |
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