WO2005041259A3 - A system-level test architecture for delivery of compressed tests - Google Patents

A system-level test architecture for delivery of compressed tests Download PDF

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Publication number
WO2005041259A3
WO2005041259A3 PCT/US2004/031055 US2004031055W WO2005041259A3 WO 2005041259 A3 WO2005041259 A3 WO 2005041259A3 US 2004031055 W US2004031055 W US 2004031055W WO 2005041259 A3 WO2005041259 A3 WO 2005041259A3
Authority
WO
WIPO (PCT)
Prior art keywords
tests
compressed
delivery
level test
test architecture
Prior art date
Application number
PCT/US2004/031055
Other languages
French (fr)
Other versions
WO2005041259A2 (en
Inventor
Srivaths Ravi
Anand Raghunathan
Loganathan Lingappan
Srimat T Chakradhar
Niraj K Jha
Original Assignee
Nec Lab America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Lab America Inc filed Critical Nec Lab America Inc
Publication of WO2005041259A2 publication Critical patent/WO2005041259A2/en
Publication of WO2005041259A3 publication Critical patent/WO2005041259A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Abstract

An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
PCT/US2004/031055 2003-10-17 2004-09-22 A system-level test architecture for delivery of compressed tests WO2005041259A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51167203P 2003-10-17 2003-10-17
US60/511,672 2003-10-17
US10/795,231 2004-03-09
US10/795,231 US7278123B2 (en) 2003-10-17 2004-03-09 System-level test architecture for delivery of compressed tests

Publications (2)

Publication Number Publication Date
WO2005041259A2 WO2005041259A2 (en) 2005-05-06
WO2005041259A3 true WO2005041259A3 (en) 2007-05-10

Family

ID=34526621

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/031055 WO2005041259A2 (en) 2003-10-17 2004-09-22 A system-level test architecture for delivery of compressed tests

Country Status (2)

Country Link
US (1) US7278123B2 (en)
WO (1) WO2005041259A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7590905B2 (en) * 2004-05-24 2009-09-15 Syntest Technologies, Inc. Method and apparatus for pipelined scan compression
US7487419B2 (en) 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
US7415678B2 (en) * 2005-11-15 2008-08-19 Synopsys, Inc. Method and apparatus for synthesis of multimode X-tolerant compressor
US20070266283A1 (en) * 2006-05-01 2007-11-15 Nec Laboratories America, Inc. Method and Apparatus for Testing an Integrated Circuit
FR2906656A1 (en) * 2006-10-03 2008-04-04 France Telecom Decided signal decoding method for transmission system`s receiver, involves providing word of binary elements having decoded signal from allowable word, where distance considers relative reliabilities of specific sequences of elements
US20080127006A1 (en) * 2006-10-27 2008-05-29 International Business Machines Corporation Real-Time Data Stream Decompressor
US20090287438A1 (en) * 2007-12-14 2009-11-19 Wu-Tung Cheng Increased Fault Diagnosis Throughput Using Dictionaries For Hyperactive Faults
US7958472B2 (en) * 2008-09-30 2011-06-07 Synopsys, Inc. Increasing scan compression by using X-chains
US8990633B2 (en) * 2009-04-21 2015-03-24 Freescale Semiconductor, Inc. Tracing support for interconnect fabric
US8108742B2 (en) * 2009-06-11 2012-01-31 Texas Instruments Incorporated Tap control of TCA scan clock and scan enable
US8112685B2 (en) 2009-06-11 2012-02-07 Texas Instruments Incorporated Serial compressed data I/O in a parallel test compression architecture
US10345369B2 (en) 2012-10-02 2019-07-09 Synopsys, Inc. Augmented power-aware decompressor
US10394846B2 (en) * 2015-08-25 2019-08-27 International Business Machines Corporation Heterogeneous compression in replicated storage
US10380303B2 (en) 2015-11-30 2019-08-13 Synopsys, Inc. Power-aware dynamic encoding
CN105629155B (en) * 2015-12-28 2018-08-17 中国科学院声学研究所 A kind of dictionary coding method of test data
JP7150676B2 (en) * 2019-09-02 2022-10-11 株式会社東芝 Semiconductor integrated circuit and its test method
US11513818B1 (en) * 2020-09-30 2022-11-29 Cadence Design Systems, Inc. Method, product, and system for integrating a hardware accelerator with an extensible processor

Citations (1)

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Publication number Priority date Publication date Assignee Title
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment

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DE4305442C2 (en) * 1993-02-23 1999-08-05 Hewlett Packard Gmbh Method and device for generating a test vector
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
GB9623215D0 (en) * 1996-11-07 1997-01-08 Process Insight Limited Solid state memory test system with defect compression
JP4077578B2 (en) * 1999-04-30 2008-04-16 松下電器産業株式会社 Integrated circuit device design method
US6238937B1 (en) * 1999-09-08 2001-05-29 Advanced Micro Devices, Inc. Determining endpoint in etching processes using principal components analysis of optical emission spectra with thresholding
WO2001039254A2 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US6560756B1 (en) * 2001-07-02 2003-05-06 Ltx Corporation Method and apparatus for distributed test pattern decompression

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment

Also Published As

Publication number Publication date
WO2005041259A2 (en) 2005-05-06
US20050097413A1 (en) 2005-05-05
US7278123B2 (en) 2007-10-02

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