WO2005043299A3 - Method and apparatus for a variable processing period in an integrated circuit - Google Patents

Method and apparatus for a variable processing period in an integrated circuit Download PDF

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Publication number
WO2005043299A3
WO2005043299A3 PCT/US2004/034429 US2004034429W WO2005043299A3 WO 2005043299 A3 WO2005043299 A3 WO 2005043299A3 US 2004034429 W US2004034429 W US 2004034429W WO 2005043299 A3 WO2005043299 A3 WO 2005043299A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing circuit
integrated circuit
processing period
output
variable processing
Prior art date
Application number
PCT/US2004/034429
Other languages
French (fr)
Other versions
WO2005043299A2 (en
Inventor
Alain Vergnes
Original Assignee
Atmel Corp
Alain Vergnes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0312485A external-priority patent/FR2861474B1/en
Application filed by Atmel Corp, Alain Vergnes filed Critical Atmel Corp
Priority to EP04795572A priority Critical patent/EP1676192A4/en
Publication of WO2005043299A2 publication Critical patent/WO2005043299A2/en
Publication of WO2005043299A3 publication Critical patent/WO2005043299A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack

Abstract

The invention is a system for modifying the processing period in a digital logic module. The invention comprises the following. A processing circuit is configured to receive an input in order to create an output. A controller is coupled to the processing circuit and is configured to track L manipulations, wherein L is an integer. The controller is further configured to send a select signal to the processing circuit and to cause the processing circuit to manipulate the input over N clock cycles. N is an integer and N is less than or equal to L. N varies over the plurality of processing time periods. An output port is coupled to the processing circuit and is configured to convey the output.
PCT/US2004/034429 2003-10-24 2004-10-15 Method and apparatus for a variable processing period in an integrated circuit WO2005043299A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04795572A EP1676192A4 (en) 2003-10-24 2004-10-15 Method and apparatus for a variable processing period in an integrated circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0312485 2003-10-24
FR0312485A FR2861474B1 (en) 2003-10-24 2003-10-24 METHOD AND APPARATUS FOR A VARIABLE PROCESSING PERIOD IN AN INTEGRATED CIRCUIT
US10/861,682 US7661011B2 (en) 2003-10-24 2004-06-04 Method and apparatus for a variable processing period in an integrated circuit
US10/861,682 2004-06-04

Publications (2)

Publication Number Publication Date
WO2005043299A2 WO2005043299A2 (en) 2005-05-12
WO2005043299A3 true WO2005043299A3 (en) 2006-09-28

Family

ID=34553754

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/034429 WO2005043299A2 (en) 2003-10-24 2004-10-15 Method and apparatus for a variable processing period in an integrated circuit

Country Status (2)

Country Link
EP (1) EP1676192A4 (en)
WO (1) WO2005043299A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020054594A1 (en) * 2000-11-07 2002-05-09 Hoof Werner Van Non-blocking, multi-context pipelined processor
US20030043800A1 (en) * 2001-08-30 2003-03-06 Sonksen Bradley Stephen Dynamic data item processing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587044B2 (en) 1998-01-02 2009-09-08 Cryptography Research, Inc. Differential power analysis method and apparatus
ATE216518T1 (en) 1998-07-29 2002-05-15 Infineon Technologies Ag CLOCKED INTEGRATED SEMICONDUCTOR CIRCUIT AND METHOD FOR OPERATING SAME

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020054594A1 (en) * 2000-11-07 2002-05-09 Hoof Werner Van Non-blocking, multi-context pipelined processor
US20030043800A1 (en) * 2001-08-30 2003-03-06 Sonksen Bradley Stephen Dynamic data item processing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1676192A4 *

Also Published As

Publication number Publication date
WO2005043299A2 (en) 2005-05-12
EP1676192A2 (en) 2006-07-05
EP1676192A4 (en) 2008-12-10

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