WO2005048314A2 - Tapered dielectric and conductor structures and applications thereof - Google Patents

Tapered dielectric and conductor structures and applications thereof Download PDF

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Publication number
WO2005048314A2
WO2005048314A2 PCT/US2004/037757 US2004037757W WO2005048314A2 WO 2005048314 A2 WO2005048314 A2 WO 2005048314A2 US 2004037757 W US2004037757 W US 2004037757W WO 2005048314 A2 WO2005048314 A2 WO 2005048314A2
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WO
WIPO (PCT)
Prior art keywords
tapered
dielectric
integrated circuit
dielectric layer
pitch
Prior art date
Application number
PCT/US2004/037757
Other languages
French (fr)
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WO2005048314A3 (en
Inventor
C. Joseph Fjelstad
P. Kevin Grundy
K. Para Segaram
Gary Yasumura
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Silicon Pipe, Inc.
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Publication date
Application filed by Silicon Pipe, Inc. filed Critical Silicon Pipe, Inc.
Publication of WO2005048314A2 publication Critical patent/WO2005048314A2/en
Publication of WO2005048314A3 publication Critical patent/WO2005048314A3/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
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    • H01L2924/19039—Structure including wave guides being a hybrid line type impedance transition between different types of wave guides
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09154—Bevelled, chamferred or tapered edge
    • H—ELECTRICITY
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • the present invention relates to the field of high speed electronic interconnections and the packaging of semiconductor integrated circuits for use therewith.
  • microstrip and stripline interconnection paths are constructed to control the impedance and provide a measure of shielding. While these solutions have worked well for the industry for some years, as the electronics industry transitions into the gigahertz frequency due to the continuing advance of semiconductors processing, the old methods must be either replaced with new ones or the old methods must be modified to accommodate the changes needed. This is especially true as signals from the IC chip start out at a very fine pitch (i.e. circuit or contact width and spacing) and must from there graduate to the coarser pitches required for next level assembly.
  • transitions are normally characterized by junctions that are abrupt as the signal moves from one part of the interconnection chain to the next and, depending on the speed of the signal, these transitions can have profound effects on the signal integrity, manifest in the form of reflections and ringing in the circuit.
  • circuit speeds climb, there is need for new approaches to design of interconnections from the chip through the interconnection chain, which will provide relief from those current design features and elements that degrade circuit performance.
  • Figure 1 A-C shows top (i.e. conductor circuit side), cross sectional and perspective views of a cable embodiment
  • Figure 2 A & B provides first and second side views (i.e.
  • Figure 3 A, B & C provides circuit side and cross sectional views of a strip of IC packages embodiment with enlarged areas of detail provided for clarity;
  • Figure 4 provides a cross sectional view of an embodiment comprising strips of IC packages mounted to opposite sides of a section of next level interconnection substrate and illustrating, with dotted lines, a prospective flow of the signal;
  • Figure 5 A & B provides cross sectional views of embodiments that provide access to more than one layer of circuits within a structure.
  • a first objective of the present disclosure is to describe structures which provide uniform controlled impedance from one electronic device or element to another electronic device or element while the signal transitions from a fine pitch to a course pitch and back. It is a second objective of the disclosure to describe applications of the structures described in specific product embodiments where significant benefit or improvements in product performance can be gained.
  • the present embodiments offer novel alternative approaches to addressing and meeting the stated objective and solving the problems associated with current design approaches.
  • the conceptual structures comprise the use of any of a number of alternative embodiments of controlled impedance signal distribution structures from one device or element to a second device or element while the pitch (i.e. width and spacing) of the conductor is reduced or enlarged.
  • FIG. 1 A a top view of a circuit section 100 having a insulating dielectric base 101, which is desirably uniform in terms of its electrical properties (e.g., dielectric constant and loss tangent) and has conductors 102 disposed on its surface.
  • the individual circuit traces have different widths, Wi and W 2> , at their distal ends, with the width of the traces being reduced as the circuit traces transition through a tapering zone Z.
  • the width of dielectric is shown being also reduced in the illustration but this is not a requirement.
  • Figure IB shows a cross sectional view of IB wherein the circuit traces 102 are disposed on the first surface and a ground layer 103 resides on the»side opposite the circuit traces separated by an insulating dielectric material 101.
  • the dielectric material is shown having two different thicknesses T] and T 2j at the distal ends and a zone Z that is tapered in the same region where the insulating dielectric material is tapered to create the effect of uniform characteristic impedance as the circuit trace width and pitch is reduced.
  • Figure IC provides a perspective view of the circuit section and the elements of structure in a more clarified form.
  • the objectives can be also be accomplished by keeping the dielectric thickness constant and, in lieu of tapering the dielectric, having the ground metal layer become more physically diffuse with expanding open area to incrementally control capacitance as the circuit width expands, (i.e. having more or greater openings in the metal ground as the circuit on the opposite side transitions from lesser to greater width)
  • the objective could likewise be accomplished by having the dielectric become more diffuse (e.g. a filigree or sieve-like perforated metal of expanding percentage of open or free space area) to create a gradient dielectric constant in the material that trends from the relative dielectric constant value of the material toward a value of 1.
  • Such tapered structures could be created by molding of the dielectric followed by the creation of the conductor traces or, alternatively the dielectric material could be molded over the circuits on a second material.
  • Another alternative manufacturing method is to form the taper structure by deposition of the dielectric, such as by means of multiple layers of prefabricated or multiple layers of sequentially screen printed dielectric materials or by means of ink jet printing thin layers of dielectric materials onto a metal base to create the desired dielectric taper topography for the circuits.
  • FIG. 2 A provides an illustration of a first side of an embodiment useful for high speed testing, such as a high speed probe card 200.
  • circuit traces having straight and tapered portions along their length 202, are disposed on a dielectric material 201, which has an aperture in the center 204 for accessing a device under test.
  • the outer portion of the circular probe card, zone N has a constant dielectric thickness and trace width in this area is also constant. Both circuit width and dielectric thickness diminish in zone Z to provide uniform characteristic impedance along their length.
  • Figure 2B provides a view of the reverse side of the probe card revealing a full ground layer with a central aperture 204.
  • Figure 3 A & B provide circuit side and cross sectional views of a multi-chip package strip embodiment, such as might be used in a memory module application.
  • Figure 3C provides an enlarged view of an alternative structure and method of interconnection to the IC die. While the structure is shown as a multi-chip structure, it is clear that a single individual IC die could also be packaged with the attributes of those IC die within the packaged strip as shown.
  • Figure 3 A provides a circuit side view of a packaged strip 300, having IC chips 305 (shown in phantom outline as they are located on the back side) in any practical number.
  • the strip is comprised of an insulating base material 301 that has disposed on its surface parallel circuit traces 302 for critical signal transmission and discrete terminations 303, used for connection to power, ground and non critical signal terminations on a next level assembly (the next level assembly is not shown in this figure).
  • the ends of the strip package 309 are used for termination to the next level assembly.
  • An enlarged view of the terminations with encapsulant 304 removed reveals wires 306 bonded to both bond pads 307 on the chip 305 and the tapered ends of the circuit traces 302 A.
  • Figure 3B provides a cross section view of Figure 3A wherein the packaged strip 300 is shown on edge to provide more detail.
  • the insulating dielectric base material 301 has circuits 302 disposed on one side and a ground layer 303 on the second side.
  • IC chips 305 are bonded to the base material with its circuits and ground plane by means of an adhesive 308 and interconnections between the chip 305 and the circuits 302 is accomplished by wire bonds 306 and then protected with an encapsulant 304.
  • An enlarged view of a section of the assembly provides greater detail for clarity and shows a section of the material that is tapered 301 A beneath the tapered traces. 1
  • FIG. 4 illustrates a partial view of module embodiment 400 wherein package strips 300 are mounted to an interconnecting substrate 401 having interconnection vias, such as a memory module, as partially shown.
  • a memory controller/buffer chip 404 is interconnected to the interconnecting substrate 401 with solder balls 402 or other suitable interconnecting connecting medium. Solder balls or other interconnecting medium are also used to interconnect the package strips 300 to the interconnecting substrate 401. Additional lapped interconnections 403 are made between the packaging strip and the interconnecting substrate at the ends 409 by a suitable method such as soldering or by use of a conductive adhesive. In the figure is also shown a prospective routing path for the critical or high speed signals represented by the dotted line arrows 409.
  • strip packages could be stacked to increase memory density as well as speed if the I/O terminations for non-critical signals were moved to the gap between the chips while the ends are connected to a bus that controls their passage from different layers of packaged strips.
  • Figure 5 A and B illustrate other embodiments wherein more than one layer of tapered circuits (taper of circuit widths not shown) are stacked to increase local contact density.
  • Figure 5A is shown an embodiment of a multilayer circuit structure having tapered dielectric 500 A.
  • layers of insulation material 501 are interleaved with conductor signal layers 502 and ground layers 503.
  • the insulation tapers to a reduced thickness in zone Z and the signals egress from the substrate to be accessed for interconnection to mating elements in a stair step fashion at the ends 504 A and 504C which are accessed on the same side of the structure.
  • FIG. 5B is shown another embodiment of a multilayer circuit structure having tapered dielectric 500B.
  • layers of insulation material 501 are interleaved with conductor signal layers 502 and ground layers 503.
  • the insulation tapers to a reduced thickness in the zone Z and the signals egress from the substrate to be accessed for interconnection to mating elements in a stair step fashion at the ends 504B and 504C which are accessed on opposite sides of the structure.
  • the structures in Figure 5 indicate only two conductor signal lines routed in a straight line, it is clear based on the other structures disclosed in this document that many signal lines and many physical configurations (e.g.

Abstract

Disclosed are tapered dielectric and conductor structures (100) which provide controlled impedance interconnection while signal conductor lines (102) transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

Description

Tapered Dielectric and Conductor Structures and Applications Thereof
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority from, and hereby incorporates by reference, U.S. Provisional Application No. 60/519,545, filed November 12, 2003 and entitled: "Memory Package and Structures Created There From"
FIELD OF THE INVENTION
[0002] The present invention relates to the field of high speed electronic interconnections and the packaging of semiconductor integrated circuits for use therewith.
BACKGROUND
[0003] The overall performance of high speed electronic systems operating in the multi- gigabit per second range is ultimately dependant on the signal integrity of the transmitted data. The first steps in controlling signal integrity are made in the design of the circuit. Choices made in terms of circuit layout, the materials used and the general architecture of the complete assembly will all have impact on the quality of the transmitted electronic signal. One of the major concerns in maintaining signal integrity is to assure that the signal encounters as few parasitic effects and electrical discontinuities as possible. One solution would be to have all signals in an electronic system be made by means of coaxial cable connections to provide and maintain a fully shielded conductor path having unvarying characteristic impedance through its entire path. However, this solution is impractical and too expensive for most electronic products. In place of coaxial cables, microstrip and stripline interconnection paths are constructed to control the impedance and provide a measure of shielding. While these solutions have worked well for the industry for some years, as the electronics industry transitions into the gigahertz frequency due to the continuing advance of semiconductors processing, the old methods must be either replaced with new ones or the old methods must be modified to accommodate the changes needed. This is especially true as signals from the IC chip start out at a very fine pitch (i.e. circuit or contact width and spacing) and must from there graduate to the coarser pitches required for next level assembly. These transitions are normally characterized by junctions that are abrupt as the signal moves from one part of the interconnection chain to the next and, depending on the speed of the signal, these transitions can have profound effects on the signal integrity, manifest in the form of reflections and ringing in the circuit. Thus as circuit speeds climb, there is need for new approaches to design of interconnections from the chip through the interconnection chain, which will provide relief from those current design features and elements that degrade circuit performance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The present invention is best illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: Figure 1 A-C shows top (i.e. conductor circuit side), cross sectional and perspective views of a cable embodiment; Figure 2 A & B provides first and second side views (i.e. conductor circuit side and ground side) of a probe card embodiment; Figure 3 A, B & C provides circuit side and cross sectional views of a strip of IC packages embodiment with enlarged areas of detail provided for clarity; Figure 4 provides a cross sectional view of an embodiment comprising strips of IC packages mounted to opposite sides of a section of next level interconnection substrate and illustrating, with dotted lines, a prospective flow of the signal; and Figure 5 A & B provides cross sectional views of embodiments that provide access to more than one layer of circuits within a structure.
DETAILED DESCRIPTION
[0005] Disclosed herein are innovative structures for controlling the quality of an electronic signal that must transition from a fine pitch to a coarser, more useful pitch. An example is the pitch transition from IC chip to terminations on an IC package. Another example is pitch transition required from IC chip to an IC test system. The objective is accomplished by creating interconnection paths that simultaneously taper insulating substrate and signal line to effectively produce the desired characteristic impedance in the signal line in a manner that is unchanging as the signal transitions from a fine pitch to a coarser pitch. This structure is useful for a wide variety of applications from test and measurement to electronic system structures such as switches and routers to IC packages for a range of chips and applications from CPU chips to memory chips as well as for circuit structures that are used to interconnect them.
[0006] The embodiments herein disclosed address the limitations of current circumstances relative to the design and manufacturing practices employed in the fabrication of electronic device and system interconnections and the present inability of those design and manufacturing practices to address adequately and fully the needs for improved electronic signal integrity as it transitions from fine pitch to course pitch and back to fine pitch as required. Thus, a first objective of the present disclosure is to describe structures which provide uniform controlled impedance from one electronic device or element to another electronic device or element while the signal transitions from a fine pitch to a course pitch and back. It is a second objective of the disclosure to describe applications of the structures described in specific product embodiments where significant benefit or improvements in product performance can be gained. It is a third objective of this disclosure to describe prospective methods for the construction of tapered dielectric and tapered trace structures that provide a uniform characteristic impedance as traces transition from fine to coarse pitch. [0007] The present embodiments offer novel alternative approaches to addressing and meeting the stated objective and solving the problems associated with current design approaches. The conceptual structures comprise the use of any of a number of alternative embodiments of controlled impedance signal distribution structures from one device or element to a second device or element while the pitch (i.e. width and spacing) of the conductor is reduced or enlarged.
[0008] In Figure 1 A, B and C is shown an embodiment that accomplishes the objective of maintaining uniform characteristic impedance by simultaneously tapering, or incrementally stepping, both trace and dielectric in a common region. In Figure 1 A a top view of a circuit section 100 having a insulating dielectric base 101, which is desirably uniform in terms of its electrical properties (e.g., dielectric constant and loss tangent) and has conductors 102 disposed on its surface. The individual circuit traces have different widths, Wi and W2> , at their distal ends, with the width of the traces being reduced as the circuit traces transition through a tapering zone Z. The width of dielectric is shown being also reduced in the illustration but this is not a requirement. Continuing, Figure IB shows a cross sectional view of IB wherein the circuit traces 102 are disposed on the first surface and a ground layer 103 resides on the»side opposite the circuit traces separated by an insulating dielectric material 101. The dielectric material is shown having two different thicknesses T] and T2j at the distal ends and a zone Z that is tapered in the same region where the insulating dielectric material is tapered to create the effect of uniform characteristic impedance as the circuit trace width and pitch is reduced. Figure IC provides a perspective view of the circuit section and the elements of structure in a more clarified form. While this represents a preferred embodiment, the objectives can be also be accomplished by keeping the dielectric thickness constant and, in lieu of tapering the dielectric, having the ground metal layer become more physically diffuse with expanding open area to incrementally control capacitance as the circuit width expands, (i.e. having more or greater openings in the metal ground as the circuit on the opposite side transitions from lesser to greater width) The objective could likewise be accomplished by having the dielectric become more diffuse (e.g. a filigree or sieve-like perforated metal of expanding percentage of open or free space area) to create a gradient dielectric constant in the material that trends from the relative dielectric constant value of the material toward a value of 1.
[0009] Such tapered structures could be created by molding of the dielectric followed by the creation of the conductor traces or, alternatively the dielectric material could be molded over the circuits on a second material. Another alternative manufacturing method is to form the taper structure by deposition of the dielectric, such as by means of multiple layers of prefabricated or multiple layers of sequentially screen printed dielectric materials or by means of ink jet printing thin layers of dielectric materials onto a metal base to create the desired dielectric taper topography for the circuits.
[0010] Figure 2 A provides an illustration of a first side of an embodiment useful for high speed testing, such as a high speed probe card 200. In the figure, circuit traces, having straight and tapered portions along their length 202, are disposed on a dielectric material 201, which has an aperture in the center 204 for accessing a device under test. The outer portion of the circular probe card, zone N, has a constant dielectric thickness and trace width in this area is also constant. Both circuit width and dielectric thickness diminish in zone Z to provide uniform characteristic impedance along their length. Figure 2B provides a view of the reverse side of the probe card revealing a full ground layer with a central aperture 204. [0011] Figure 3 A & B provide circuit side and cross sectional views of a multi-chip package strip embodiment, such as might be used in a memory module application. Figure 3C provides an enlarged view of an alternative structure and method of interconnection to the IC die. While the structure is shown as a multi-chip structure, it is clear that a single individual IC die could also be packaged with the attributes of those IC die within the packaged strip as shown. [0012] Figure 3 A provides a circuit side view of a packaged strip 300, having IC chips 305 (shown in phantom outline as they are located on the back side) in any practical number. The strip is comprised of an insulating base material 301 that has disposed on its surface parallel circuit traces 302 for critical signal transmission and discrete terminations 303, used for connection to power, ground and non critical signal terminations on a next level assembly (the next level assembly is not shown in this figure). The ends of the strip package 309 are used for termination to the next level assembly. An enlarged view of the terminations with encapsulant 304 removed reveals wires 306 bonded to both bond pads 307 on the chip 305 and the tapered ends of the circuit traces 302 A.
[0013] Figure 3B provides a cross section view of Figure 3A wherein the packaged strip 300 is shown on edge to provide more detail. The insulating dielectric base material 301 has circuits 302 disposed on one side and a ground layer 303 on the second side. IC chips 305 are bonded to the base material with its circuits and ground plane by means of an adhesive 308 and interconnections between the chip 305 and the circuits 302 is accomplished by wire bonds 306 and then protected with an encapsulant 304. An enlarged view of a section of the assembly provides greater detail for clarity and shows a section of the material that is tapered 301 A beneath the tapered traces. 1
[0014] While the structures are shown with wire bonds being made to two rows of bond pads, the structure is not so limited and could also be created using a single bond pad in the center or at the edges of the IC chip. For a center bond pad structure as illustrated in Figure 3C, a common lead 310 could be down bonded or soldered to the central bond 311 pad and be unbroken. Moreover, the tapering structure could also fan away from a peripherally leaded device in a manner similar to current BGA or QFP IC packages. [0015] Figure 4 illustrates a partial view of module embodiment 400 wherein package strips 300 are mounted to an interconnecting substrate 401 having interconnection vias, such as a memory module, as partially shown. In the figure, a memory controller/buffer chip 404 is interconnected to the interconnecting substrate 401 with solder balls 402 or other suitable interconnecting connecting medium. Solder balls or other interconnecting medium are also used to interconnect the package strips 300 to the interconnecting substrate 401. Additional lapped interconnections 403 are made between the packaging strip and the interconnecting substrate at the ends 409 by a suitable method such as soldering or by use of a conductive adhesive. In the figure is also shown a prospective routing path for the critical or high speed signals represented by the dotted line arrows 409. While not shown in the drawing, it is evident that the strip packages could be stacked to increase memory density as well as speed if the I/O terminations for non-critical signals were moved to the gap between the chips while the ends are connected to a bus that controls their passage from different layers of packaged strips.
[0016] Figure 5 A and B illustrate other embodiments wherein more than one layer of tapered circuits (taper of circuit widths not shown) are stacked to increase local contact density. In Figure 5A is shown an embodiment of a multilayer circuit structure having tapered dielectric 500 A. In the figure, layers of insulation material 501 are interleaved with conductor signal layers 502 and ground layers 503. The insulation tapers to a reduced thickness in zone Z and the signals egress from the substrate to be accessed for interconnection to mating elements in a stair step fashion at the ends 504 A and 504C which are accessed on the same side of the structure.
[0017] In Figure 5B is shown another embodiment of a multilayer circuit structure having tapered dielectric 500B. In the figure, layers of insulation material 501 are interleaved with conductor signal layers 502 and ground layers 503. The insulation tapers to a reduced thickness in the zone Z and the signals egress from the substrate to be accessed for interconnection to mating elements in a stair step fashion at the ends 504B and 504C which are accessed on opposite sides of the structure. [0018] While the structures in Figure 5 indicate only two conductor signal lines routed in a straight line, it is clear based on the other structures disclosed in this document that many signal lines and many physical configurations (e.g. round, rectangular, triangular, etc.) and that many different step configurations accessing different conductors at different layers are possible. It is also possible within the embodiments shown to integrate, when desired or advantageous, various active and passive electronic elements to enhance or further improve the performance of a system employing the invention. Finally, it is clear that the benefits of the tapered conductor and dielectric and like structures which provide a consistent value of characteristic impedance as signal lines transition from wide to narrow are suitable as interconnection substrates for the assembly of components.
[0019] Although the invention has been described briefly with reference to specific exemplary embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS What is claimed is:
1. An electronic interconnection structure to provide a controlled characteristic impedance for signal conductors that converge from a coarser pitch to a finer pitch comprising: a first dielectric layer having a tapered thickness; a first signal conductor disposed on a first surface of the first dielectric layer and having a tapered width; and a first conductive grounding layer disposed on a surface of the first dielectric layer opposite the first surface.
2. The electronic interconnection structure of Claim 1 wherein the first signal conductor is tapered to a progressively narrower width over a region of the first dielectric layer that tapers to a progressively narrower thickness to provide a substantially uniform characteristic impedance along the length of the first signal conductor.
3. The electronic interconnection structure of Claim 1 further comprising a second dielectric layer having a tapered thickness and having a first surface disposed adjacent the first surface of the first dielectric layer to sandwich the first signal conductor therebetween.
4. The electronic interconnection structure of claim 1 further comprising a second grounding layer disposed on a second surface of the second dielectric layer, the second surface of the second dielectric layer being opposite the first surface of the second dielectric layer.
5. The electronic interconnection structure of claim 4 further comprising: a third dielectric layer having a tapered thickness and having a first surface disposed adjacent the second surface of the second dielectric layer to sandwich the second grounding layer therebetween; and a second signal conductor having a tapered width and disposed on a surface of the third dielectric layer opposite the first surface of the third dielectric layer.
6. The electronic interconnection structure of claim 5 wherein each of the first and second signal conductors is exposed at both ends of the electronic interconnection structure..
7. An integrated circuit packaging assembly comprising: a first integrated circuit die; a dielectric substrate having at least one region of tapered dielectric material; a tapered signal conductor disposed on the dielectric substrate and extending, across the region of tapered dielectric material, from a narrow-pitch termination at the first integrated circuit die to a coarser pitch termination.
8. The integrated circuit packaging assembly of claim 7 further comprising a package housing, and wherein the coarser pitch termination is disposed adjacent an outer surface of the package housing.
9. The integrated circuit packaging assembly of claim 7 wherein the tapered signal conductor exhibits a substantially uniform characteristic impedance over its length.
10. The integrated circuit package assembly of Claim 7 wherein the assembly comprises a strip of interconnected integrated circuit devices, the integrated circuit devices including the first integrated circuit die.
11. The integrated circuit package assembly of Claim 7 wherein the assembly comprises a strip of interconnected integrated circuit memory devices, the integrated circuit memory devices including the first integrated circuit die.
12. The integrated circuit package assembly of claim 7 wherein at least one of the tapered signal conductor and the region of tapered dielectric material is stepwise tapered.
13. A method of manufacturing a substrate for a confroUed-impedance electronic interconnection structure that provides substantially uniform controlled characteristic impedance for circuits, the method comprising selective layering of dielectric material by dispensing to create a dielectric having a tapered topography.
14. The method of claim 13 wherein dispensing to create a dielectric having a tapered topography comprises dispensing the dielectric material with an ink jet.
15. A method of manufacturing a substrate for a confroUed-impedance electronic interconnection structure that provides a substantially uniform characteristic impedance for circuits, the method comprising sequentially stenciling layers of dielectric material to create a dielectric having a tapered topography.
16. A controlled impedance test structure comprising: a dielectric substrate having at least one area of tapered dielectric; and at least one tapered signal conductor disposed on the tapered dielectric, wherein said dielectric substrate and at least one tapered signal conductor constitute a test connection that extends between a narrow-pitch termination and a coarser-pitch termination and exhibits substantially uniform characteristic impedance from the narrow-pitch termination to the coarser-pitch termination.
17. The test structure of Claim 16 where the test structure is a probe card.
PCT/US2004/037757 2003-11-12 2004-11-12 Tapered dielectric and conductor structures and applications thereof WO2005048314A2 (en)

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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291923B1 (en) * 2003-07-24 2007-11-06 Xilinx, Inc. Tapered signal lines
WO2005048314A2 (en) * 2003-11-12 2005-05-26 Silicon Pipe, Inc. Tapered dielectric and conductor structures and applications thereof
US7466021B2 (en) * 2003-11-17 2008-12-16 Interconnect Portfolio, Llp Memory packages having stair step interconnection layers
US20110298567A1 (en) * 2004-09-24 2011-12-08 Oracle America, Inc., formerly known as Sun Microsystems, Inc. System and method for constant characteristic impedance in a flexible trace interconnect array
JP2007129018A (en) 2005-11-02 2007-05-24 Nec Electronics Corp Semiconductor device
US8026600B2 (en) * 2008-01-02 2011-09-27 Samsung Electronics Co., Ltd. Controlled impedance structures for high density interconnections
US8022861B2 (en) * 2008-04-04 2011-09-20 Toyota Motor Engineering & Manufacturing North America, Inc. Dual-band antenna array and RF front-end for mm-wave imager and radar
US7733265B2 (en) * 2008-04-04 2010-06-08 Toyota Motor Engineering & Manufacturing North America, Inc. Three dimensional integrated automotive radars and methods of manufacturing the same
US7830301B2 (en) * 2008-04-04 2010-11-09 Toyota Motor Engineering & Manufacturing North America, Inc. Dual-band antenna array and RF front-end for automotive radars
US7990237B2 (en) * 2009-01-16 2011-08-02 Toyota Motor Engineering & Manufacturing North America, Inc. System and method for improving performance of coplanar waveguide bends at mm-wave frequencies
US8786496B2 (en) 2010-07-28 2014-07-22 Toyota Motor Engineering & Manufacturing North America, Inc. Three-dimensional array antenna on a substrate with enhanced backlobe suppression for mm-wave automotive applications
US8916996B2 (en) * 2011-07-29 2014-12-23 General Electric Company Electrical distribution system
US9053279B2 (en) 2013-03-14 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Pattern modification with a preferred position function
US20140320364A1 (en) * 2013-04-26 2014-10-30 Research In Motion Limited Substrate integrated waveguide horn antenna
US20160266737A1 (en) * 2015-03-13 2016-09-15 International Business Machines Corporation Calendar-based social network engagement
US9490518B1 (en) * 2015-09-28 2016-11-08 Texas Instruments Incorporated System for launching a signal into a dielectric waveguide
US10027010B2 (en) * 2015-11-17 2018-07-17 United Arab Emirates University Printed circuit board structure and method of manufacturing using wideband microstrip lines
US9966180B2 (en) 2016-01-22 2018-05-08 Raytheon Company Impedance transformer
US20170288290A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Electrical cable
JP6983688B2 (en) * 2018-02-05 2021-12-17 日本メクトロン株式会社 Flexible printed wiring board for catheters and its manufacturing method
CN111697300A (en) * 2020-05-13 2020-09-22 中国科学院上海微系统与信息技术研究所 Multi-channel transmission structure for low-temperature interconnection and transmission line

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017397A1 (en) * 2000-06-26 2002-02-14 Ramey Samuel C. Vialess printed circuit board
US20020119584A1 (en) * 1999-07-21 2002-08-29 E Ink Corporation Preferred methods for producing electrical circuit elements used to control an electronic display
US20040012458A1 (en) * 2002-07-19 2004-01-22 Amparan Alfonso Benjamin Device interconnects and methods of making the same

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE534739A (en) * 1954-01-14
US2979676A (en) * 1957-10-30 1961-04-11 Research Corp Waveguide to microstrip transition structure
US3419813A (en) * 1967-06-22 1968-12-31 Rca Corp Wide-band transistor power amplifier using a short impedance matching section
US4048589A (en) * 1975-06-30 1977-09-13 Epsilon Lambda Electronics Corporation Receiver module and components thereof
US4072902A (en) * 1975-06-30 1978-02-07 Epsilon Lambda Electronics Corp. Receiver module and mixer thereof
US4125810A (en) * 1977-04-08 1978-11-14 Vari-L Company, Inc. Broadband high frequency baluns and mixer
JPS5772349A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor integrated circuit device
US4514751A (en) * 1982-12-23 1985-04-30 International Business Machines Corporation Compressively stresses titanium metallurgy for contacting passivated semiconductor devices
JPS6010645A (en) * 1983-06-30 1985-01-19 Toshiba Corp Resin-sealed semiconductor device
DE3343367A1 (en) * 1983-11-30 1985-06-05 Siemens AG, 1000 Berlin und 8000 München SEMICONDUCTOR COMPONENT WITH HUMPER-LIKE, METAL CONNECTION CONTACTS AND MULTIPLE-WIRE WIRING
US4697143A (en) * 1984-04-30 1987-09-29 Cascade Microtech, Inc. Wafer probe
JPS62269349A (en) * 1986-05-19 1987-11-21 Nec Corp Semiconductor device
US4827211A (en) * 1987-01-30 1989-05-02 Cascade Microtech, Inc. Wafer probe
US4745377A (en) * 1987-06-08 1988-05-17 The United States Of America As Represented By The Secretary Of The Army Microstrip to dielectric waveguide transition
US4894612A (en) * 1987-08-13 1990-01-16 Hypres, Incorporated Soft probe for providing high speed on-wafer connections to a circuit
US4862120A (en) * 1988-02-29 1989-08-29 Canadian Patents And Development Limited/Societe Canadienne Des Brevets Et D'exploitation Limitee Wideband stripline to microstrip transition
US4806886A (en) * 1988-03-01 1989-02-21 The United States Of America As Represented By The Secretary Of The Army Microstrip resonance isolator
JP2601867B2 (en) * 1988-03-31 1997-04-16 株式会社東芝 Semiconductor integrated circuit mounting substrate, method of manufacturing the same, and semiconductor integrated circuit device
JPH0274039A (en) * 1988-09-09 1990-03-14 Texas Instr Japan Ltd Electronic circuit device
US5170138A (en) * 1989-03-30 1992-12-08 Electromagnetic Sciences, Inc. Single toroid hybrid mode RF phase shifter
US5075648A (en) * 1989-03-30 1991-12-24 Electromagnetic Sciences, Inc. Hybrid mode rf phase shifter and variable power divider using the same
US5107231A (en) * 1989-05-25 1992-04-21 Epsilon Lambda Electronics Corp. Dielectric waveguide to TEM transmission line signal launcher
BR8906400A (en) * 1989-12-07 1991-06-11 Brasilia Telecom IMPEDANCES CASER COUPLER
JPH04116827A (en) * 1990-09-06 1992-04-17 Mitsubishi Electric Corp Semiconductor device
US5119048A (en) * 1990-11-05 1992-06-02 Grunwell Randall L Pseudo tapered lines using modified ground planes
US5289036A (en) * 1991-01-22 1994-02-22 Nec Corporation Resin sealed semiconductor integrated circuit
US5140288A (en) * 1991-04-08 1992-08-18 Motorola, Inc. Wide band transmission line impedance matching transformer
US5172082A (en) * 1991-04-19 1992-12-15 Hughes Aircraft Company Multi-octave bandwidth balun
JP3004083B2 (en) * 1991-06-21 2000-01-31 沖電気工業株式会社 Semiconductor device and its manufacturing apparatus
US5160904A (en) * 1991-11-07 1992-11-03 The United States Of America As Represented By The Secretary Of The Army Microstrip circuit with transition for different dielectric materials
US5155352A (en) * 1991-11-25 1992-10-13 The United States Of America As Represented By The Secretary Of The Army Optically activated sub-nanosecond hybrid pulser
US5280168A (en) * 1991-11-25 1994-01-18 The United States Of America As Represented By The Secretary Of The Army Tapered radial transmission line for an optically activated hybrid pulser
US5173666A (en) * 1992-03-27 1992-12-22 The United States Of America As Represented By The Secretary Of The Army Microstrip-to-inverted-microstrip transition
US5225797A (en) * 1992-04-27 1993-07-06 Cornell Research Foundation, Inc. Dielectric waveguide-to-coplanar transmission line transitions
US5177456A (en) * 1992-05-22 1993-01-05 The United States Of America As Represented By The Secretary Of The Army Microstrip ferrite circulator for substrate transitioning
US5382831A (en) * 1992-12-14 1995-01-17 Digital Equipment Corporation Integrated circuit metal film interconnect having enhanced resistance to electromigration
US5470788A (en) * 1994-02-28 1995-11-28 International Business Machines Corporation Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration
US5461260A (en) * 1994-08-01 1995-10-24 Motorola Inc. Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density
JPH08293523A (en) * 1995-02-21 1996-11-05 Seiko Epson Corp Semiconductor device and its manufacture
US5672889A (en) * 1995-03-15 1997-09-30 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5576671A (en) * 1995-04-24 1996-11-19 Motorola, Inc. Method and apparatus for power combining/dividing
WO1997004495A1 (en) * 1995-07-18 1997-02-06 General Atomics Microwave vacuum window having wide bandwidth
US5712510A (en) * 1995-08-04 1998-01-27 Advanced Micro Devices, Inc. Reduced electromigration interconnection line
US5689139A (en) * 1995-09-11 1997-11-18 Advanced Micro Devices, Inc. Enhanced electromigration lifetime of metal interconnection lines
KR100299338B1 (en) * 1996-04-19 2001-10-19 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device
JPH09289404A (en) * 1996-04-24 1997-11-04 Honda Motor Co Ltd Ribbon,bonding wire, and package for microwave circuit
KR100215847B1 (en) * 1996-05-16 1999-08-16 구본준 Metal interconnector of semiconductor device and process for forming the same
SE511377C2 (en) * 1996-12-19 1999-09-20 Ericsson Telefon Ab L M via structure
US5818315A (en) * 1996-12-31 1998-10-06 Lucent Technologies Inc. Signal trace impedance control using a grid-like ground plane
JP3500268B2 (en) * 1997-02-27 2004-02-23 京セラ株式会社 High frequency input / output terminal and high frequency semiconductor element storage package using the same
US6198284B1 (en) * 1997-04-14 2001-03-06 Doty Scientific Inc. High power flexible leads for DAS NMR
EP0877443B1 (en) * 1997-05-09 2008-01-02 Nippon Telegraph And Telephone Corporation Antenna and manufacturing method therefor
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
JP3500308B2 (en) * 1997-08-13 2004-02-23 インターナショナル・ビジネス・マシーンズ・コーポレーション Integrated circuit
US6100853A (en) * 1997-09-10 2000-08-08 Hughes Electronics Corporation Receiver/transmitter system including a planar waveguide-to-stripline adapter
US5969421A (en) * 1997-11-18 1999-10-19 Lucent Technologies Inc. Integrated circuit conductors that avoid current crowding
JP3498597B2 (en) * 1998-10-22 2004-02-16 株式会社村田製作所 Dielectric line conversion structure, dielectric line device, directional coupler, high frequency circuit module, and transmission / reception device
US6420884B1 (en) * 1999-01-29 2002-07-16 Advantest Corp. Contact structure formed by photolithography process
US6191481B1 (en) * 1998-12-18 2001-02-20 Philips Electronics North America Corp. Electromigration impeding composite metallization lines and methods for making the same
FI106414B (en) * 1999-02-02 2001-01-31 Nokia Networks Oy Broadband impedance adapter
JP3464933B2 (en) * 1999-03-25 2003-11-10 Ｎｅｃエレクトロニクス株式会社 Semiconductor wiring evaluation system
JP2000294639A (en) * 1999-04-09 2000-10-20 Oki Electric Ind Co Ltd Semiconductor device
US6426686B1 (en) * 1999-06-16 2002-07-30 Microsubstrates Corporation Microwave circuit packages having a reduced number of vias in the substrate
US6518663B1 (en) * 1999-08-30 2003-02-11 Texas Instruments Incorporated Constant impedance routing for high performance integrated circuit packaging
JP3776666B2 (en) * 2000-02-25 2006-05-17 沖電気工業株式会社 Semiconductor device
JP2002016065A (en) * 2000-06-29 2002-01-18 Toshiba Corp Semiconductor device
DE20114544U1 (en) * 2000-12-04 2002-02-21 Cascade Microtech Inc wafer probe
US6624718B2 (en) * 2000-12-14 2003-09-23 Intel Corporation Signal transmission unit
JP4349742B2 (en) * 2000-12-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 Circuit design apparatus and circuit design method
US6624729B2 (en) * 2000-12-29 2003-09-23 Hewlett-Packard Development Company, L.P. Slotted ground plane for controlling the impedance of high speed signals on a printed circuit board
US6882761B2 (en) * 2001-01-22 2005-04-19 The Furukawa Electric Co., Ltd. Silicon platform for optical modules
US6556099B2 (en) * 2001-01-25 2003-04-29 Motorola, Inc. Multilayered tapered transmission line, device and method for making the same
JP4515003B2 (en) * 2001-09-05 2010-07-28 富士通セミコンダクター株式会社 Semiconductor device
US6525631B1 (en) * 2001-09-21 2003-02-25 Anritsu Company System and method for improved microstrip termination
US6660174B2 (en) * 2001-09-21 2003-12-09 Anritsu Company Method of manufacturing a microstrip edge ground termination
US6876085B1 (en) * 2001-09-24 2005-04-05 Nortel Networks Limited Signal layer interconnect using tapered traces
US6995710B2 (en) * 2001-10-09 2006-02-07 Ngk Spark Plug Co., Ltd. Dielectric antenna for high frequency wireless communication apparatus
JP3936858B2 (en) * 2001-11-01 2007-06-27 日本オプネクスト株式会社 Light modulator
US6566758B1 (en) * 2001-11-27 2003-05-20 Sun Microsystems, Inc. Current crowding reduction technique for flip chip package technology
US20030122258A1 (en) * 2001-12-28 2003-07-03 Sudhakar Bobba Current crowding reduction technique using slots
US6897563B2 (en) * 2001-12-28 2005-05-24 Sun Microsystems, Inc. Current crowding reduction technique using selective current injection
US6770822B2 (en) * 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
JP2005525684A (en) * 2002-05-10 2005-08-25 モレックス　インコーポレーテッド Edge card connector assembly with terminals with adjusted impedance
US6700207B2 (en) * 2002-08-05 2004-03-02 Lsi Logic Corporation Flip-chip ball grid array package for electromigration testing
JP3580803B2 (en) * 2002-08-09 2004-10-27 沖電気工業株式会社 Semiconductor device
US6940108B2 (en) * 2002-12-05 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Slot design for metal interconnects
US6832029B2 (en) * 2002-12-17 2004-12-14 Mcnc Impedance control devices for use in the transition regions of electromagnetic and optical circuitry and methods for using the same
US6906406B2 (en) * 2002-12-19 2005-06-14 Freescale Semiconductor, Inc. Multiple dice package
US6818996B2 (en) * 2002-12-20 2004-11-16 Lsi Logic Corporation Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps
JP2004241680A (en) * 2003-02-07 2004-08-26 Mitsubishi Electric Corp Multilayer printed circuit board
WO2004079855A1 (en) * 2003-03-07 2004-09-16 Ericsson Telecomunicações S.A. Impedance-matching coupler
US7057404B2 (en) * 2003-05-23 2006-06-06 Sharp Laboratories Of America, Inc. Shielded probe for testing a device under test
US7065721B2 (en) * 2003-07-28 2006-06-20 Lsi Logic Corporation Optimized bond out method for flip chip wafers
WO2005048314A2 (en) * 2003-11-12 2005-05-26 Silicon Pipe, Inc. Tapered dielectric and conductor structures and applications thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020119584A1 (en) * 1999-07-21 2002-08-29 E Ink Corporation Preferred methods for producing electrical circuit elements used to control an electronic display
US20020017397A1 (en) * 2000-06-26 2002-02-14 Ramey Samuel C. Vialess printed circuit board
US20040012458A1 (en) * 2002-07-19 2004-01-22 Amparan Alfonso Benjamin Device interconnects and methods of making the same

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US7388279B2 (en) 2008-06-17
US7973391B2 (en) 2011-07-05
WO2005048314A3 (en) 2008-12-18
US20050133922A1 (en) 2005-06-23
US20090027137A1 (en) 2009-01-29

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