WO2005050448A3 - Early crc delivery for partial frame - Google Patents

Early crc delivery for partial frame Download PDF

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Publication number
WO2005050448A3
WO2005050448A3 PCT/US2004/036966 US2004036966W WO2005050448A3 WO 2005050448 A3 WO2005050448 A3 WO 2005050448A3 US 2004036966 W US2004036966 W US 2004036966W WO 2005050448 A3 WO2005050448 A3 WO 2005050448A3
Authority
WO
WIPO (PCT)
Prior art keywords
frame
partial frame
early crc
delivery
crc delivery
Prior art date
Application number
PCT/US2004/036966
Other languages
French (fr)
Other versions
WO2005050448A2 (en
Inventor
Pete Vogt
Original Assignee
Intel Corp
Pete Vogt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Pete Vogt filed Critical Intel Corp
Priority to EP04810428A priority Critical patent/EP1683017A2/en
Priority to JP2006539675A priority patent/JP4331756B2/en
Publication of WO2005050448A2 publication Critical patent/WO2005050448A2/en
Publication of WO2005050448A3 publication Critical patent/WO2005050448A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Abstract

Memory apparatus and methods transmit and receive a CRC code for a first portion of a frame before the second portion of the frame is finished being transferred. The CRC may be used to check the first portion of the frame before the second portion of the frame is completely received. A command or other information in the first portion of the frame may be used without waiting for the rest of the frame. Other embodiments are described and claimed.
PCT/US2004/036966 2003-11-14 2004-11-05 Early crc delivery for partial frame WO2005050448A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04810428A EP1683017A2 (en) 2003-11-14 2004-11-05 Early crc delivery for partial frame
JP2006539675A JP4331756B2 (en) 2003-11-14 2004-11-05 Early CRC supply for some frames

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/714,025 US7219294B2 (en) 2003-11-14 2003-11-14 Early CRC delivery for partial frame
US10/714,025 2003-11-14

Publications (2)

Publication Number Publication Date
WO2005050448A2 WO2005050448A2 (en) 2005-06-02
WO2005050448A3 true WO2005050448A3 (en) 2005-07-28

Family

ID=34573868

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/036966 WO2005050448A2 (en) 2003-11-14 2004-11-05 Early crc delivery for partial frame

Country Status (6)

Country Link
US (1) US7219294B2 (en)
EP (1) EP1683017A2 (en)
JP (1) JP4331756B2 (en)
CN (1) CN100498724C (en)
TW (1) TWI265525B (en)
WO (1) WO2005050448A2 (en)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6760772B2 (en) 2000-12-15 2004-07-06 Qualcomm, Inc. Generating and implementing a communication protocol and interface for high data rate signal transfer
US8812706B1 (en) 2001-09-06 2014-08-19 Qualcomm Incorporated Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system
US7362697B2 (en) 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
KR101168839B1 (en) 2003-06-02 2012-07-26 퀄컴 인코포레이티드 Generating and implementing a signal protocol and interface for higher data rates
US7200787B2 (en) * 2003-06-03 2007-04-03 Intel Corporation Memory channel utilizing permuting status patterns
US8171331B2 (en) 2003-06-04 2012-05-01 Intel Corporation Memory channel having deskew separate from redrive
US7386768B2 (en) * 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
KR101178080B1 (en) 2003-08-13 2012-08-30 퀄컴 인코포레이티드 A signal interface for higher data rates
KR100951158B1 (en) 2003-09-10 2010-04-06 콸콤 인코포레이티드 High data rate interface
US8694652B2 (en) 2003-10-15 2014-04-08 Qualcomm Incorporated Method, system and computer program for adding a field to a client capability packet sent from a client to a host
CN1902880A (en) 2003-10-29 2007-01-24 高通股份有限公司 High data rate interface
CN101729205A (en) 2003-11-12 2010-06-09 高通股份有限公司 High data rate interface with improved link control
BRPI0416895A (en) 2003-11-25 2007-03-06 Qualcomm Inc High data rate interface with enhanced link synchronization
EP2247072B1 (en) 2003-12-08 2013-09-25 QUALCOMM Incorporated High data rate interface with improved link synchronization
US20050138267A1 (en) * 2003-12-23 2005-06-23 Bains Kuljit S. Integral memory buffer and serial presence detect capability for fully-buffered memory modules
WO2005088939A1 (en) 2004-03-10 2005-09-22 Qualcomm Incorporated High data rate interface apparatus and method
JP4519903B2 (en) 2004-03-17 2010-08-04 クゥアルコム・インコーポレイテッド High speed data rate interface apparatus and method
KR101019935B1 (en) 2004-03-24 2011-03-09 퀄컴 인코포레이티드 High data rate interface apparatus and method
DE102004044785A1 (en) * 2004-04-10 2005-10-27 Leica Microsystems Semiconductor Gmbh Apparatus and method for determining positioning coordinates for semiconductor substrates
US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
EP1978692B1 (en) 2004-06-04 2011-07-27 QUALCOMM Incorporated High data rate interface apparatus and method
US8539119B2 (en) * 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
US8723705B2 (en) * 2004-11-24 2014-05-13 Qualcomm Incorporated Low output skew double data rate serial encoder
US8667363B2 (en) * 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US20060161691A1 (en) * 2004-11-24 2006-07-20 Behnam Katibian Methods and systems for synchronous execution of commands across a communication link
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US7417883B2 (en) * 2004-12-30 2008-08-26 Intel Corporation I/O data interconnect reuse as repeater
US7366931B2 (en) 2004-12-30 2008-04-29 Intel Corporation Memory modules that receive clock information and are placed in a low power state
US7577151B2 (en) 2005-04-01 2009-08-18 International Business Machines Corporation Method and apparatus for providing a network connection table
US7697536B2 (en) * 2005-04-01 2010-04-13 International Business Machines Corporation Network communications for operating system partitions
US7508771B2 (en) * 2005-04-01 2009-03-24 International Business Machines Corporation Method for reducing latency in a host ethernet adapter (HEA)
US7903687B2 (en) * 2005-04-01 2011-03-08 International Business Machines Corporation Method for scheduling, writing, and reading data inside the partitioned buffer of a switch, router or packet processing device
US7586936B2 (en) * 2005-04-01 2009-09-08 International Business Machines Corporation Host Ethernet adapter for networking offload in server environment
US20060221953A1 (en) 2005-04-01 2006-10-05 Claude Basso Method and apparatus for blind checksum and correction for network transmissions
US7706409B2 (en) * 2005-04-01 2010-04-27 International Business Machines Corporation System and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA)
US7606166B2 (en) * 2005-04-01 2009-10-20 International Business Machines Corporation System and method for computing a blind checksum in a host ethernet adapter (HEA)
US7881332B2 (en) * 2005-04-01 2011-02-01 International Business Machines Corporation Configurable ports for a host ethernet adapter
US8730069B2 (en) 2005-11-23 2014-05-20 Qualcomm Incorporated Double data rate serial encoder
US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US7353316B2 (en) * 2006-03-24 2008-04-01 Micron Technology, Inc. System and method for re-routing signals between memory system components
US7627804B2 (en) * 2006-06-30 2009-12-01 Intel Corporation Memory device with speculative commands to memory core
US7810013B2 (en) * 2006-06-30 2010-10-05 Intel Corporation Memory device that reflects back error detection signals
US7774684B2 (en) * 2006-06-30 2010-08-10 Intel Corporation Reliability, availability, and serviceability in a memory device
US7881303B2 (en) 2006-12-13 2011-02-01 GlobalFoundries, Inc. Command packet packing to mitigate CRC overhead
US7840873B2 (en) 2006-12-13 2010-11-23 Globalfoundries Inc. Partial CRC insertion in data packets for early forwarding
US7644344B2 (en) * 2007-05-15 2010-01-05 Intel Corporation Latency by offsetting cyclic redundancy code lanes from data lanes
EP2191601B1 (en) * 2007-10-26 2015-08-19 Agere Systems Inc. Extraction of values from partially-corrupted data packets
US7913128B2 (en) * 2007-11-23 2011-03-22 Mosaid Technologies Incorporated Data channel test apparatus and method thereof
US8321778B2 (en) * 2008-06-16 2012-11-27 Intel Corporation Efficient in-band reliability with separate cyclic redundancy code frames
US8858698B2 (en) * 2008-09-05 2014-10-14 Mentor Worldwide Llc Acellular matrix glue
JP4922279B2 (en) * 2008-10-30 2012-04-25 株式会社東芝 Data receiving apparatus, data receiving method, and data receiving program
US8924836B2 (en) * 2008-10-30 2014-12-30 Kabushiki Kaisha Toshiba Data receiving apparatus, data receiving method, and computer-readable recording medium
US8032804B2 (en) * 2009-01-12 2011-10-04 Micron Technology, Inc. Systems and methods for monitoring a memory system
KR101037559B1 (en) 2009-03-04 2011-05-27 주식회사 실리콘웍스 Display driving system with monitoring means for data driver integrated circuit
US8381067B2 (en) * 2010-01-29 2013-02-19 International Business Machines Corporation Apparatus, system, and method for specifying intermediate CRC locations in a data stream
CN102340368B (en) * 2010-07-19 2014-07-02 中兴通讯股份有限公司 Method, system and device for monitoring error codes in CPRI (Common Public Radio Interface) link
US9106258B2 (en) 2013-11-22 2015-08-11 International Business Machines Corporation Early data tag to allow data CRC bypass via a speculative memory data return protocol
US9853772B2 (en) 2016-02-23 2017-12-26 Dell Products L.P. Intelligent network checksum processing
US10216657B2 (en) 2016-09-30 2019-02-26 Intel Corporation Extended platform with additional memory module slots per CPU socket and configured for increased performance
US9818457B1 (en) 2016-09-30 2017-11-14 Intel Corporation Extended platform with additional memory module slots per CPU socket
US10771364B2 (en) * 2018-03-27 2020-09-08 Shanghai Zhaoxin Semiconductor Co., Ltd. Network interface controller
JP7215389B2 (en) * 2019-10-08 2023-01-31 株式会社デンソー electronic controller
CN111177042A (en) * 2019-12-10 2020-05-19 中国航空工业集团公司西安航空计算技术研究所 Frame processing method and frame storage device
KR20220052018A (en) * 2020-10-20 2022-04-27 삼성전자주식회사 A storage system
CN114220222B (en) * 2021-11-30 2023-09-05 杭州海兴电力科技股份有限公司 Offline prepaid electric quantity recharging method and system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6029186A (en) * 1998-01-20 2000-02-22 3Com Corporation High speed calculation of cyclical redundancy check sums

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6112287A (en) 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
DE69519426T2 (en) 1994-03-22 2001-06-21 Hyperchip Inc Cell-based fault-tolerant architecture with advantageous use of the unallocated redundant cells
US6408402B1 (en) 1994-03-22 2002-06-18 Hyperchip Inc. Efficient direct replacement cell fault tolerant architecture
US6154826A (en) 1994-11-16 2000-11-28 University Of Virginia Patent Foundation Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order
US5867422A (en) 1995-08-08 1999-02-02 University Of South Florida Computer memory chip with field programmable memory cell arrays (fpmcas), and method of configuring
US5742840A (en) 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6006318A (en) 1995-08-16 1999-12-21 Microunity Systems Engineering, Inc. General purpose, dynamic partitioning, programmable media processor
US5860080A (en) 1996-03-19 1999-01-12 Apple Computer, Inc. Multicasting system for selecting a group of memory devices for operation
US6125419A (en) 1996-06-13 2000-09-26 Hitachi, Ltd. Bus system, printed circuit board, signal transmission line, series circuit and memory module
US6092229A (en) 1996-10-09 2000-07-18 Lsi Logic Corporation Single chip systems using general purpose processors
US5922077A (en) 1996-11-14 1999-07-13 Data General Corporation Fail-over switching system
JP3455040B2 (en) 1996-12-16 2003-10-06 株式会社日立製作所 Source clock synchronous memory system and memory unit
JP3127853B2 (en) 1997-04-30 2001-01-29 日本電気株式会社 Memory integrated circuit, main storage system and graphics memory system using the same
US5898863A (en) 1997-06-03 1999-04-27 Emc Corporation Method and apparatus for determining I/O size distribution of an input/output system and its use for load simulation
DE69836437T2 (en) 1997-12-05 2007-09-27 Intel Corporation, Santa Clara STORAGE SYSTEM WITH MEMORY MODULE WITH A MEMORY MODULE CONTROL UNIT
US6968419B1 (en) 1998-02-13 2005-11-22 Intel Corporation Memory module having a memory module controller controlling memory transactions for a plurality of memory devices
US6970968B1 (en) 1998-02-13 2005-11-29 Intel Corporation Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module
US6160423A (en) 1998-03-16 2000-12-12 Jazio, Inc. High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
PL343258A1 (en) 1998-03-16 2001-07-30 Jazio High speed signaling for interfacing vlsi cmos circuits
US6327205B1 (en) 1998-03-16 2001-12-04 Jazio, Inc. Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
US6964008B1 (en) * 1999-11-12 2005-11-08 Maxtor Corporation Data checksum method and apparatus
US6643752B1 (en) 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US6487102B1 (en) 2000-09-18 2002-11-26 Intel Corporation Memory module having buffer for isolating stacked memory devices
US6625687B1 (en) 2000-09-18 2003-09-23 Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US6317352B1 (en) 2000-09-18 2001-11-13 Intel Corporation Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
US6369605B1 (en) 2000-09-18 2002-04-09 Intel Corporation Self-terminated driver to prevent signal reflections of transmissions between electronic devices
US6449213B1 (en) 2000-09-18 2002-09-10 Intel Corporation Memory interface having source-synchronous command/address signaling
US6493250B2 (en) 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
US7055085B2 (en) * 2002-03-07 2006-05-30 Broadcom Corporation System and method for protecting header information using dedicated CRC

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6029186A (en) * 1998-01-20 2000-02-22 3Com Corporation High speed calculation of cyclical redundancy check sums

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BERND SCHÜRMANN: "Rechnerverbindungsstrukturen Kap. 5.1 Kommunikationsmodelle", 31 December 1997, VIEWEG, WIESBADEN, GERMANY, XP002323563 *

Also Published As

Publication number Publication date
CN100498724C (en) 2009-06-10
TW200516594A (en) 2005-05-16
JP4331756B2 (en) 2009-09-16
TWI265525B (en) 2006-11-01
WO2005050448A2 (en) 2005-06-02
US20050108611A1 (en) 2005-05-19
CN1882916A (en) 2006-12-20
JP2007511011A (en) 2007-04-26
EP1683017A2 (en) 2006-07-26
US7219294B2 (en) 2007-05-15

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