WO2005050465A3 - Lane testing with variable mapping - Google Patents

Lane testing with variable mapping Download PDF

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Publication number
WO2005050465A3
WO2005050465A3 PCT/US2004/036835 US2004036835W WO2005050465A3 WO 2005050465 A3 WO2005050465 A3 WO 2005050465A3 US 2004036835 W US2004036835 W US 2004036835W WO 2005050465 A3 WO2005050465 A3 WO 2005050465A3
Authority
WO
WIPO (PCT)
Prior art keywords
lanes
variable mapping
lane testing
return sequences
lane
Prior art date
Application number
PCT/US2004/036835
Other languages
French (fr)
Other versions
WO2005050465A2 (en
Inventor
Pete Vogt
Original Assignee
Intel Corp
Pete Vogt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Pete Vogt filed Critical Intel Corp
Priority to JP2006539654A priority Critical patent/JP2007514216A/en
Priority to EP04810354A priority patent/EP1683019A2/en
Publication of WO2005050465A2 publication Critical patent/WO2005050465A2/en
Publication of WO2005050465A3 publication Critical patent/WO2005050465A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol

Abstract

Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be analyzed to identify failed lanes. Other embodiments are described and claimed.
PCT/US2004/036835 2003-11-14 2004-11-05 Lane testing with variable mapping WO2005050465A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006539654A JP2007514216A (en) 2003-11-14 2004-11-05 Lane inspection with variable mapping
EP04810354A EP1683019A2 (en) 2003-11-14 2004-11-05 Lane testing with variable mapping

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/714,026 US7447953B2 (en) 2003-11-14 2003-11-14 Lane testing with variable mapping
US10/714,026 2003-11-14

Publications (2)

Publication Number Publication Date
WO2005050465A2 WO2005050465A2 (en) 2005-06-02
WO2005050465A3 true WO2005050465A3 (en) 2006-03-02

Family

ID=34573869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/036835 WO2005050465A2 (en) 2003-11-14 2004-11-05 Lane testing with variable mapping

Country Status (6)

Country Link
US (1) US7447953B2 (en)
EP (1) EP1683019A2 (en)
JP (1) JP2007514216A (en)
CN (1) CN100470496C (en)
TW (1) TWI259363B (en)
WO (1) WO2005050465A2 (en)

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Also Published As

Publication number Publication date
CN1882920A (en) 2006-12-20
JP2007514216A (en) 2007-05-31
WO2005050465A2 (en) 2005-06-02
CN100470496C (en) 2009-03-18
TWI259363B (en) 2006-08-01
TW200528984A (en) 2005-09-01
EP1683019A2 (en) 2006-07-26
US7447953B2 (en) 2008-11-04
US20050108458A1 (en) 2005-05-19

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