WO2005050701A8 - Stressed semiconductor device structures having granular semiconductor material - Google Patents

Stressed semiconductor device structures having granular semiconductor material

Info

Publication number
WO2005050701A8
WO2005050701A8 PCT/US2004/037434 US2004037434W WO2005050701A8 WO 2005050701 A8 WO2005050701 A8 WO 2005050701A8 US 2004037434 W US2004037434 W US 2004037434W WO 2005050701 A8 WO2005050701 A8 WO 2005050701A8
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor material
semiconductor device
device structures
stressed
granular
Prior art date
Application number
PCT/US2004/037434
Other languages
French (fr)
Other versions
WO2005050701A2 (en
WO2005050701A3 (en
Inventor
Bruce B Doris
Michael P Belyansky
Diane C Boyd
Dureseti Chidambarrao
Oleg Gluschenkov
Original Assignee
Ibm
Bruce B Doris
Michael P Belyansky
Diane C Boyd
Dureseti Chidambarrao
Oleg Gluschenkov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Bruce B Doris, Michael P Belyansky, Diane C Boyd, Dureseti Chidambarrao, Oleg Gluschenkov filed Critical Ibm
Priority to AT04810633T priority Critical patent/ATE512465T1/en
Priority to JP2006539779A priority patent/JP4843498B2/en
Priority to EP04810633A priority patent/EP1683187B1/en
Publication of WO2005050701A2 publication Critical patent/WO2005050701A2/en
Publication of WO2005050701A8 publication Critical patent/WO2005050701A8/en
Publication of WO2005050701A3 publication Critical patent/WO2005050701A3/en

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    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/115Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
    • H01L31/119Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
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    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28158Making the insulator
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    • H01L29/107Substrate region of field-effect devices
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    • H01L29/66409Unipolar field-effect transistors
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Abstract

A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
PCT/US2004/037434 2003-11-14 2004-11-09 Stressed semiconductor device structures having granular semiconductor material WO2005050701A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AT04810633T ATE512465T1 (en) 2003-11-14 2004-11-09 STRESSED SEMICONDUCTOR DEVICE STRUCTURES USING GRANULAR SEMICONDUCTOR MATERIAL
JP2006539779A JP4843498B2 (en) 2003-11-14 2004-11-09 Method for manufacturing a semiconductor device structure
EP04810633A EP1683187B1 (en) 2003-11-14 2004-11-09 Stressed semiconductor device structures having granular semiconductor material

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/707,018 2003-11-14
US10/707,018 US7122849B2 (en) 2003-11-14 2003-11-14 Stressed semiconductor device structures having granular semiconductor material

Publications (3)

Publication Number Publication Date
WO2005050701A2 WO2005050701A2 (en) 2005-06-02
WO2005050701A8 true WO2005050701A8 (en) 2005-11-03
WO2005050701A3 WO2005050701A3 (en) 2006-01-05

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Application Number Title Priority Date Filing Date
PCT/US2004/037434 WO2005050701A2 (en) 2003-11-14 2004-11-09 Stressed semiconductor device structures having granular semiconductor material

Country Status (7)

Country Link
US (2) US7122849B2 (en)
EP (1) EP1683187B1 (en)
JP (1) JP4843498B2 (en)
KR (1) KR100946038B1 (en)
CN (1) CN100468785C (en)
AT (1) ATE512465T1 (en)
WO (1) WO2005050701A2 (en)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10245153A1 (en) * 2002-09-27 2004-04-15 Infineon Technologies Ag Integrated field effect transistor with two control areas, use of this field effect transistor and manufacturing process
JP4085891B2 (en) * 2003-05-30 2008-05-14 ソニー株式会社 Semiconductor device and manufacturing method thereof
US7410846B2 (en) * 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US6887751B2 (en) 2003-09-12 2005-05-03 International Business Machines Corporation MOSFET performance improvement using deformation in SOI structure
US7144767B2 (en) * 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7029964B2 (en) 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7122849B2 (en) 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7202132B2 (en) * 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7118999B2 (en) * 2004-01-16 2006-10-10 International Business Machines Corporation Method and apparatus to increase strain effect in a transistor channel
US7381609B2 (en) 2004-01-16 2008-06-03 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7205206B2 (en) 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
TWI463526B (en) * 2004-06-24 2014-12-01 Ibm Improved strained-silicon cmos device and method
US7288443B2 (en) * 2004-06-29 2007-10-30 International Business Machines Corporation Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US7384829B2 (en) * 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7355256B2 (en) * 2005-04-11 2008-04-08 Nec Electronics Corporation MOS Devices with different gate lengths and different gate polysilicon grain sizes
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
US7470943B2 (en) 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US20070063277A1 (en) * 2005-09-22 2007-03-22 International Business Machines Corporation Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US20070108529A1 (en) 2005-11-14 2007-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strained gate electrodes in semiconductor devices
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US20070281405A1 (en) * 2006-06-02 2007-12-06 International Business Machines Corporation Methods of stressing transistor channel with replaced gate and related structures
US8853746B2 (en) 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
US8754446B2 (en) 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
US7829407B2 (en) * 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US20080237733A1 (en) * 2007-03-27 2008-10-02 International Business Machines Corporation Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress
JP5222583B2 (en) * 2007-04-06 2013-06-26 パナソニック株式会社 Semiconductor device
US7615435B2 (en) * 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
KR20100101446A (en) * 2009-03-09 2010-09-17 삼성전자주식회사 Semiconductor device and method of forming the same
US8034692B2 (en) * 2009-10-20 2011-10-11 International Business Machines Corporation Structure and method for manufacturing asymmetric devices
US8664070B2 (en) * 2009-12-21 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. High temperature gate replacement process
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
CN102376582A (en) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and method for producing same
JP5422534B2 (en) * 2010-10-14 2014-02-19 株式会社東芝 Nonvolatile resistance change element and method of manufacturing nonvolatile resistance change element
CN102456621A (en) * 2010-10-29 2012-05-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and method for manufacturing same
US8883623B2 (en) 2012-10-18 2014-11-11 Globalfoundries Inc. Facilitating gate height uniformity and inter-layer dielectric protection

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
US4665415A (en) 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
EP0219641B1 (en) 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrated circuit comprising bipolar and complementary mos transistors on a common substrate, and method of making the same
US4958213A (en) 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US4952524A (en) 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
EP0469215B1 (en) * 1990-07-31 1995-11-22 International Business Machines Corporation Method of forming stacked tungsten gate PFET devices and structures resulting therefrom
US5081513A (en) 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5670798A (en) 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5557122A (en) 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
KR100213196B1 (en) * 1996-03-15 1999-08-02 윤종용 Trench device separation
KR100230359B1 (en) * 1996-04-04 1999-11-15 윤종용 Fabrication method of low temperature polysilicon thin film transistor
US6403975B1 (en) 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US6251763B1 (en) 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US5960297A (en) 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (en) 1997-10-15 2001-02-26 日本電気株式会社 Semiconductor device
JP3523093B2 (en) * 1997-11-28 2004-04-26 株式会社東芝 Semiconductor device and manufacturing method thereof
US6066545A (en) 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (en) 1998-03-02 2000-12-15 윤종용 Method of fabricating trench isolation in an integrated circuit
US6361885B1 (en) 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US6165383A (en) 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US5989978A (en) 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (en) 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6319794B1 (en) 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
JP2000183346A (en) * 1998-12-15 2000-06-30 Toshiba Corp Semiconductor device and manufacture thereof
US6117722A (en) 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
US6281559B1 (en) 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6284626B1 (en) 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6274467B1 (en) * 1999-06-04 2001-08-14 International Business Machines Corporation Dual work function gate conductors with self-aligned insulating cap
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6228694B1 (en) 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6656822B2 (en) 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
KR100332108B1 (en) 1999-06-29 2002-04-10 박종섭 Transistor in a semiconductor device and method of manufacuring the same
TW426940B (en) 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6423615B1 (en) * 1999-09-22 2002-07-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
US6284623B1 (en) 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6476462B2 (en) 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
JP2002093921A (en) * 2000-09-11 2002-03-29 Hitachi Ltd Method of manufacturing semiconductor device
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
JP2003086708A (en) * 2000-12-08 2003-03-20 Hitachi Ltd Semiconductor device and manufacturing method thereof
US6563152B2 (en) 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
JP4831885B2 (en) * 2001-04-27 2011-12-07 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6403486B1 (en) 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6908810B2 (en) 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (en) 2001-08-21 2003-02-28 Nec Corp Semiconductor device and manufacturing method therefor
WO2003025984A2 (en) 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6635506B2 (en) 2001-11-07 2003-10-21 International Business Machines Corporation Method of fabricating micro-electromechanical switches on CMOS compatible substrates
US6461936B1 (en) 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
US6534390B1 (en) * 2002-01-16 2003-03-18 Chartered Semiconductor Manufacturing Ltd. Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure
US6621392B1 (en) 2002-04-25 2003-09-16 International Business Machines Corporation Micro electromechanical switch having self-aligned spacers
JP2004172389A (en) * 2002-11-20 2004-06-17 Renesas Technology Corp Semiconductor device and method for manufacturing the same
US6717216B1 (en) 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6825529B2 (en) 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6974981B2 (en) 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7279746B2 (en) 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
JP4449374B2 (en) * 2003-09-04 2010-04-14 株式会社日立製作所 Semiconductor device
US7119403B2 (en) 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US8008724B2 (en) 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US7015082B2 (en) 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7122849B2 (en) 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247912B2 (en) 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs

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