WO2005050722A1 - DESIGN AND FABRICATION OF 6.1- Å FAMILY SEMICONDUCTOR DEVICES USING SEMI-INSULATING AlSb SUBSTRATE - Google Patents

DESIGN AND FABRICATION OF 6.1- Å FAMILY SEMICONDUCTOR DEVICES USING SEMI-INSULATING AlSb SUBSTRATE Download PDF

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WO2005050722A1
WO2005050722A1 PCT/US2004/037707 US2004037707W WO2005050722A1 WO 2005050722 A1 WO2005050722 A1 WO 2005050722A1 US 2004037707 W US2004037707 W US 2004037707W WO 2005050722 A1 WO2005050722 A1 WO 2005050722A1
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semiconductor device
semiconductor
layers
alsb
substrate
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PCT/US2004/037707
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French (fr)
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John W. Sherohman
Arthur W. Coombs, Iii
Jick Hong Yee
Kuang Jen J. Wu
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The Regents Of The University Of California
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Priority claimed from US10/856,175 external-priority patent/US7224041B1/en
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Publication of WO2005050722A1 publication Critical patent/WO2005050722A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02398—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02466—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02549—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/0256—Selenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02562—Tellurides

Definitions

  • the present invention relates to semiconductors. More specifically, the present invention relates to bulk single crystal Aluminum Antimonide (AlSb) substrates incorporated with heterostructures from the 6.1-A family of semiconductors. State of Technology
  • Antimonide/ Arsenide heterostructures are recognized in the semiconductor industry as revolutionary low-noise, low-power, high-speed electronic devices.
  • the composition of the Antimonide/ Arsenide heterostructure is composed of multiple layers of Antimonide and Arsenide semiconductor compounds such as AlSb, GaSb, InAs, and related ternary and quaternary alloys from the elements of Al, As, Ga, In, and Sb.
  • Antimonide and Arsenide semiconductor compounds have a crystal structure dimension or lattice parameter that is nearly matched at 6.1 A (Angstrom). Such compounds are identified as lattice-matched 6.1-A family III-V semiconductors.
  • HEMTs high electron mobility transistors
  • HFETs heterostructure field-effect transistors
  • RITDs resonant interband tunneling diodes
  • HBTs heterojunction bipolar transistors
  • HSS hybrid superconductor /semiconductor devices
  • magneto-electronic devices e.g., Hybrid Hall effect device
  • QCLs quantum cascade lasers
  • Antimonide/ Arsenide heterostructure devices can be used for high-speed analog and digital applications, highspeed logic applications, innovative multi-function radar and comrnunication systems, and mid-infrared lasing and detection applications. Such applications strongly impact military and national security interest as well as cornrnercialization interest.
  • 6.1-A family heterostructure devices are complicated because available semi-insulating (SI) substrates, i.e., substrates with very high resistivity (p) at room temperature (p 3 oo greater than about 10 7 ⁇ -cm) do not have a suitable lattice parameter for lattice matching semiconductors from the 6.1-A family III-V or the 6.1-A family II- VI (e.g., Zinc Telluride (ZnTe)) semiconductors.
  • the room temperature lattice parameter of the desirable III-V SI GaAs substrate is 5.653 A and the room temperature lattice parameter of the III-V SI InP substrate is 5.869 A.
  • the lattice mismatch is about 8% when heterostructures from the 6.1-A III-V family are used for desired devices, which can create about 10 8 cm -2 surface dislocations.
  • 6.1-A family II- VI heterostructure devices e.g. ZeTe
  • grown on such GaAs substrates also results in a mismatch coefficient of about 7.4%, which induces compressed strain along the interface.
  • buffer layers remains a fabrication issue because surface dislocations, known as threading dislocations, can still travel through the buffer layer material and severely degrade device performance by acting as radiative (photon) and non-radiative (phonon) recombination centers.
  • the present invention provides a method of forming a semiconductor device that includes: providing an AlSb substrate; and growing one or more semiconductor layers substantially lattice matched to the AlSb substrate.
  • Another aspect of the present invention is to provide a method of forming a semiconductor device that includes: providing an AlSb substrate; and growing a semiconductor heterostructure substantially lattice matched to the AlSb substrate, wherein the semiconductor device is capable of being arranged with one or more buffer layers intermediate the AlSb substrate and the semiconductor heterostructure.
  • a further aspect of the present invention is to provide a semiconductor device that includes an AlSb substrate and one or more semiconductor layers grown on the AlSb substrate, wherein the one or more semiconductor layers are substantially lattice matched to the AlSb substrate.
  • a final aspect of the present invention is to provide a semiconductor device that includes an AlSb substrate and a semiconductor heterostructure grown on the AlSb base substrate, wherein the heterostructure is substantially lattice matched to the AlSb substrate and wherein the one or more buffer layers are capable of being arranged intermediate the AlSb substrate and the heterostructure.
  • the present invention provides a semi-insulating (SI) Aluminum.
  • Antimonide (AlSb) single crystal substrate capable of having a resistivity (p) at room temperature (p 3 ⁇ o ⁇ ° ) of greater than about 10 3 ⁇ -cm, more often greater than about 10 7 ⁇ -cm to be utilized in the design and fabrication of 6.1-A family Antimonide/Arsenide heterostructures devices.
  • SI AlSb of the present invention provides a substantially lattice- matched substrate to construct high-speed low-power Antimonide/Arsenide and/or Zinc/Telluride heterostructures electronic devices such as, but not limited to, HEMTs, HFETs, RITDs, HBTs, HSS structures, and magneto- electronic devices (e.g., the Hybrid Hall effect device).
  • HEMTs high-speed low-power Antimonide/Arsenide and/or Zinc/Telluride heterostructures electronic devices
  • HEMTs high-speed low-power Antimonide/Arsenide and/or Zinc/Telluride heterostructures electronic devices
  • Such a high resistivity AlSb substrate also allows for inter-device isolation for other Antimonide/Arsenide and/or Zinc/Telluride heterostructures such as QCLs, photodiodes, infrared photodiodes, and infrared detectors.
  • Fig. 1 shows lattice constants vs. band gaps for various pure and compound semiconductors.
  • Fig. 2(a) illustrates a conventionally grown heterostructure device having a GaAs SI substrate.
  • Fig. 2(b) illustrates heterostructure device of the present invention having an AlSb substrate.
  • Fig. 3 illustrates a current versus voltage (I-V) curve of the substrate material to be utilized in heterostructures.
  • I-V current versus voltage
  • AlSb Aluminum Antimonide
  • GaAs Gallium Arsenide
  • InSb Indium Antimonide
  • GaP Gallium Phosphide
  • AlSb Similar to Germanium (Ge), Silicon (Si) and GaAs, AlSb has a zinc-blend cubic crystal structure, similar to
  • AlSb has an indirect energy band gap, and similar to
  • the energy band gap (E g ) is relatively high, i.e., an Eg of about 1.62 eV.
  • E g energy band gap
  • Such structure and band-gap features of AlSb provide a material that is beneficial as an electronic device quality semiconductor substrate when utilized with heterostructures from the 6.1 A III-V family of semiconductors, such as AlSb, GaSb and Indium Arsenide (InAs).
  • the AlSb substrate of the present invention can also be arranged with II- VI 6.1-A family semiconductors, such as, for example, Zinc Telluride (ZnTe) and Cadmium Selenide (CdSe), to provide desired semiconductor heterostructure devices.
  • ZnTe Zinc Telluride
  • CdSe Cadmium Selenide
  • ZnTe is a compound that can be incorporated into the present invention because such a compound has a direct energy band gap of 2.26eV and a zinc-blend structure with a lattice constant of 6.10037 A.
  • ZnTe provides a substantially lattice matched material with the AlSb substrate of the present invention to construct heterostructure opto-electronic devices in the blue- green region, such as pure green light emitting diodes (LEDs) and laser diodes (LDs).
  • LEDs pure green light emitting diodes
  • LDs laser diodes
  • Heterostructures can include one or more thin layers (between about 10 A and up to about 2 ⁇ m) of binary compounds such as, but not limited to Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Indium Arsenide (InAs), Zinc Telluride (ZnTe), and/or related ternary and quaternary alloys of such materials.
  • binary compounds such as, but not limited to Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Indium Arsenide (InAs), Zinc Telluride (ZnTe), and/or related ternary and quaternary alloys of such materials.
  • Antimonide (Sb) and Arsenide (As) semiconductor compounds are exemplary materials that can be utilized in the present invention due to an inherent crystal structure dimension or lattice parameter that is substantially lattice matched at 6.1 Angstroms, e.g., the room temperature lattice constant of AlSb is 6.135 A, for GaSb it is 6.095 A, and for InAs it is 6.058 A.
  • Fig. 1 illustrates lattice constants vs. band gaps for various pure and compound semiconductors.
  • the present invention incorporates the 6.1 A family semiconductors, such as, for example, InAs 2, GaSb 4, CdSe 6, ZnTe 8, and AlSb 10 (also denoted by squares).
  • compounds such as AlSb, GaSb, InAs, ZnTe, CdSe and related ternary and quaternary alloys from the elements of Al, As, Ga, In, Sb, Cd, Se, Zn, and Te are herein identified as substantially lattice-matched 6.1-A family semiconductors that can utilized in the present invention.
  • the present invention utilizes such 6.1-A family semiconductors identified above, by growing such materials on a substrate material as disclosed herein with or without an intermediate buffer layer (i.e., a buffer layer, such as, for example, a layer of AlSb or layers containing Sb compounds, is herein defined as an intermediate material layer sandwiched between a substrate and a heterostructure).
  • a buffer layer such as, for example, a layer of AlSb or layers containing Sb compounds, is herein defined as an intermediate material layer sandwiched between a substrate and a heterostructure.
  • Such a buffer layer's functions can include crystal lattice matching, electrical isolation and /or surface smoothing.
  • the Aluminum Antimonide (AlSb) single crystal substrate utilized herein is capable of having a substantially uniform resistivity (p) as measured over the entire produced substrate at room temperature (300K°) of often greater than about 10 3 ⁇ -cm, more often greater than about 10 7 ⁇ -cm.
  • Such AlSb crystal substrates of the present invention can be produced by a Czochralski (CZ) growth technique.
  • CZ Czochralski
  • other growth methods such as, but not limited to, a Traveling Heating Method (THM), capable of producing quality crystals may also be employed.
  • THM Traveling Heating Method
  • Such a crystal substrate is beneficial in the design and fabrication of heterostructure devices that utilize semiconductor materials from the 6.1-A family semiconductors as described above, e.g., GaSb, InAs, AlSb, ZnTe, CdSe and various combinations of the elements Al, As, Ga, In, Sb, Zn, Te, Cd, and Se thereof.
  • AlSb Being a member of the 6.1-A family semiconductors, the use of AlSb provides a lattice-matched substrate to such overlying semiconductor materials so as to construct high-speed (e.g., quantum tunneling devices capable of oscillating at up to about 1 THz) low-power electronic devices such as, but not limited to, HEMTs, HFETs, RITDs, HBTs, HSS structures, and magneto-electronic devices (e.g., the Hybrid Hall effect device).
  • high-speed e.g., quantum tunneling devices capable of oscillating at up to about 1 THz
  • low-power electronic devices such as, but not limited to, HEMTs, HFETs, RITDs, HBTs, HSS structures, and magneto-electronic devices (e.g., the Hybrid Hall effect device).
  • the present invention's high resistivity capability of greater than about 10 7 ⁇ -cm AlSb substrate allows for interdevice isolation for other heterostructures, such as, but not limited to, Antimonide/Arsenide QCLs, infrared photodiodes, and infrared detectors.
  • device fabrication using a lattice matched AlSb substrate as disclosed herein minimizes the nucleation of threading dislocations.
  • the production yield and operational life-time of 6.1-A family heterostructure devices grown on an AlSb substrate are enhanced over similar devices that use SI GaAs or SI InP substrates.
  • FIG. 2(a) shows an example of the basic concept that exemplifies conventionally grown heterostructure semiconductor devices, e.g., HEMTs, HFETs, RITDs, HBTs, etc., that incorporate semiconductor materials within the 6.1-A family such as, for example, Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Indium Arsenide (InAs), Zinc Telluride (ZnTe) and/or their related ternary and quaternary alloys as previously disclosed.
  • AlSb Aluminum Antimonide
  • GaSb Gallium Antimonide
  • InAs Indium Arsenide
  • ZnTe Zinc Telluride
  • Such devices utilize a semi-insulating substrate 10, such as GaAs, and one or more overlying layers 12, such as, but not limited to AlSb, or layers containing Sb compounds, to buffer and /or smooth lattice mismatches between substrate 10 and overlying semiconductor layers 16, 18, to prevent non-uniformities, such as threaded dislocations.
  • a semi-insulating substrate 10 such as GaAs
  • overlying layers 12 such as, but not limited to AlSb, or layers containing Sb compounds
  • MBE molecular beam epitaxy
  • FIG. 2(b) shows a basic example configuration of a heterostructure semiconductor device of the present invention, generally designated as reference numeral 100, that utilizes similar semiconductor layers from the 6.1- A family as discussed above.
  • Such a device incorporates a substantially uniform high resistivity AlSb substrate 10 of often greater than about 10 3 ⁇ -cm, more often greater than about 10 7 ⁇ -cm, capable of semi-insulating one or more overlying heterostructure layers 16, 18.
  • Device fabrication using such an AlSb substrate 10 as disclosed herein in addition to providing a semi- insulating base substrate, minimizes the nucleation of threading dislocations as a result of the substantial lattice matching to overlying 6.1-A family semiconductor layers, resulting in an increase in the operational life-time of 6.1-A family heterostructure devices, such as HEMTs, HFETs, RITDs, HBTs, LEDs, HSS structures, and magneto-electronic devices (e.g., the Hybrid Hall effect device).
  • Fig. 3 shows an I-V curve 310 (current versus voltage) of a substrate material of the present invention illustrating current levels capable of being produced within such a substrate between about - 4.5 ⁇ amps and about +4 ⁇ amps when subjected to respective voltages between about -10 volts and about ⁇ IO volts.
  • I-V curve 310 represents the basic electrical properties of a substrate AlSb material used in a device such as a heterostructure, fabricated from such a material as disclosed herein.
  • a thin piece of AlSb sample measuring about 1cm x 1cm x 0.1cm and mechanically polished to about Vi micron finish is arranged with approximately 1000 A thick and 6 mm diameter of gold sputtered onto the sample's surface to establish electrical contacts.
  • An I-V measurement then is conducted at room temperature (300K°) at a voltage range between about - 10V and about +10V, which covers the operating voltage regime for most of the common electrical devices.
  • Such an I-V characteristic is ohrnic in nature and a resulting response current of about ⁇ 5 ⁇ A, as shown in Fig.
  • an AlSb substrate of the present invention that can produce such a surprising I-V curve as shown in Fig. 3, illustrates the semi- insulating properties of such a substrate having a lattice constant of 6.1 A that can fulfill a need in the industry to produce desired electronic devices.
  • NRL Naval Research Laboratory
  • TRW at the August 2002 IEEE Lester Eastman Conference on High Performance Devices stated such an industry need by stating, "A semi- insulating substrate is required for complex circuits, and none exist with a lattice constant near 6.2 A," IEEE Proceedings, pp. 288-296, 2002.
  • heterostructure devices such as, but not limited to Antimonide/Arsenide heterostructures, which have previously been fabricated on a GaSb substrate for infrared laser and infrared detector applications, can also incorporate an AlSb substrate as disclosed herein.
  • GaSb is substantially lattice matched, such a substrate material is a very low band gap semiconductor (bandgap at 300 °K for GaSb is 0.725 eV) and is therefore quite conducting at room temperature (resistivity of about 0.01 ⁇ -cm, which is much lower than the resistivity capability of AlSb greater than about 10 7 ⁇ -cm), has a high carrier concentration, and low mechanical strength.
  • GaSb can be deposited on an AlSb substrate of the present invention to provide interdevice isolation and lattice matching properties as discussed above.

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Abstract

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The A1Sb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-Å family heterostructure devices.

Description

DESIGN AND FABRICATION OF 6.1-A FAMILY SEMICONDUCTOR DEVICES USING SEMI-INSULATING AlSb SUBSTRATE [0001] The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory. RELATED APPLICATION [0002] This application claims the benefit of U.S. Provisional Application No. 60/520,903, filed November 17, 2003, entitled "Design and Fabrication of 6.1-A Family III-V Semiconductor Devices Using Semi-Insulating AlSb Substrate" which is incorporated herein by this reference. BACKGROUND OF THE INVENTION Field of the Invention
[0003] The present invention relates to semiconductors. More specifically, the present invention relates to bulk single crystal Aluminum Antimonide (AlSb) substrates incorporated with heterostructures from the 6.1-A family of semiconductors. State of Technology
[0004] Antimonide/ Arsenide heterostructures are recognized in the semiconductor industry as revolutionary low-noise, low-power, high-speed electronic devices. The composition of the Antimonide/ Arsenide heterostructure is composed of multiple layers of Antimonide and Arsenide semiconductor compounds such as AlSb, GaSb, InAs, and related ternary and quaternary alloys from the elements of Al, As, Ga, In, and Sb. These Antimonide and Arsenide semiconductor compounds have a crystal structure dimension or lattice parameter that is nearly matched at 6.1 A (Angstrom). Such compounds are identified as lattice-matched 6.1-A family III-V semiconductors. [0005] Recent research and development of the 6.1-A family heterostructure devices, has lead to fabrication of state-of-the-art electronic devices, e.g., high electron mobility transistors (HEMTs), heterostructure field-effect transistors (HFETs), resonant interband tunneling diodes (RITDs), heterojunction bipolar transistors (HBTs), hybrid superconductor /semiconductor (HSS) devices, magneto-electronic devices (e.g., Hybrid Hall effect device), quantum cascade lasers (QCLs), irifrared photodiodes, and infrared detectors. The development of Antimonide/ Arsenide heterostructure devices has demonstrated that such devices can be used for high-speed analog and digital applications, highspeed logic applications, innovative multi-function radar and comrnunication systems, and mid-infrared lasing and detection applications. Such applications strongly impact military and national security interest as well as cornrnercialization interest. [0006] However, fabrication of 6.1-A family heterostructure devices is complicated because available semi-insulating (SI) substrates, i.e., substrates with very high resistivity (p) at room temperature (p3oo greater than about 107 Ω-cm) do not have a suitable lattice parameter for lattice matching semiconductors from the 6.1-A family III-V or the 6.1-A family II- VI (e.g., Zinc Telluride (ZnTe)) semiconductors. For example, the room temperature lattice parameter of the desirable III-V SI GaAs substrate is 5.653 A and the room temperature lattice parameter of the III-V SI InP substrate is 5.869 A. In the case of GaAs, the lattice mismatch is about 8% when heterostructures from the 6.1-A III-V family are used for desired devices, which can create about 108 cm-2 surface dislocations. Moreover, 6.1-A family II- VI heterostructure devices (e.g. ZeTe) grown on such GaAs substrates, also results in a mismatch coefficient of about 7.4%, which induces compressed strain along the interface. [0007] Because of such disparate lattice mismatches, device fabrication using such substrates requires a buffer layer material (often a relatively thick layer of up to a few microns of a semiconductor material, such as AlSb) arranged between a substrate and heterostructure to counter surface dislocation nucleation. The use of such buffer layers remains a fabrication issue because surface dislocations, known as threading dislocations, can still travel through the buffer layer material and severely degrade device performance by acting as radiative (photon) and non-radiative (phonon) recombination centers.
[0008] Background information on such a buffer layer requirement and remaining fabrication issues can be found in, "The 6.1 A family (InAs, GaSb, AlSb) and its heterostructures: a selective review," by Herbert Kroemer, Physica E 20, pp. 196 - 203, 2004, including the following, "When the MBE growth is performed on lattice-mismatched GaAs substrates rather than on GaSb, the interposition of a proper buffer layer is essential for high quality growth ... Using GaSb for the initial nucleation leads to very rough initial morphology. Nucleating with AlSb leads to much less initial surface roughness, but the residual roughness persists with continued growth, and leads to InAs quantum wells with poor transport properties. Following the initial thin AlSb nucleation layer with a thick (« 1 μm) GaSb buffer layer smoothes out the surface morphology, and if the growth is then switched to AlSb or (Al, Ga)Sb, the smooth surface persist, leading to InAs quantum wells with much better transport properties."
[0009] Accordingly, a need exists for a high-speed low-power electronic heterostructure device that includes a single crystal, lattice-matched, semi- insulating substrate to replace the current use of lattice-mismatched substrates of SI GaAs or SI InP. Such a need has been jointly emphasized by several, such as Naval Research Laboratory (NRL) and TRW researchers at the August 2002 IEEE Lester Eastman Conference on High Performance Devices, "A senri-insulating substrate is required for complex circuits, and none exist with a lattice constant near 6.2 A," IEEE Proceedings, pp. 288-296, 2002. The present invention is directed to such a need. SUMMARY OF THE INVENTION [0010] Accordingly, the present invention provides a method of forming a semiconductor device that includes: providing an AlSb substrate; and growing one or more semiconductor layers substantially lattice matched to the AlSb substrate.
[0011] Another aspect of the present invention is to provide a method of forming a semiconductor device that includes: providing an AlSb substrate; and growing a semiconductor heterostructure substantially lattice matched to the AlSb substrate, wherein the semiconductor device is capable of being arranged with one or more buffer layers intermediate the AlSb substrate and the semiconductor heterostructure.
[0012] A further aspect of the present invention is to provide a semiconductor device that includes an AlSb substrate and one or more semiconductor layers grown on the AlSb substrate, wherein the one or more semiconductor layers are substantially lattice matched to the AlSb substrate.
[0013] A final aspect of the present invention is to provide a semiconductor device that includes an AlSb substrate and a semiconductor heterostructure grown on the AlSb base substrate, wherein the heterostructure is substantially lattice matched to the AlSb substrate and wherein the one or more buffer layers are capable of being arranged intermediate the AlSb substrate and the heterostructure. [0014] Accordingly, the present invention provides a semi-insulating (SI) Aluminum. Antimonide (AlSb) single crystal substrate capable of having a resistivity (p) at room temperature (p 3θoκ°) of greater than about 103 Ω-cm, more often greater than about 107Ω-cm to be utilized in the design and fabrication of 6.1-A family Antimonide/Arsenide heterostructures devices. The use of SI AlSb of the present invention provides a substantially lattice- matched substrate to construct high-speed low-power Antimonide/Arsenide and/or Zinc/Telluride heterostructures electronic devices such as, but not limited to, HEMTs, HFETs, RITDs, HBTs, HSS structures, and magneto- electronic devices (e.g., the Hybrid Hall effect device). Such a high resistivity AlSb substrate also allows for inter-device isolation for other Antimonide/Arsenide and/or Zinc/Telluride heterostructures such as QCLs, photodiodes, infrared photodiodes, and infrared detectors. Fabrication of such heterostructures using SI Aluminum Antimonide (AlSb) single crystal substrates substantially minimizes the nucleation of threading dislocations. As a result, production yield and operational life-time of Antimonide/Arsenide and/or Zinc/Telluride heterostructure devices configured with such substrates are enhanced over similar devices, such as devices that incorporate SI GaAs or SI InP substrates.
BRIEF DESCRIPTION OF THE DRAWLNGS [0015] The accompanying drawings, which are incorporated into and form a part of the disclosure, illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention. Fig. 1 shows lattice constants vs. band gaps for various pure and compound semiconductors. Fig. 2(a) illustrates a conventionally grown heterostructure device having a GaAs SI substrate. Fig. 2(b) illustrates heterostructure device of the present invention having an AlSb substrate. Fig. 3 illustrates a current versus voltage (I-V) curve of the substrate material to be utilized in heterostructures. DETAILED DESCRIPTION OF THE INVENTION [0016] Referring now to the following detailed information, and to incorporated materials; a detailed description of the invention, including specific embodiments, is presented. The detailed description serves to explain the principles of the invention.
[0017] Unless otherwise indicated, all numbers expressing quantities of ingredients, constituents, reaction conditions and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by the subject matter presented herein. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the subject matter presented herein are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. General Description
[0018] An Aluminum Antimonide (AlSb) semiconductor substrate material is a member of the III-V family of semiconductors including Gallium Arsenide (GaAs), Indium Antimonide (InSb), Gallium Phosphide (GaP), etc. Similar to Germanium (Ge), Silicon (Si) and GaAs, AlSb has a zinc-blend cubic crystal structure, similar to
Ge and Si, but unlike GaAs, AlSb has an indirect energy band gap, and similar to
GaAs, but unlike Ge and Si, the energy band gap (Eg) is relatively high, i.e., an Eg of about 1.62 eV. Such structure and band-gap features of AlSb provide a material that is beneficial as an electronic device quality semiconductor substrate when utilized with heterostructures from the 6.1 A III-V family of semiconductors, such as AlSb, GaSb and Indium Arsenide (InAs). [0019] Moreover, the AlSb substrate of the present invention can also be arranged with II- VI 6.1-A family semiconductors, such as, for example, Zinc Telluride (ZnTe) and Cadmium Selenide (CdSe), to provide desired semiconductor heterostructure devices. Specifically, ZnTe is a compound that can be incorporated into the present invention because such a compound has a direct energy band gap of 2.26eV and a zinc-blend structure with a lattice constant of 6.10037 A. By virtue of such a band gap, ZnTe provides a substantially lattice matched material with the AlSb substrate of the present invention to construct heterostructure opto-electronic devices in the blue- green region, such as pure green light emitting diodes (LEDs) and laser diodes (LDs). [0020] Heterostructures, as utilized in the present invention, can include one or more thin layers (between about 10 A and up to about 2 μm) of binary compounds such as, but not limited to Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Indium Arsenide (InAs), Zinc Telluride (ZnTe), and/or related ternary and quaternary alloys of such materials. For example, Antimonide (Sb) and Arsenide (As) semiconductor compounds are exemplary materials that can be utilized in the present invention due to an inherent crystal structure dimension or lattice parameter that is substantially lattice matched at 6.1 Angstroms, e.g., the room temperature lattice constant of AlSb is 6.135 A, for GaSb it is 6.095 A, and for InAs it is 6.058 A. [0021] Fig. 1 illustrates lattice constants vs. band gaps for various pure and compound semiconductors. The present invention incorporates the 6.1 A family semiconductors, such as, for example, InAs 2, GaSb 4, CdSe 6, ZnTe 8, and AlSb 10 (also denoted by squares). Accordingly, compounds, such as AlSb, GaSb, InAs, ZnTe, CdSe and related ternary and quaternary alloys from the elements of Al, As, Ga, In, Sb, Cd, Se, Zn, and Te are herein identified as substantially lattice-matched 6.1-A family semiconductors that can utilized in the present invention.
[0022] The present invention utilizes such 6.1-A family semiconductors identified above, by growing such materials on a substrate material as disclosed herein with or without an intermediate buffer layer (i.e., a buffer layer, such as, for example, a layer of AlSb or layers containing Sb compounds, is herein defined as an intermediate material layer sandwiched between a substrate and a heterostructure). Such a buffer layer's functions can include crystal lattice matching, electrical isolation and /or surface smoothing. [0023] The Aluminum Antimonide (AlSb) single crystal substrate utilized herein is capable of having a substantially uniform resistivity (p) as measured over the entire produced substrate at room temperature (300K°) of often greater than about 103Ω-cm, more often greater than about 107Ω-cm. Such AlSb crystal substrates of the present invention can be produced by a Czochralski (CZ) growth technique. However, other growth methods such as, but not limited to, a Traveling Heating Method (THM), capable of producing quality crystals may also be employed. A detailed disclosure of example methods of producing such a single crystal substrate is disclosed in Incorporated by reference, Co-pending, U.S. Application Serial No. 10/260,141, titled "High Resistivity Aluminum Antimonide Radiation Detector" by Sherohman et al., assigned to the assignee of the present invention, the disclosure herein incorporated by reference in its entirety. [0024] Such a crystal substrate is beneficial in the design and fabrication of heterostructure devices that utilize semiconductor materials from the 6.1-A family semiconductors as described above, e.g., GaSb, InAs, AlSb, ZnTe, CdSe and various combinations of the elements Al, As, Ga, In, Sb, Zn, Te, Cd, and Se thereof. Being a member of the 6.1-A family semiconductors, the use of AlSb provides a lattice-matched substrate to such overlying semiconductor materials so as to construct high-speed (e.g., quantum tunneling devices capable of oscillating at up to about 1 THz) low-power electronic devices such as, but not limited to, HEMTs, HFETs, RITDs, HBTs, HSS structures, and magneto-electronic devices (e.g., the Hybrid Hall effect device). [0025] In addition, the present invention's high resistivity capability of greater than about 107Ω-cm AlSb substrate allows for interdevice isolation for other heterostructures, such as, but not limited to, Antimonide/Arsenide QCLs, infrared photodiodes, and infrared detectors. Moreover, device fabrication using a lattice matched AlSb substrate as disclosed herein, minimizes the nucleation of threading dislocations. As a result, the production yield and operational life-time of 6.1-A family heterostructure devices grown on an AlSb substrate are enhanced over similar devices that use SI GaAs or SI InP substrates. Specific Description
[0026] FIG. 2(a) shows an example of the basic concept that exemplifies conventionally grown heterostructure semiconductor devices, e.g., HEMTs, HFETs, RITDs, HBTs, etc., that incorporate semiconductor materials within the 6.1-A family such as, for example, Aluminum Antimonide (AlSb), Gallium Antimonide (GaSb), Indium Arsenide (InAs), Zinc Telluride (ZnTe) and/or their related ternary and quaternary alloys as previously disclosed. Such devices utilize a semi-insulating substrate 10, such as GaAs, and one or more overlying layers 12, such as, but not limited to AlSb, or layers containing Sb compounds, to buffer and /or smooth lattice mismatches between substrate 10 and overlying semiconductor layers 16, 18, to prevent non-uniformities, such as threaded dislocations. [0027] Semiconductor layers 16, such as AlSb, and alternating semiconductor layers 18 such as semiconductor layers from the 6.1-A family doped with materials such as, but not limited to, Silicon (Si), Tellerium (Te), Selenium (Se), Beryllium (Be), and Tin (Sn), can be grown according to methods known in the art, such as by molecular beam epitaxy (MBE), to create barrier layers, channels (current paths), caps, Schottky barriers, etc., so as to form what is know to those skilled in the art as semiconductor heterostructures. In addition, an oxidation barrier (not shown) can be grown so as to protect underlying layers of materials, e.g., 16, 18, and metalized ohmic contacts (not shown), can be applied to predetermined layers according to methods known in the art to provide such devices with a means for such devices to be integrated into a desired circuitry. [0028] FIG. 2(b) shows a basic example configuration of a heterostructure semiconductor device of the present invention, generally designated as reference numeral 100, that utilizes similar semiconductor layers from the 6.1- A family as discussed above. Such a device incorporates a substantially uniform high resistivity AlSb substrate 10 of often greater than about 103 Ω-cm, more often greater than about 107 Ω-cm, capable of semi-insulating one or more overlying heterostructure layers 16, 18. Device fabrication using such an AlSb substrate 10 as disclosed herein, in addition to providing a semi- insulating base substrate, minimizes the nucleation of threading dislocations as a result of the substantial lattice matching to overlying 6.1-A family semiconductor layers, resulting in an increase in the operational life-time of 6.1-A family heterostructure devices, such as HEMTs, HFETs, RITDs, HBTs, LEDs, HSS structures, and magneto-electronic devices (e.g., the Hybrid Hall effect device).
[0029] Fig. 3 shows an I-V curve 310 (current versus voltage) of a substrate material of the present invention illustrating current levels capable of being produced within such a substrate between about - 4.5 μamps and about +4 μamps when subjected to respective voltages between about -10 volts and about ΨIO volts. Such a measurement involves measuring an electrical current flow across a sample material, such as an AlSb bulk crystal utilized in the present invention, when a DC voltage is applied onto a given sample. I-V curve 310, as shown in Fig. 3, represents the basic electrical properties of a substrate AlSb material used in a device such as a heterostructure, fabricated from such a material as disclosed herein.
[0030] In making the measurements to produce such a curve as shown in Fig. 3, a thin piece of AlSb sample measuring about 1cm x 1cm x 0.1cm and mechanically polished to about Vi micron finish is arranged with approximately 1000 A thick and 6 mm diameter of gold sputtered onto the sample's surface to establish electrical contacts. An I-V measurement then is conducted at room temperature (300K°) at a voltage range between about - 10V and about +10V, which covers the operating voltage regime for most of the common electrical devices. Such an I-V characteristic is ohrnic in nature and a resulting response current of about ±5 μA, as shown in Fig. 3, is produced when an AlSb substrate sample of the present invention is subjected to the imposed measurement conditions. Previous reports as disclosed in, "Electrical Properties of Semiconducting AlSb", by R. K. Willardson, A. C. Beer and A. E. Middleton, J. Electro. Chem. Soc. 101, 354 (1954); and in "Some Properties of alurninium antimonide p-n junctions", by C. R. Bemrose, Solid-State Electronics, 7, 765 (1964), show AlSb I-V measurements response currents with similar measurement conditions in the hundreds of μA to mA ranges.
[0031] Accordingly, an AlSb substrate of the present invention that can produce such a surprising I-V curve as shown in Fig. 3, illustrates the semi- insulating properties of such a substrate having a lattice constant of 6.1 A that can fulfill a need in the industry to produce desired electronic devices. As discussed above, researchers at The Naval Research Laboratory (NRL) and TRW at the August 2002 IEEE Lester Eastman Conference on High Performance Devices stated such an industry need by stating, "A semi- insulating substrate is required for complex circuits, and none exist with a lattice constant near 6.2 A," IEEE Proceedings, pp. 288-296, 2002. [0032] Moreover, in addition to applications as discussed above, heterostructure devices, such as, but not limited to Antimonide/Arsenide heterostructures, which have previously been fabricated on a GaSb substrate for infrared laser and infrared detector applications, can also incorporate an AlSb substrate as disclosed herein. Although GaSb is substantially lattice matched, such a substrate material is a very low band gap semiconductor (bandgap at 300 °K for GaSb is 0.725 eV) and is therefore quite conducting at room temperature (resistivity of about 0.01 Ω-cm, which is much lower than the resistivity capability of AlSb greater than about 107 Ω-cm), has a high carrier concentration, and low mechanical strength. [0033] In addition to the above, as another example arrangement, for applications where GaSb has been used as a substrate, GaSb can be deposited on an AlSb substrate of the present invention to provide interdevice isolation and lattice matching properties as discussed above.
[0034] It is to be understood that the number of semiconductor layers and the variations disclosed herein are not limited to these numbers of layers and/or variations. While the example arrangements of the invention are described, various modifications may be made in such arrangements to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Claims

THE INVENTION CLAIMED IS
1. A method of forming a semiconductor device, comprising: providing an AlSb substrate; and growing one or more semiconductor layers substantially lattice matched to said AlSb substrate.
2. The method of claim 1, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about - 4.5 μamps and about +4 μamps when subjected to respective voltages between about -10 volts and about +10 volts.
3. The method of claim 1, wherein said one or more semiconductor layers comprises a compound from the 6.1-A family III-V semiconductor family.
4. The method of claim 1, wherein said one or more semiconductor layers comprises a compound from the 6.1-A family II- VI semiconductor family.
5. The method of claim 1, wherein said growing step further comprises molecular beam epitaxy.
6. The method of claim 1, wherein said one or more semiconductor layers further comprise alternating layers of doped and undoped semiconductor materials.
7. The method of claim 1, said semiconductor device is configured comprising an HFET.
8. The method of claim 1, said semiconductor device is configured comprising an HEMT.
9. The method of claim 1, said semiconductor device is configured comprising an HBT.
10. The method of claim 1, said semiconductor device is configured comprising an RITD.
11. The method of claim 1, said semiconductor device is configured comprising a HSS structure.
12. The method of claim 1, said semiconductor device is configured comprising a Hybrid Hall effect device.
13. The method of claim 1, said semiconductor device is configured comprising a QCL.
14. The method of claim 1, said semiconductor device is configured comprising an infrared photodiode.
15. The method of claim 1, said semiconductor device is configured comprising an infrared detector.
16. A method of forming a semiconductor device, comprising: providing an AlSb substrate; and growing a semiconductor heterostructure substantially lattice matched to said AlSb substrate, wherein said semiconductor device is capable of being arranged with one or more buffer layers intermediate said AlSb substrate and said semiconductor heterostructure.
17. The method of claim 16, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about - 4.5 μamps and about +4 μamps when subjected to respective voltages between about -10 volts and about +10 volts.
18. The method of claim 16, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A III-V family.
19. The method of claim 16, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A II- VI family.
20. The method of claim 16, wherein said one or more buffer layers are arranged so as to provide crystal lattice matching, electrical isolation and/or surface smoothing.
21. A semiconductor device, comprising: an AlSb substrate; and one or more semiconductor layers grown on said AlSb substrate, wherein said one or more semiconductor layers are substantially lattice matched to said AlSb substrate.
22. The semiconductor device of claim 21, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about - 4.5 μamps and about +4 μamps when subjected to respective voltages between about -10 volts and about +10 volts.
23. The semiconductor device of claim 21, wherein said one or more semiconductor layers further comprise one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A III-V family.
24. The semiconductor device of claim 21, wherein said one or more semiconductor layers further comprise one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A II- VI family.
25. The semiconductor device of claim 21, wherein said semiconductor layers are formed by molecular beam epitaxy.
26. The semiconductor device of claim 21, wherein said one or more semiconductor layers further comprise alternating layers of doped and undoped semiconductor materials.
27. The semiconductor device of claim 21, said semiconductor device is configured comprising an HFET.
28. The semiconductor device of claim 21, said semiconductor device is configured comprising an HEMT.
29. The semiconductor device of claim 21, said semiconductor device is configured comprising an HBT.
30. The semiconductor device of claim 21, said semiconductor device is configured comprising an RITD.
31. The semiconductor device of claim 21, said semiconductor device is configured comprising a HSS structure.
32. The semiconductor device of claim 21, said semiconductor device is configured comprising a Hybrid Hall effect device.
33. The semiconductor device of claim 21, said semiconductor device is configured comprising a QCL.
34. The semiconductor device of claim 21, said semiconductor device is configured comprising an infrared photodiode.
35. The semiconductor device of claim 21, said semiconductor device is configured comprising an infrared detector.
36. A semiconductor device, comprising: an AlSb substrate; and a semiconductor heterostructure grown on said AlSb base substrate, wherein said heterostructure is substantially lattice matched to said AlSb substrate and wherein one or more buffer layers are capable of being arranged intermediate said AlSb substrate and said heterostructure.
37. The semiconductor device of claim 36, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about - 4.5 μamps and about +4 μamps when subjected to respective voltages between about -10 volts and about +10 volts.
38. The semiconductor device of claim 36, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A III-V family.
39. The semiconductor device of claim 36, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-A II- VI family.
40. The semiconductor device of claim 36, wherein said buffer layer is arranged so as to provide crystal lattice matching, electrical isolation and/or surface smoothing.
41. The semiconductor device of claim 36, wherein said semiconductor heterostructure is formed by molecular beam epitaxy.
42. The semiconductor device of claim 36, wherein said semiconductor heterostructure further comprises alternating layers of doped and undoped semiconductor materials.
43. The semiconductor device of claim 36, said semiconductor device is configured comprising an HFET.
44. The semiconductor device of claim 36, said semiconductor device is configured comprising an HEMT.
45. The semiconductor device of claim 36, said semiconductor device is configured comprising an HBT.
46. The semiconductor device of claim 36, said semiconductor device is configured comprising an RITD.
47. The semiconductor device of claim 36, said semiconductor device is configured comprising a HSS structure.
48. The semiconductor device of claim 36, said semiconductor device is configured comprising a Hybrid Hall effect device.
49. The semiconductor device of claim 36, said semiconductor device is configured comprising a QCL.
50. The semiconductor device of claim 36, said semiconductor device is configured comprising an infrared photodiode.
51. The semiconductor device of claim 36, said semiconductor device is configured comprising an infrared detector.
PCT/US2004/037707 2003-11-17 2004-11-12 DESIGN AND FABRICATION OF 6.1- Å FAMILY SEMICONDUCTOR DEVICES USING SEMI-INSULATING AlSb SUBSTRATE WO2005050722A1 (en)

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