WO2005050842A3 - Apparatus and method for generating a delayed clock signal - Google Patents

Apparatus and method for generating a delayed clock signal Download PDF

Info

Publication number
WO2005050842A3
WO2005050842A3 PCT/US2004/037503 US2004037503W WO2005050842A3 WO 2005050842 A3 WO2005050842 A3 WO 2005050842A3 US 2004037503 W US2004037503 W US 2004037503W WO 2005050842 A3 WO2005050842 A3 WO 2005050842A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
generating
output
synchronizing
delayed clock
Prior art date
Application number
PCT/US2004/037503
Other languages
French (fr)
Other versions
WO2005050842A2 (en
Inventor
Leel S Janzen
Original Assignee
Micron Technology Inc
Leel S Janzen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Leel S Janzen filed Critical Micron Technology Inc
Publication of WO2005050842A2 publication Critical patent/WO2005050842A2/en
Publication of WO2005050842A3 publication Critical patent/WO2005050842A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Abstract

An apparatus and method for generating a delayed clock siral is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal (CLK) from an input clock signal and further includes a delay circuit (106) having an input coupled to the output of the synchronizing circuit. The delay circuit (106) provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.
PCT/US2004/037503 2003-11-13 2004-11-08 Apparatus and method for generating a delayed clock signal WO2005050842A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/713,587 US7065666B2 (en) 2003-11-13 2003-11-13 Apparatus and method for generating a delayed clock signal
US10/713,587 2003-11-13

Publications (2)

Publication Number Publication Date
WO2005050842A2 WO2005050842A2 (en) 2005-06-02
WO2005050842A3 true WO2005050842A3 (en) 2006-08-17

Family

ID=34573761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/037503 WO2005050842A2 (en) 2003-11-13 2004-11-08 Apparatus and method for generating a delayed clock signal

Country Status (2)

Country Link
US (9) US7065666B2 (en)
WO (1) WO2005050842A2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8155236B1 (en) * 2002-06-21 2012-04-10 Netlogic Microsystems, Inc. Methods and apparatus for clock and data recovery using transmission lines
TWI267870B (en) * 2004-05-10 2006-12-01 Hynix Semiconductor Inc Semiconductor memory device for controlling output timing of data depending on frequency variation
US7698589B2 (en) * 2006-03-21 2010-04-13 Mediatek Inc. Memory controller and device with data strobe calibration
US7849348B1 (en) * 2006-09-12 2010-12-07 NexLogic Microsystems, Inc. Programmable delay clock buffer
US7423928B2 (en) * 2007-01-30 2008-09-09 Atmel Corporation Clock circuitry for DDR-SDRAM memory controller
KR100933800B1 (en) * 2008-06-30 2009-12-24 주식회사 하이닉스반도체 Output enable signal generator of semiconductor memory device
US8181056B2 (en) * 2008-09-30 2012-05-15 Mosaid Technologies Incorporated Serial-connected memory system with output delay adjustment
US8161313B2 (en) * 2008-09-30 2012-04-17 Mosaid Technologies Incorporated Serial-connected memory system with duty cycle correction
US8140629B2 (en) * 2008-09-30 2012-03-20 Pivot Solutions, Inc. System and method for processing instant messages
KR101086874B1 (en) * 2009-09-04 2011-11-25 주식회사 하이닉스반도체 Semiconductor integrated circuit
US8423814B2 (en) * 2010-03-19 2013-04-16 Netlogic Microsystems, Inc. Programmable drive strength in memory signaling
US8520744B2 (en) * 2010-03-19 2013-08-27 Netlogic Microsystems, Inc. Multi-value logic signaling in multi-functional circuits
US8537949B1 (en) 2010-06-30 2013-09-17 Netlogic Microsystems, Inc. Systems, circuits and methods for filtering signals to compensate for channel effects
US8494377B1 (en) 2010-06-30 2013-07-23 Netlogic Microsystems, Inc. Systems, circuits and methods for conditioning signals for transmission on a physical medium
US8896455B2 (en) * 2011-08-18 2014-11-25 Microsoft Corporation Intrusion detection and communication
KR101989393B1 (en) * 2012-08-24 2019-06-14 에스케이하이닉스 주식회사 Domain crossing circuit of semiconductor apparatus
US9036434B1 (en) * 2013-10-31 2015-05-19 Nanya Technology Corporation Random access memory and method of adjusting read timing thereof
CN109367586B (en) * 2018-10-19 2023-10-17 卡斯柯信号有限公司 Clock synchronization system and method for urban rail transit signal system
CN110442187B (en) * 2019-08-08 2021-05-28 南京芯驰半导体科技有限公司 Clock limiting system for module and method thereof
CN112711547B (en) * 2020-12-25 2022-08-02 海宁奕斯伟集成电路设计有限公司 Memory control device, control method and memory chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020733A (en) * 1994-12-22 2000-02-01 Anritsu Company Two port handheld vector network analyzer with frequency monitor mode
US20040260961A1 (en) * 2003-06-23 2004-12-23 Chengting Zhao Synchronized serial interface

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (en) 1992-10-02 1996-03-14 삼성전자주식회사 Semiconductor memory device
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US5465076A (en) * 1991-10-04 1995-11-07 Nippondenso Co., Ltd. Programmable delay line programmable delay circuit and digital controlled oscillator
US5608896A (en) 1992-05-28 1997-03-04 Texas Instruments Incorporated Time skewing arrangement for operating memory devices in synchronism with a data processor
JPH08180678A (en) 1994-12-27 1996-07-12 Hitachi Ltd Dynamic ram
JPH08222808A (en) * 1995-02-15 1996-08-30 Mitsubishi Electric Corp Manufacture of semiconductor light-emitting device
JP3768608B2 (en) 1996-01-30 2006-04-19 株式会社日立製作所 Semiconductor device and semiconductor memory device
JP4014669B2 (en) 1996-04-22 2007-11-28 株式会社ルネサステクノロジ Synchronous semiconductor memory device
US5771264A (en) 1996-08-29 1998-06-23 Altera Corporation Digital delay lock loop for clock signal frequency multiplication
JPH1079650A (en) * 1996-09-04 1998-03-24 Fujitsu Ltd Clock generating circuit
US5953284A (en) 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
JP3566051B2 (en) * 1997-11-14 2004-09-15 株式会社ルネサステクノロジ Clock signal generation circuit outputting a plurality of clock signals having different phases and clock phase control circuit using the same
KR100274602B1 (en) 1997-11-20 2000-12-15 윤종용 Synchronous memory device
US6061296A (en) * 1998-08-17 2000-05-09 Vanguard International Semiconductor Corporation Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices
KR100295056B1 (en) * 1999-01-27 2001-07-12 윤종용 Loop &method for delay-locking
KR100287184B1 (en) 1999-02-23 2001-04-16 윤종용 Internal Clock Delay Circuit for Synchronous DRAM Semiconductor Device and Delay Method Thereof
KR100304705B1 (en) 1999-03-03 2001-10-29 윤종용 SDRAM having posted CAS latency and CAS latency control method therefor
JP2000306399A (en) 1999-04-22 2000-11-02 Mitsubishi Electric Corp Semiconductor device
US6636978B1 (en) * 1999-11-17 2003-10-21 International Business Machines Corporation Rescheduling data input and output commands for bus synchronization by using digital latency shift detection
JP3848038B2 (en) 2000-01-12 2006-11-22 株式会社日立製作所 Semiconductor integrated circuit
US6359579B1 (en) * 2000-02-17 2002-03-19 Advanced Micro Devices, Inc. Digital logic correction circuit for a pipeline analog to digital (A/D) converter
JP2001297585A (en) * 2000-04-18 2001-10-26 Mitsubishi Electric Corp Clock generating circuit, and semiconductor memory provided with it
US6438062B1 (en) * 2000-07-28 2002-08-20 International Business Machines Corporation Multiple memory bank command for synchronous DRAMs
US6553472B2 (en) 2001-01-12 2003-04-22 Sun Microsystems, Inc. Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor
JP2002230972A (en) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp Synchronous semiconductor memory
JP2003032104A (en) * 2001-07-12 2003-01-31 Mitsubishi Electric Corp Dll circuit and its control method
US6552955B1 (en) * 2001-10-30 2003-04-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption
US6542416B1 (en) 2001-11-02 2003-04-01 Rambus Inc. Methods and arrangements for conditionally enforcing CAS latencies in memory devices
KR100446291B1 (en) 2001-11-07 2004-09-01 삼성전자주식회사 Delay locked loop circuit capable of adjusting locking resolution using CAS latency
DE10208715B4 (en) 2002-02-28 2004-05-06 Infineon Technologies Ag Latency timer for an S-DRAM
JP4181847B2 (en) 2002-10-25 2008-11-19 エルピーダメモリ株式会社 Timing adjustment circuit, semiconductor device and timing adjustment method
KR100468776B1 (en) 2002-12-10 2005-01-29 삼성전자주식회사 Synchronous semiconductor memory device capable of reducing the influence of clock jitter
KR100518547B1 (en) * 2002-12-28 2005-10-04 삼성전자주식회사 Delay locked loop capable of compensating the delay of internal clock signal according to the variation of output driver strength in semiconductor memory device
US6958658B2 (en) * 2003-03-25 2005-10-25 Intel Corporation Circuit and method for generating a clock signal
US7134034B1 (en) 2003-10-15 2006-11-07 Integrated Device Technology, Inc. Data paths with receiver timing fixable to a downstream stage and methods of operation thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020733A (en) * 1994-12-22 2000-02-01 Anritsu Company Two port handheld vector network analyzer with frequency monitor mode
US20040260961A1 (en) * 2003-06-23 2004-12-23 Chengting Zhao Synchronized serial interface

Also Published As

Publication number Publication date
US8677170B2 (en) 2014-03-18
US7278045B2 (en) 2007-10-02
US20100023793A1 (en) 2010-01-28
US7275172B2 (en) 2007-09-25
US20060265621A1 (en) 2006-11-23
US20120159229A1 (en) 2012-06-21
US20060265619A1 (en) 2006-11-23
US20060265620A1 (en) 2006-11-23
US20050108590A1 (en) 2005-05-19
WO2005050842A2 (en) 2005-06-02
US20060265618A1 (en) 2006-11-23
US20060117204A1 (en) 2006-06-01
US7610503B2 (en) 2009-10-27
US7350093B2 (en) 2008-03-25
US7065666B2 (en) 2006-06-20
US8127171B2 (en) 2012-02-28
US7308594B2 (en) 2007-12-11
US20060277427A1 (en) 2006-12-07
US7610502B2 (en) 2009-10-27

Similar Documents

Publication Publication Date Title
WO2005050842A3 (en) Apparatus and method for generating a delayed clock signal
AU2003265818A1 (en) Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
GB2353156A (en) Method and apparatus for varying a clock frequency on a phase by phase basis
GB2363684B (en) Frequency-multiplying delay locked loop
EP0969350A3 (en) Clock switching circuit
AU6365500A (en) Method and apparatus for adjusting control signal timing in a memory device
TW200605512A (en) Circuit for applying jitter and test
WO2004010418A3 (en) Variable duty cycle clock generation circuits and methods and systems using the same
WO2004049140A3 (en) Clock synchronization circuit
WO2007120957A3 (en) Dynamic timing adjustment in a circuit device
WO2004038918A3 (en) Method and device for generating a clock signal with predetermined clock signal properties
WO2005053159A3 (en) Clock pulse generator apparatus with reduced jitter clock phase
TW200515705A (en) Frequency divider and related frequency divider designing method
EP1271284A3 (en) Timing signal generating system
TW200518021A (en) Apparatus and method for processing signals
DE60228909D1 (en) Network interface with programmable delay and frequency doubler
EP1260899A3 (en) Circuit and method for generating a delayed internal clock signal
JP2005039829A5 (en)
TWI268410B (en) Circuit and method for generating a clock signal
AU2001278331A1 (en) Frequency synthesizer
WO2003038687A3 (en) Optimization of the design of a synchronous digital circuit
WO2006082516A3 (en) A fractional and integer pure digital programmable clock generator
KR100807610B1 (en) Frequency multiply circuit using smd, with arbitrary multiplication factor
TW200514991A (en) Method and apparatus for testing a bridge circuit
WO2002103911A3 (en) Method and apparatus for a clock circuit

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase