WO2005052611A1 - Identifying process and temperature of silicon chips - Google Patents
Identifying process and temperature of silicon chips Download PDFInfo
- Publication number
- WO2005052611A1 WO2005052611A1 PCT/US2004/039689 US2004039689W WO2005052611A1 WO 2005052611 A1 WO2005052611 A1 WO 2005052611A1 US 2004039689 W US2004039689 W US 2004039689W WO 2005052611 A1 WO2005052611 A1 WO 2005052611A1
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- Prior art keywords
- ring oscillator
- chip
- frequency
- temperature
- measured
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31707—Test strategies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Definitions
- the present disclosure relates to systems and techniques for identifying process and temperature of chips.
- Chips for use in communications devices must generally be rated to operate at a specified nominal speed, within a certain allowed tolerance. However, a set of chips generated from a single wafer commonly will fall into a range of different process speed ratings.
- SDRAM chips require an external clock from the host controller with control and data signals. Because the host clock is sensitive to process speed, temperature and voltage variations, it is possible that a given set of parameters used to generate timing in a controller may not hold true across all process speed, temperature and voltage variations. In such cases speed binning is commonly used. This involves sorting chips according to different speed settings, and even providing software customized for different speeds. Of course, such customized operations can be very costly.
- a method for determining an operating parameter of a chip having first and second ring oscillators includes measuring a frequency of the first ring oscillator, measuring a frequency of the second ring oscillator, and calculating an operating parameter of the chip as a function of the first and second ring oscillator frequencies.
- computer-readable media embodying a program of instructions is executable by a computer to perform a method of determining an operating parameter of a chip having first and second ring oscillators.
- the method includes measuring a frequency of the first ring oscillator, measuring a frequency of the second ring oscillator, and calculating an operating parameter of the chip as a function of the first and second ring oscillator frequencies.
- a system includes a chip and a processor configured to measure the frequencies of first and second ring oscillators on the chip.
- the processor is further configured to calculate an operating parameter of the chip as a function of the first and second ring oscillator frequencies.
- an apparatus for measuring an operating parameter of a chip including means for measuring a frequency of a first ring oscillator, means for measuring a frequency of the second ring oscillator, and means for calculating an operating parameter of the chip as a function of the first and second ring oscillator frequencies.
- FIG. 1 is a functional block diagram of an exemplary hardware configuration comprising a dual ring oscillator configuration embedded in a chip;
- FIG. 2 is a flow chart illustrating an exemplary method for obtaining a frequency measurement from a ring oscillator embedded in a chip
- FIG. 3 illustrates an exemplary data set representing a range of characterization data of chips from a wafer, plotted as the product of ring oscillator frequencies versus temperature;
- FIG. 4 is a flow chart illustrating an exemplary method for determining the operating temperature of a chip as a function of ring oscillator frequency;
- FIG. 5 illustrates an exemplary data set representing the range of characterization data of chips from a wafer, plotted as the quotient of ring oscillator frequencies versus temperature;
- FIG. 6 illustrates an exemplary data set representing the range of characterization data of chips from a wafer, plotted as the normalized quotient of ring oscillator frequencies versus temperature;
- FIG. 7 is a flow chart illustrating an exemplary method for determining the process speed of a chip as a function of ring oscillator frequency and temperature;
- FIG. 8 illustrates the exemplary data set of FIG. 3, to which the identified chip speed is applied to adjust the previously calculated temperature
- FIG. 9 is a flow chart illustrating an exemplary method for adjusting the previously calculated temperature
- FIG. 10 is a flow chart illustrating an exemplary end to end process for calculating and identifying both temperature and process speed of a chip based on two measured ring oscillator frequencies;
- FIG. 11 is a graph illustrating an exemplary distribution of chips produced across multiple splits.
- FIG. 12 is a flow chart illustrating another alternative exemplary method for determining a chip's operating temperature and speed.
- FIG. 1 is a functional block diagram of an exemplary hardware configuration comprising a dual ring oscillator configuration that may be embedded on a chip 116.
- FIG. 1 also illustrates a processor 114 that may also be embedded on the chip 116 or, alternatively, on a separate chip (separation indicated by line 117) that receives inputs from the chip on which the dual ring oscillator configuration of FIG. 1 is embedded.
- Processor 114 receives inputs from the dual ring oscillator configuration, and performs various methods described herein according to the inputs.
- the dual ring oscillator configuration includes a first ring oscillator 100 and a second ring oscillator 102, the outputs of which are switched at multiplexer 104 after optionally conditioned by buffers 101 and 103, respectively.
- Chips often have a plurality of ring oscillators embedded thereon, and any two of a chip's available ring oscillators may be used as first ring oscillator 100 and second ring oscillator 102 in the dual ring oscillator configuration of FIG. 1.
- Each of ring oscillators 100 and 102 may comprise a plurality of inverters in serial, or may alternatively comprise some other configuration that is generally known in the art.
- the chip may also include a frequency divider 109 to generate a clock output 108 from the dual ring oscillator configuration.
- a first counter 106 may be used to count clock output 108.
- the chip may also include a second counter 110 that counts an independent clock output.
- second counter 110 could be configured to count the output 112 of that internal clock.
- FIG. 2 is a flow chart illustrating an exemplary method for obtaining a frequency measurement from a ring oscillator embedded in a chip. At block 200, one of the two ring oscillators in the dual ring oscillator configuration of FIG.
- the selected ring oscillator is enabled as the output 108 illustrated in FIG. 1.
- counters for both the selected ring oscillator and an independent clock for example the internal clock of an embedded chip, are then disabled.
- the counters are simultaneously reset.
- the counts for both of the counters are saved simultaneously at block 206.
- the counts for both of the counters are again saved simultaneously at block 210.
- a difference ratio of the saved count values is calculated.
- the count difference of the ring oscillator between the first count save at block 206 and the second count save at block 210 is determined, and the count difference of the independent clock between the first count save at block 206 and the second count save at block 210 is determined.
- the ratio of these two differences is then calculated.
- the ratio is multiplied by the clock speed of the independent clock at block 214, to convert the ratio to a frequency value, which is output as indicated at 216.
- a typical setting for a Tcxo counter (internal clock) of an embedded chip is 19.2MHz, however the teachings herein are not limited to any particular clock type or speed setting.
- the process repeats again at block 200, with the second ring oscillator now being selected and enabled as the output 108.
- the frequencies of both the first and second ring oscillators in the dual ring oscillator configuration are measured.
- These steps may be performed by a processor that is also embedded on the chip, or may be performed by a separate processor embedded on a second chip, wherein inputs to the separate processor are obtained by the ring oscillator counter and independent clock counter, which comprise readable registers on the chip whose ring oscillator frequencies are being measured.
- various methods disclosed herein may be implemented to calculate the operating temperature and process speed of the chip. As with determination of ring oscillator frequencies, the methods described below may be performed by a processor that is also embedded on the chip, or may be performed by a separate processor embedded on a second chip that is operably coupleded to the chip whose temperature and process speed are being measured. The methods are based upon measurable relationships between a chip's ring oscillator frequency and its process speed and temperature.
- the frequency of each of a chip's ring oscillators is a function of the process speed, voltage, and temperature of a chip during operation
- different sets of equations according to the particular mathematical relationships can be implemented to calculate either process speed or temperature according to known characterization data of the ring oscillators and the chip.
- exemplary techniques disclosed herein may be used to determine operating temperature of a chip as a function of ring oscillator frequency.
- the techniques may implement a series of equations according to a linear model that may be developed through the empirical testing of a large number of chips from various "splits" that are representative of the range of process speeds achieved from an entire production lot.
- split denotes a set of chips that may be either slower than nominal, faster than nominal, or nominal.
- a production wafer may include various splits. Because the chips produced from any given wafer will include a range of slow, fast and nominal chips, i.e. a range of different splits, the testing and collection of characterization data across the entire split range can be used to develop a linear model representative of all chips that may be produced from the production lot. Those skilled in the art will recognize various methods of collecting characterization data for this range of chips.
- chips for gathering empirical data for a particular split may be identified either through a precise manufacturing method in which a wafer is carefully controlled during production to produce only a single type of chip (such as only slow, only nominal or only fast), or by speed binning the resultant chips from manufactured wafers that produce numerous splits.
- FIG. 3 illustrates an exemplary data set representing a range of characterization data of chips across multiple splits.
- the data may be plotted, for example, to represent the product of two ring oscillator frequencies 300 versus temperature 302.
- the data will represent a range of frequency products that is representative of chips across the multiple splits, from slow chips 304, through nominal chips 306, to fast chips 308.
- a linear model can be formulated to represent the data range across the multiple splits.
- T ⁇ and T 2 represent the minimum and maximum temperatures, respectively, that would be expected for the given / within the range of splits, xyz
- FIG. 4 is a flow chart illustrating an exemplary method for determining the operating temperature of a chip as a function of ring oscillator frequency according to the above equations.
- the measured ring oscillator frequencies are received into the temperature calculation algorithm at block 400.
- the values for 7] and T 2 may be calculated with the equations according to the known characterization data and the measured ring oscillator frequencies, which are represented by the constant values C x .
- the calculated temperature values represent minimum and maximum temperatures expected for the chip given the measured ring oscillator frequency according to known characterization data of chips from the same wafer.
- the actual temperature of the chip may then be estimated, at block 406, as the
- FIG. 5 illustrates an exemplary data set representing the previously discussed range of characterization data of chips across multiple splits from a wafer, this time plotted as the quotient of the two ring oscillator frequencies 500 versus temperature 502.
- the data will represent a range of frequency quotients representative of chips across the multiple splits, from slow chips 504, through nominal chips 506, to fast chips 508. From this graph, it is apparent that, because the two ring oscillators do not have a similar slope, the ratio of their frequencies also does not result in a constant ratio over temperature.
- the quotient must be normalized according to the average temperature that was calculated as described above: wherein N represents a normalization factor that is determined by triangulation based on the characterization data.
- N represents a normalization factor that is determined by triangulation based on the characterization data.
- the characterization data which may be modeled with a linear equation whose slope defines a change over temperature, may be normalized so that the data is constant over temperature.
- a normalization factor N can be calculated such that it causes the slope of the modeled data to be approximately zero, meaning that the normalized data is constant over temperature.
- FIG. 6 illustrates an exemplary data set representing the range of characterization data of chips across the multiple splits, this time plotted as the normalized quotient of the two ring oscillator frequencies 600 versus temperature 602.
- the data will still represent the range of frequency quotients representative of chips across the splits, from slow chips 604, through nominal chips 606, to fast chips 608, but will now adhere to a linear model that is stable over temperature.
- the graph identifies three known ranges of process speed for chips within this known range of splits: a fast range 610, a nominal range 612 and a slow range 614. For a chip being measured for process speed during use, depending on where the normalized quotient of its measured ring oscillator frequencies falls within the ranges indicated on the graph of FIG. 6, the chip may then be identified as fast, nominal, or slow.
- FIG. 7 is a flow chart illustrating an exemplary method for determining the process speed of a chip as a function of ring oscillator frequency and temperature as described above.
- the frequencies of the two ring oscillators are received by the algorithm at block 700, and their quotient is calculated at block 702.
- the ring oscillator frequency quotient is normalized at block 704, and its process speed may then be identified as fast, nominal or slow at block 706 using the characterization data as described above.
- FIG. 8 illustrates the exemplary data set of FIG. 3, to which the identified chip speed may now be applied to adjust the previously calculated temperature estimate.
- the characterization data plotted as the product of ring oscillator frequencies 800 versus temperature 802 represents frequency product ranges for slow chips 804, nominal chips 806 and fast chips 808.
- the temperature of a chip was estimated as T avg 810, which was midway between the minimum temperature T and the maximum temperature T 2 for the measured ring oscillator frequencies within the characterized split range.
- the initially calculated temperature estimate can be refined accordingly. Because the data in FIG.
- slow range 812 is bounded by minimum temperature T and a lower boundary temperature T x 818
- nominal range 814 is bounded by lower boundary temperature T x 818 and an upper boundary temperature
- the refined temperature may be calculated as the midway point in whichever range was identified in the earlier process determination step, which was described above. For example, if the process speed of the chip was determined to be fast, the fast range 816 would be utilized to adjust the estimated
- FIG. 9 is a flow chart illustrating an exemplary method for adjusting the initial temperature estimation according to the method described above.
- the identified process speed is received.
- a process range is identified within characterization temperature data, at block 902.
- a refined temperature is estimated, with a reduced margin of error, at block 904.
- FIG. 10 is a flow chart illustrating an exemplary end to end process for calculating and identifying both temperature and process speed of a chip based on two measured ring oscillator frequencies.
- the individual steps have been described above in terms of comprising separate algorithms. However, it will be understood by those skilled in the art that the steps may be performed individually, in combined functions, or as an end to end process or algorithm, such as that illustrated in the flow chart of FIG. 10.
- the product of the measured frequencies is calculated, and the minimum temperature for chips in that split is calculated, and at block 1004 the maximum such temperature is calculated.
- the average temperature of the previously determined minimum and maximum temperatures is calculated according to equations based on known characterization data of the split. Once it is calculated, the average temperature is stored as an initial chip temperature estimation at block 1006. Then, at block 1008, the quotient of the measured ring oscillator frequencies is calculated, and normalized according to characterization data of the split range at block 1010, as described above. Based on the normalized quotient, the process speed of the chip is identified at block 1012. Then, at block 1014, a process range is identified in the characterization data for temperatures across the multiple splits, and a refined temperature estimation is made at block 1016, accordingly. Finally, at block 1018, the end to end algorithm outputs, as a function of the initially measured ring oscillator frequencies and characterization data from the range of splits, the chip's process speed and refined temperature estimation.
- FIG. 11 is a graph illustrating the distribution of chips produced across multiple splits obtained during an entire production cycle. From this distribution, which represents a typical Gaussian distribution of samples, a first order difference equation approach for identifying process speed and temperature of a chip can be used to enable a second order equation for yielding more accurate results than the methods previously described.
- the data 1100 plotted as quantity of chips vs. process speed, represent the various splits that may be produced from a wafer, and may be divided so as to fall into three categories: a nominal category 1102, slow category 1104 and fast category 1106.
- the device delay in terms of either of a chip's two ring oscillators, K ⁇ and K ⁇ is 0.
- Device delay may be calculated according to the characterization data, as will be recognized by those skilled in the art.
- slow category 1104 the device delays are negative, and in the fast category 1106 the device delays are positive.
- its actual device delay can be quantified and, depending on the amount of deviation from nominal center 1108, its process speed can be calculated.
- the process speed of the chip can be identified from the P value graph of split data and the temperature of the chip can be identified from the T value graph of split data.
- actual graphs and plots are not necessary for implementing the methods disclosed herein. Rather, such graphs and plots of data are used for purposes of clarity in explaining the disclosed methods.
- characterization data may be a ⁇ anged in any format, and need only be referenced to determine particular values of a chip, but need not be referenced in a particular format.
- characterization data may be used to determine the constants in the equations disclosed herein, which may then be implemented into particular algorithms used to calculate process speed and temperature for a particular chip based upon its operating ring oscillator frequencies.
- FIG. 12 is a flow chart illustrating the alternative exemplary method for determining temperature and speed that was described above.
- the ring oscillator frequencies of a chip are measured.
- scaled frequency numbers for process P value and temperature T mlue are calculated according to the formulas above.
- the calculated value of P value is compared to characterization data representative of the range of P mlue values in the split. From this comparison, the process speed of the chip is determined.
- the calculated value of T value is compared to characterization data representative of the range of T value values in the split. From this comparison, the chip's temperature is determined.
- a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
- An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an ASIC.
- the ASIC may reside in a chip.
- the processor and the storage medium may reside as discrete components in a chip.
Abstract
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Priority Applications (1)
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CN2004800347083A CN1886668B (en) | 2003-11-24 | 2004-11-24 | Identifying process and temperature of silicon chips |
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US52510303P | 2003-11-24 | 2003-11-24 | |
US60/525,103 | 2003-11-24 | ||
US10/750,342 | 2003-12-31 | ||
US10/750,342 US7742887B2 (en) | 2003-11-24 | 2003-12-31 | Identifying process and temperature of silicon chips |
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- 2004-11-24 CN CN2004800347083A patent/CN1886668B/en active Active
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US20030204354A1 (en) * | 2001-10-30 | 2003-10-30 | Corr William E. | Apparatus and method for determining effect of on-chip noise on signal propagation |
Also Published As
Publication number | Publication date |
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US20050114056A1 (en) | 2005-05-26 |
US7742887B2 (en) | 2010-06-22 |
CN1886668A (en) | 2006-12-27 |
CN1886668B (en) | 2010-09-22 |
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