WO2005057403A3 - Method for the automatic creation of a processor using a machine description - Google Patents

Method for the automatic creation of a processor using a machine description Download PDF

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Publication number
WO2005057403A3
WO2005057403A3 PCT/DE2004/002580 DE2004002580W WO2005057403A3 WO 2005057403 A3 WO2005057403 A3 WO 2005057403A3 DE 2004002580 W DE2004002580 W DE 2004002580W WO 2005057403 A3 WO2005057403 A3 WO 2005057403A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
processing
functional unit
functional units
description
Prior art date
Application number
PCT/DE2004/002580
Other languages
German (de)
French (fr)
Other versions
WO2005057403A2 (en
Inventor
Gordon Cichon
Original Assignee
Univ Dresden Tech
Gordon Cichon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102004004434A external-priority patent/DE102004004434B4/en
Application filed by Univ Dresden Tech, Gordon Cichon filed Critical Univ Dresden Tech
Priority to US10/595,965 priority Critical patent/US20090024832A1/en
Publication of WO2005057403A2 publication Critical patent/WO2005057403A2/en
Publication of WO2005057403A3 publication Critical patent/WO2005057403A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Abstract

The invention relates to a method for creating an SIMD processor, which contains respective slices that share common control signals in order to process various data, whereby the geometry of the processor is created at least indirectly from a machine description. The aim of the invention is to create machine descriptions from a given processor description, which can be used to perform an automated optimal hardware design of SIMD processors. To achieve this, the production of the geometry of the SIMD processor is used as a basis for selecting functional units, which process vectors, from an identifier in the machine description. In addition, a first and second reduced functional unit are selected according to their definitions from each vector-processing functional unit, said reduced functional units processing only one element of a vectorial value as a component of the respective vector-processing functional unit. All reduced functional units, which use common control signals for the processing of each data element that is associated with the vectorial value, are combined to form a slice.
PCT/DE2004/002580 2003-11-24 2004-11-23 Method for the automatic creation of a processor using a machine description WO2005057403A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/595,965 US20090024832A1 (en) 2003-11-24 2004-11-23 Process for the automatic production of a processor from a machine description

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10355112.3 2003-11-24
DE10355112 2003-11-24
DE102004004434.1 2004-01-28
DE102004004434A DE102004004434B4 (en) 2003-11-24 2004-01-28 A method for improved processor design from a machine description

Publications (2)

Publication Number Publication Date
WO2005057403A2 WO2005057403A2 (en) 2005-06-23
WO2005057403A3 true WO2005057403A3 (en) 2006-02-09

Family

ID=34680016

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/002580 WO2005057403A2 (en) 2003-11-24 2004-11-23 Method for the automatic creation of a processor using a machine description

Country Status (1)

Country Link
WO (1) WO2005057403A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838583A (en) * 1996-04-12 1998-11-17 Cadence Design Systems, Inc. Optimized placement and routing of datapaths
US5896521A (en) * 1996-03-15 1999-04-20 Mitsubishi Denki Kabushiki Kaisha Processor synthesis system and processor synthesis method
WO2001033441A2 (en) * 1999-11-05 2001-05-10 Intel Corporation Structural regularity extraction and floorplanning in datapath circuits using vectors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896521A (en) * 1996-03-15 1999-04-20 Mitsubishi Denki Kabushiki Kaisha Processor synthesis system and processor synthesis method
US5838583A (en) * 1996-04-12 1998-11-17 Cadence Design Systems, Inc. Optimized placement and routing of datapaths
WO2001033441A2 (en) * 1999-11-05 2001-05-10 Intel Corporation Structural regularity extraction and floorplanning in datapath circuits using vectors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HIROSHI YOSHIMURA ET AL: "HIGH-SPEED DIGITAL BICMOS ICS 500K TRANSISTOR CUSTOM BICMOS LSI USING AUTOMATED MACROCELL DESIGN", IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, IEEE INC. NEW YORK, US, vol. 32, 1 February 1989 (1989-02-01), pages 122 - 123,308, XP000066852, ISSN: 0193-6530 *

Also Published As

Publication number Publication date
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