WO2005062349B1 - Containing capacitors and method of forming - Google Patents

Containing capacitors and method of forming

Info

Publication number
WO2005062349B1
WO2005062349B1 PCT/US2004/040252 US2004040252W WO2005062349B1 WO 2005062349 B1 WO2005062349 B1 WO 2005062349B1 US 2004040252 W US2004040252 W US 2004040252W WO 2005062349 B1 WO2005062349 B1 WO 2005062349B1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon nitride
silicon
memory array
over
region
Prior art date
Application number
PCT/US2004/040252
Other languages
French (fr)
Other versions
WO2005062349A1 (en
Inventor
H Montgomery Manning
Thomas M Graettinger
Marsela Pontoh
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP04812703.9A priority Critical patent/EP1700332B1/en
Priority to JP2006542721A priority patent/JP5007465B2/en
Publication of WO2005062349A1 publication Critical patent/WO2005062349A1/en
Publication of WO2005062349B1 publication Critical patent/WO2005062349B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material (60) within openings in an insulative material (28) to form conductive containers. A retaining structure lattice (30) is formed in physical contact with at least some of the containers, and subsequently the insulative material (28) is removed to expose outer surfaces of the containers. The retaining structure (30) can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material (100) is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode (103) is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Claims

[received by the International Bureau on 11 July 2005 (11.07.05); original claims 2, 3, 5, 6, 9, 12, 25, 30, 31, 34, 36, 45, 52, 59, 68, 70 and 71 amended; original claims 1, 49, 51, 56, 65 and 67 cancelled;
CLAIMS remaining claims unchanged (9 pages)] The invention claimed is: 1. Canceled.
2. A method of forming a plurality of capacitor devices, comprising: forming conductive capacitor electrode material within openings in a first material comprising silicon and oxygen; providing a retaining structure in physical contact with at least some of the conductive capacitor electrode material; removing at least some of the first material while the retaining structure physically contacts the at least some of the conductive capacitor electrode material; after removing at least some of the first material, incorporating the conductive capacitor electrode material into a plurality of capacitor devices; wherein: the first material comprises borophosphosilicate glass; a wet etch is utilized to remove at least some of the first material; the retaining structure comprises silicon nitride and a material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch; said material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch consisting of silicon.
3. A method of forming a plurality of capacitor devices, comprising: forming conductive capacitor electrode material within openings in a first material comprising silicon and oxygen; providing a retaining structure in physical contact with at least some of the conductive capacitor electrode material; removing at least some of the first material while the retaining structure physically contacts the at least some of the conductive capacitor electrode material; after removing at least some of the first material, incorporating the conductive capacitor electrode material into a plurality of capacitor devices; wherein: the first material comprises borophosphosilicate glass; a wet etch is utilized to remove at least some of the first material; the retaining structure comprises silicon nitride and a material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch; said material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch including polycrystalline silicon. 29
4. The method of claim 3 wherein the polycrystalline silicon is over the silicon nitride.
5. The method of claim 4 wherein the polycrystalline silicon has a thickness of from 5θA to 100θA.
6. The method of claim 4 wherein the polycrystalline silicon has a thickness of from 50A to 100θA; and wherein the silicon nitride has a thickness of from 50A to 3000A.
7. The method of claim 3 wherein the polycrystalline silicon is under the silicon nitride.
8. The method of claim 3 wherein the polycrystalline silicon is over and under the silicon nitride.
9. The method of claim 8 wherein the polycrystalline silicon below the silicon nitride has a thickness of from 50A to 50θA; wherein the polycrystalline silicon above the silicon nitride has a thickness of from 5θA to 50θA; and wherein the silicon nitride has a thickness of from 5θA to 100θA.
10. The method of claim 3 wherein the polycrystalline silicon entirely surrounds the silicon nitride.
11. A method of forming a plurality of capacitor devices, comprising: providing a construction comprising a first material over a substrate; forming a retaining structure over at least a portion of the first material; forming openings extending into the first material; forming conductive structures within the openings utilizing a first conductive layer, the conductive structures having outer sidewalls along the first material; removing at least some of the first material to expose at least portions of the outer sidewalls of the conductive structures, the retaining structure retaining the conductive structures during the removal of the first material; forming a capacitor dielectric material along the exposed portions of the outer sidewalls; forming a second conductive layer over the capacitor dielectric material; and wherein: the first material comprises borophosphosilicate glass; an isotropic etch is utilized to remove at least some of the first material; and the retaining structure comprises silicon nitride and a material having increased selectivity to borophosphosilicate glass than silicon nitride during the isotropic etch.
30
12. The method of claim 11 wherein the material having increased selectivity to borophosphosilicate glass than silicon nitride during the isotropic etch consists of silicon.
13. The method of claim 11 wherein the material having increased selectivity to borophosphosilicate glass than silicon nitride during the isotropic etch includes polycrystalline silicon.
14. The method of claim 13 wherein the polycrystalline silicon is over the silicon nitride.
15. The method of claim 13 wherein the polycrystalline silicon is under the silicon nitride.
16. The method of claim 13 wherein the polycrystalline silicon is over and under the silicon nitride.
17. The method of claim 13 wherein the polycrystalline silicon entirely surrounds the silicon nitride.
18. The method of claim 13 further comprising removing the retaining structure from over the first material after forming the second conductive layer.
19. A method of forming a plurality of capacitor devices, comprising: providing a construction comprising a first material over a substrate; forming openings extending into the first material; the openings being arranged in an array consisting of linear rows and linear columns; forming a first conductive layer within the openings, the first conductive layer within the openings forming container structures having outer sidewalls along the first material wherein the container structures are formed in the array defined by the openings and thus the container structures are within an array comprising rows and columns; providing a retaining structure which extends between and connects alternating pairs of the rows of the container structure array, the retaining structure being directly against the first conductive layer of the container structures; removing at least some of the first material to expose at least portions of the outer sidewalls of the container structures, the retaining structure retaining the container structures during the removal of the first material; forming a capacitor dielectric material along the exposed portions of the outer sidewalls and within the container structures; and forming a second conductive layer over the capacitor dielectric material.
20. The method of claim 19 wherein the retaining structure is beneath the first material.
21. The method of claim 19 wherein the retaining structure is over the first material.
22. The method of claim 21 wherein the retaining structure is a second retaining structure; and wherein a first retaining structure is beneath at least some of the first material.
23. The method of claim 19 wherein the first material comprises one or more of borophosphosilicate glass, spin-on-glass, silicon dioxide, phosphosilicate glass, borosilicate glass, and silicon nitride.
24. The method of claim 19 wherein the retaining structure comprises silicon nitride.
25. The method of claim 24 wherein the silicon nitride has a thickness of from 5θA to 3000A.
26. The method of claim 19 wherein the first material comprises borophosphosilicate glass and the retaining structure comprises silicon nitride.
27. The method of claim 19 wherein the first material comprises borophosphosilicate glass, wherein a wet etch is utilized to remove at least some of the first material; and wherein the retaining structure comprises silicon nitride and a material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch.
28. The method of claim 27 wherein the material having increased selectivity to borophosphosilicate glass than silicon nitride during the wet etch is a silicon-containing material.
29. The method of claim 28 wherein the silicon-containing material is over the silicon nitride.
30. The method of claim 29 wherein the silicon-containing material has a thickness of from 5θA to 10OOA.
31. The method of claim 29 wherein the silicon-containing material has a thickness of from 5θA to 10OOA; and wherein the silicon nitride has a thickness of from 5θA to 3000A.
32. The method of claim 28 wherein the silicon-containing material is under the silicon nitride.
33. The method of claim 28 wherein the silicon-containing material is over and under the silicon nitride.
34. The method of claim 33 wherein the silicon-containing material below the silicon nitride has a thickness of from 5θA to 50θA; wherein the silicon-containing material above the silicon nitride has a thickness of from 5θA to 50θA; and wherein the silicon nitride has a thickness of from 5θA to 10OOA.
35. The method of claim 28 wherein the silicon-containing material entirely surrounds the silicon nitride.
32
36. A method of forming a plurality of capacitor devices, comprising: providing a construction comprising a memory array region, a region other than the memory array region and a location between the memory array region and said other region; forming a first material extending over the memory array region, over said other region, and over the location between the memory array region and said other region; forming a second material over at least a portion of the first material that is over the memory array region and over an entirety of the first material that is over said other region; forming openings extending into the first material over the memory array region and forming a trench within the first material over the location between the memory array region and said other region; said trench being formed simultaneously with the forming of said openings; forming a first conductive layer within the openings and within the trench, the first conductive layer within the openings forming container structures having outer sidewalls along the first material; after forming the first conductive layer and the second material, removing at least some of the first material to expose at least portions of the outer sidewalls of the container structures; forming a capacitor dielectric material along the exposed portions of the outer sidewalls and within the container structures; and forming a second conductive layer over the capacitor dielectric material.
37. The method of claim 36 wherein the second material comprises silicon nitride.
38. The method of claim 37 wherein the second conductive layer and the dielectric material are formed over the second material.
39. The method of claim 36 wherein the first material comprises borophosphosilicate glass; wherein an isotropic etch is utilized to remove the at least some of the first material; wherein the second material is incorporated into a retaining structure comprising the second material and a third material; wherein the second material comprises silicon nitride; and wherein the third material has increased selectivity to borophosphosilicate glass than does silicon nitride during the isotropic etch.
40. The method of claim 39 wherein the third material comprises one or both of amorphous silicon and polycrystalline silicon.
41. The method of claim 39 wherein the third material is over the silicon nitride.
42. The method of claim 39 wherein the third material is under the silicon nitride.
33
43. The method of claim 39 wherein the third material is over and under the silicon nitride.
44. The method of claim 36 wherein the first conductive layer comprises titanium nitride.
45. A semiconductor construction, comprising: a monocrystalline silicon substrate having a memory array region defined therein together with a region other than the memory array region and a location between the memory array region and said other region, said memory array region having a lateral periphery defined to entirely laterally surround the memory array region; an electrically insulative material over said other region, the electrically insulative material having a lateral sidewall extending around the lateral periphery of the memory array region, the lateral sidewall physically contacting the monocrystalline silicon of the substrate; and an electrically conductive liner along the sidewall of the material; the electrically conductive liner laterally surrounding the lateral periphery of the memory array region; the electrically conductive liner physically contacting the monocrystalline silicon of the substrate.
46. The construction of claim 45 further comprising a silicon-nitride containing material over an entirety of said other region and in direct physical contact with the electrically conductive liner.
47. The construction of claim 45 wherein said electrically insulative material comprises BPSG, and wherein the silicon nitride-containing material is over the electrically insulative material.
48. The construction of claim 45 wherein the electrically conductive liner comprises titanium nitride.
49. Canceled.
50. The construction of claim 45 wherein the electrically conductive liner consists of titanium nitride.
51. Canceled.
52. A semiconductor construction, comprising: a substrate having a memory array region defined therein together with a region other than the memory array region and a location between the memory array region and said other region, said memory array region having a lateral periphery defined to entirely laterally surround the memory array region; an electrically insulative material over said other region, the electrically insulative material having a lateral sidewall extending around the lateral periphery of the memory array region;
34 an electrically conductive liner along the sidewall of the material; the electrically conductive liner laterally surrounding the lateral periphery of the memory array region; the electrically conductive liner being part of a trough; the trough having a first sidewall corresponding to the electrically conductive liner and having a second sidewall spaced from the first sidewall; the second sidewall of the trough having an outer surface facing the memory array region and an inner surface facing the first sidewall; and a silicon nitride-containing layer directly against the outer surface of the second sidewall of the trough and extending toward the memory array region from the outer surface of the second sidewall of the trough.
53. The construction of claim 52 further comprising a plurality of capacitor constructions over the memory array region; the capacitor constructions extending in an array comprising rows and columns; the capacitor constructions comprising storage nodes which extend in the rows and columns of the array; and wherein the silicon nitride-containing layer extends between and connects alternating pairs of the rows of storage nodes of the array.
54. The construction of claim 45 further comprising a lateral periphery defined to entirely laterally surround said other region, and wherein the electrically conductive liner laterally surrounds the lateral periphery of said other region.
55. The construction of claim 54 wherein the electrically conductive liner comprises titanium nitride.
56. Canceled.
57. The construction of claim 54 wherein the electrically conductive liner consists of titanium nitride.
58. The construction of claim 54 wherein the electrically conductive liner is part of a trough; the trough having first sidewall corresponding to the electrically conductive liner and a second sidewall spaced from the first sidewall.
59. A semiconductor construction, comprising: a monocrystalline silicon substrate having a memory array region defined therein together with a region other than the memory array region and a location between the memory array region and said other region; a plurality of container structures across the memory array region; the container structures being electrically conductive and comprising inner sidewalls within the container structures and outer sidewalls in opposing relation to the inner sidewalls; an electrically insulative material over said other region, the electrically insulative material having a lateral sidewall extending to physically contact monocrystalline silicon of the substrate;
35 an electrically conductive liner along the sidewall of the material; the electrically conductive liner physically contacting monocrystalline silicon of the substrate; a capacitor dielectric material along the inner and outer sidewalls of the container structures; and a second conductive layer over the capacitor dielectric material; the container structures, dielectric material and second conductive material together being incorporated into a plurality of capacitor constructions.
60. The construction of claim 59 wherein the memory array region has a lateral periphery defined to entirely laterally surround the memory array region; and wherein the electrically conductive liner laterally surrounds an entirety of the lateral periphery of the memory array region.
61. The construction of claim 59 further comprising a silicon-nitride containing material over an entirety of said other region and in direct physical contact with the electrically conductive liner.
62. The construction of claim 59 wherein said electrically insulative material comprises BPSG, and wherein the silicon nitride-containing material is over the electrically insulative material.
63. The construction of claim 59 wherein the electrically conductive liner and the capacitor containers comprise titanium nitride.
64. The construction of claim 59 wherein the electrically conductive liner comprises titanium nitride.
65. Canceled.
66. The construction of claim 59 wherein the electrically conductive liner consists of titanium nitride.
67. Canceled.
68. A semiconductor construction, comprising: a substrate having a memory array region defined therein together with a region other than the memory array region and a location between the memory array region and said other region; a plurality of container structures across the memory array region; the container structures being electrically conductive and comprising inner sidewalls within the container structures and outer sidewalls in opposing relation to the inner sidewalls; an electrically insulative material over said other region, the electrically insulative material having a lateral sidewall; an electrically conductive liner along the sidewall of the material; the electrically conductive liner being part of a trough; the trough having a first sidewall corresponding to the electrically conductive liner and a second sidewall spaced from the first sidewall;
36 the second sidewall having an outer surface facing the memory array region and an inner surface facing the first sidewall; a capacitor dielectric material along the inner and outer sidewalls of the container structures; a second conductive layer over the capacitor dielectric material; the container structures, dielectric material and second conductive material together being incorporated into a plurality of capacitor constructions; and a silicon nitride-containing layer directly against the outer surface of the second sidewall of the trough and extending toward the memory array region from the outer surface of the second sidewall of the trough.
69. The construction of claim 68 wherein the container structures extend in an array comprising rows and columns; and wherein the silicon nitride-containing layer extends between and connects alternating pairs of the rows of the container structure array.
70. The construction of claim 68 further comprising at least one layer consisting of silicon directly against the silicon nitride-containing layer.
71. The construction of claim 68 further comprising: a first layer consisting of silicon over and directly against the silicon nitride- containing layer; and a second layer consisting of silicon under and directly against the silicon nitride- containing layer.
37
PCT/US2004/040252 2003-12-10 2004-12-01 Containing capacitors and method of forming WO2005062349A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04812703.9A EP1700332B1 (en) 2003-12-10 2004-12-01 Capacitors and method of forming the same
JP2006542721A JP5007465B2 (en) 2003-12-10 2004-12-01 Method for forming capacitor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/733,181 US7125781B2 (en) 2003-09-04 2003-12-10 Methods of forming capacitor devices
US10/733,181 2003-12-10

Publications (2)

Publication Number Publication Date
WO2005062349A1 WO2005062349A1 (en) 2005-07-07
WO2005062349B1 true WO2005062349B1 (en) 2005-09-15

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Country Status (7)

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US (4) US7125781B2 (en)
EP (1) EP1700332B1 (en)
JP (2) JP5007465B2 (en)
KR (1) KR100868812B1 (en)
CN (1) CN100405541C (en)
TW (1) TWI252511B (en)
WO (1) WO2005062349A1 (en)

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