WO2005076816A3 - Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system - Google Patents

Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system Download PDF

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Publication number
WO2005076816A3
WO2005076816A3 PCT/US2005/002410 US2005002410W WO2005076816A3 WO 2005076816 A3 WO2005076816 A3 WO 2005076816A3 US 2005002410 W US2005002410 W US 2005002410W WO 2005076816 A3 WO2005076816 A3 WO 2005076816A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
write
memory
write data
hub
Prior art date
Application number
PCT/US2005/002410
Other languages
French (fr)
Other versions
WO2005076816A2 (en
Inventor
Douglas A Larson
Jeffrey J Cronin
Original Assignee
Micron Technology Inc
Douglas A Larson
Jeffrey J Cronin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Douglas A Larson, Jeffrey J Cronin filed Critical Micron Technology Inc
Priority to JP2006552148A priority Critical patent/JP4568290B2/en
Priority to EP05712043.8A priority patent/EP1725936B1/en
Publication of WO2005076816A2 publication Critical patent/WO2005076816A2/en
Publication of WO2005076816A3 publication Critical patent/WO2005076816A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Abstract

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
PCT/US2005/002410 2004-02-05 2005-01-25 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system WO2005076816A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006552148A JP4568290B2 (en) 2004-02-05 2005-01-25 Apparatus and method for data bypass for a bidirectional data bus in a hub-based memory subsystem
EP05712043.8A EP1725936B1 (en) 2004-02-05 2005-01-25 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/773,583 US7788451B2 (en) 2004-02-05 2004-02-05 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US10/773,583 2004-02-05

Publications (2)

Publication Number Publication Date
WO2005076816A2 WO2005076816A2 (en) 2005-08-25
WO2005076816A3 true WO2005076816A3 (en) 2007-03-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/002410 WO2005076816A2 (en) 2004-02-05 2005-01-25 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

Country Status (7)

Country Link
US (4) US7788451B2 (en)
EP (2) EP1725936B1 (en)
JP (1) JP4568290B2 (en)
KR (1) KR100855193B1 (en)
CN (1) CN100578466C (en)
TW (1) TWI321727B (en)
WO (1) WO2005076816A2 (en)

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US20140207993A1 (en) 2014-07-24
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