WO2005082063A3 - Long range corrections in integrated circuit layout designs - Google Patents

Long range corrections in integrated circuit layout designs Download PDF

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Publication number
WO2005082063A3
WO2005082063A3 PCT/US2005/006168 US2005006168W WO2005082063A3 WO 2005082063 A3 WO2005082063 A3 WO 2005082063A3 US 2005006168 W US2005006168 W US 2005006168W WO 2005082063 A3 WO2005082063 A3 WO 2005082063A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
flare
long range
circuit layout
layout designs
Prior art date
Application number
PCT/US2005/006168
Other languages
French (fr)
Other versions
WO2005082063A2 (en
Inventor
James Word
Nicolas B Cobb
Yuri Granik
Original Assignee
Mentor Graphics Corp
James Word
Nicolas B Cobb
Yuri Granik
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp, James Word, Nicolas B Cobb, Yuri Granik filed Critical Mentor Graphics Corp
Priority to EP05723855A priority Critical patent/EP1723568A4/en
Priority to JP2007501020A priority patent/JP4993602B2/en
Publication of WO2005082063A2 publication Critical patent/WO2005082063A2/en
Publication of WO2005082063A3 publication Critical patent/WO2005082063A3/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method and apparatus for compensating for flare intensity variations across an integrated circuit. A layout description for a physical layer of an integrated circuit or p on thereof is divided into a number of regions such as adjacent tiles. An estimate of the flare intensity in each region is determined. The flare intensity values calculated are divided into a number of ranges. In one embodiment, a data layer in a layout description is defined for each range of flare values computed . Features to be printed in an area having a flare value in a particular range are associated with a corresponding additional date layer. The features associated with each additional data layer are analyzed with a resolution enhancement technique that is selected or adjusted to compensate for differing flare values occurring in the integrated circuit.
PCT/US2005/006168 2004-02-25 2005-02-25 Long range corrections in integrated circuit layout designs WO2005082063A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05723855A EP1723568A4 (en) 2004-02-25 2005-02-25 Long range corrections in integrated circuit layout designs
JP2007501020A JP4993602B2 (en) 2004-02-25 2005-02-25 Long-range correction in integrated circuit layout design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54748404P 2004-02-25 2004-02-25
US60/547,484 2004-02-25

Publications (2)

Publication Number Publication Date
WO2005082063A2 WO2005082063A2 (en) 2005-09-09
WO2005082063A3 true WO2005082063A3 (en) 2006-04-27

Family

ID=34910901

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/006168 WO2005082063A2 (en) 2004-02-25 2005-02-25 Long range corrections in integrated circuit layout designs

Country Status (4)

Country Link
US (1) US7234130B2 (en)
EP (1) EP1723568A4 (en)
JP (2) JP4993602B2 (en)
WO (1) WO2005082063A2 (en)

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JP2012164767A (en) 2011-02-04 2012-08-30 Toshiba Corp Flare prediction method, photomask fabrication method, semiconductor device manufacturing method, and flare prediction program
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US9355201B2 (en) 2012-08-17 2016-05-31 Mentor Graphics Corporation Density-based integrated circuit design adjustment
US8627245B1 (en) * 2012-08-28 2014-01-07 International Business Machines Corporation Density balancing in multiple patterning lithography using integrated circuit layout fill
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US8856695B1 (en) * 2013-03-14 2014-10-07 Samsung Electronics Co., Ltd. Method for generating post-OPC layout in consideration of top loss of etch mask layer
US9977325B2 (en) * 2015-10-20 2018-05-22 International Business Machines Corporation Modifying design layer of integrated circuit (IC)

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See also references of EP1723568A4 *

Also Published As

Publication number Publication date
US7234130B2 (en) 2007-06-19
JP4993602B2 (en) 2012-08-08
JP2012089892A (en) 2012-05-10
EP1723568A2 (en) 2006-11-22
WO2005082063A2 (en) 2005-09-09
JP5619795B2 (en) 2014-11-05
JP2007524255A (en) 2007-08-23
EP1723568A4 (en) 2010-06-02
US20050216878A1 (en) 2005-09-29

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