WO2005086227A8 - Technique d’amelioration de la qualite d’une couche mince prelevee - Google Patents

Technique d’amelioration de la qualite d’une couche mince prelevee

Info

Publication number
WO2005086227A8
WO2005086227A8 PCT/FR2005/000542 FR2005000542W WO2005086227A8 WO 2005086227 A8 WO2005086227 A8 WO 2005086227A8 FR 2005000542 W FR2005000542 W FR 2005000542W WO 2005086227 A8 WO2005086227 A8 WO 2005086227A8
Authority
WO
WIPO (PCT)
Prior art keywords
layer
stage
taken
donor wafer
improving
Prior art date
Application number
PCT/FR2005/000542
Other languages
English (en)
Other versions
WO2005086227A1 (fr
Inventor
Nicolas Daval
Takeshi Akatsu
Nguyet-Phuong Nguyen
Olivier Rayssac
Konstantin Bourdelle
Original Assignee
Soitec Silicon On Insulator
Nicolas Daval
Takeshi Akatsu
Nguyet-Phuong Nguyen
Olivier Rayssac
Konstantin Bourdelle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0402340A external-priority patent/FR2867307B1/fr
Application filed by Soitec Silicon On Insulator, Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen, Olivier Rayssac, Konstantin Bourdelle filed Critical Soitec Silicon On Insulator
Priority to EP05737045A priority Critical patent/EP1721333A1/fr
Priority to CN2005800141634A priority patent/CN1950937B/zh
Priority to JP2007501319A priority patent/JP4876067B2/ja
Priority to US11/179,713 priority patent/US7449394B2/en
Publication of WO2005086227A1 publication Critical patent/WO2005086227A1/fr
Publication of WO2005086227A8 publication Critical patent/WO2005086227A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

L'invention concerne un procédé de formation d'une structure (30) comprenant une couche prélevée (2) à partir d'une plaquette donneuse (10), la plaquette donneuse (10) comprenant avant prélèvement une première couche (1) et une deuxième couche (2) en matériaux différents. Le procédé comprend les étapes suivantes (a) implantation d'espèces atomiques pour former une zone de fragilisation (4) sous la deuxième couche (2); (b) collage de la plaquette donneuse (10) à une plaquette réceptrice (20); (c) apport d'énergie pour désolidariser les couches prélevées (1', 2) de la plaquette donneuse (10) au niveau de la zone de fragilisation (4); (d) gravure sélective de la partie restante de la première couche (1') vis à vis de la deuxième couche (2). Le procédé comprend en outre une étape apte à renforcer le collage, mise en œuvre à une température inférieure à environ 800 °C. Les paramètres de l'implantation réalisée lors de l'étape (a) sont ajustés de sorte à minimiser les rugosités apparaissant immédiatement après la mise en œuvre de l'étape (c).
PCT/FR2005/000542 2004-03-05 2005-03-07 Technique d’amelioration de la qualite d’une couche mince prelevee WO2005086227A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP05737045A EP1721333A1 (fr) 2004-03-05 2005-03-07 Technique d'amelioration de la qualite d'une couche mince prelevee
CN2005800141634A CN1950937B (zh) 2004-03-05 2005-03-07 用于改善剥离薄层的质量的方法
JP2007501319A JP4876067B2 (ja) 2004-03-05 2005-03-07 採取薄膜の品質改善処理方法
US11/179,713 US7449394B2 (en) 2004-03-05 2005-07-11 Atomic implantation and thermal treatment of a semiconductor layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0402340A FR2867307B1 (fr) 2004-03-05 2004-03-05 Traitement thermique apres detachement smart-cut
FR0402340 2004-03-05
FR0409980A FR2867310B1 (fr) 2004-03-05 2004-09-21 Technique d'amelioration de la qualite d'une couche mince prelevee
FR0409980 2004-09-21

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/059,122 Continuation-In-Part US7276428B2 (en) 2004-03-05 2005-02-16 Methods for forming a semiconductor structure

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/179,713 Continuation US7449394B2 (en) 2004-03-05 2005-07-11 Atomic implantation and thermal treatment of a semiconductor layer

Publications (2)

Publication Number Publication Date
WO2005086227A1 WO2005086227A1 (fr) 2005-09-15
WO2005086227A8 true WO2005086227A8 (fr) 2006-10-19

Family

ID=34863204

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/FR2005/000541 WO2005086226A1 (fr) 2004-03-05 2005-03-07 Traitement thermique d’amelioration de la qualite d’une couche mince prelevee
PCT/FR2005/000542 WO2005086227A1 (fr) 2004-03-05 2005-03-07 Technique d’amelioration de la qualite d’une couche mince prelevee

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/FR2005/000541 WO2005086226A1 (fr) 2004-03-05 2005-03-07 Traitement thermique d’amelioration de la qualite d’une couche mince prelevee

Country Status (6)

Country Link
US (2) US7276428B2 (fr)
EP (2) EP1721333A1 (fr)
JP (2) JP2007526644A (fr)
KR (1) KR100860271B1 (fr)
FR (1) FR2867310B1 (fr)
WO (2) WO2005086226A1 (fr)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
FR2837981B1 (fr) * 2002-03-28 2005-01-07 Commissariat Energie Atomique Procede de manipulation de couches semiconductrices pour leur amincissement
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
EP1894234B1 (fr) * 2005-02-28 2021-11-03 Silicon Genesis Corporation Procédé de rigidification du substrat et système pour un transfert de couche.
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
FR2892230B1 (fr) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator Traitement d'une couche de germamium
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
FR2896618B1 (fr) 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
FR2896619B1 (fr) 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
FR2898431B1 (fr) * 2006-03-13 2008-07-25 Soitec Silicon On Insulator Procede de fabrication de film mince
EP1835533B1 (fr) 2006-03-14 2020-06-03 Soitec Méthode de fabrication de plaquettes composites et procédé de recyclage d'un substrat donneur usagé
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
TW200802544A (en) * 2006-04-25 2008-01-01 Osram Opto Semiconductors Gmbh Composite substrate and method for making the same
US20070277874A1 (en) * 2006-05-31 2007-12-06 David Francis Dawson-Elli Thin film photovoltaic structure
US20070298586A1 (en) * 2006-06-21 2007-12-27 Nissan Motor Co., Ltd. Method of manufacturing semiconductor device
US20080070340A1 (en) * 2006-09-14 2008-03-20 Nicholas Francis Borrelli Image sensor using thin-film SOI
US20080173895A1 (en) * 2007-01-24 2008-07-24 Sharp Laboratories Of America, Inc. Gallium nitride on silicon with a thermal expansion transition buffer layer
JP2008198656A (ja) * 2007-02-08 2008-08-28 Shin Etsu Chem Co Ltd 半導体基板の製造方法
US8664073B2 (en) 2007-03-28 2014-03-04 United Microelectronics Corp. Method for fabricating field-effect transistor
US7888223B2 (en) * 2007-03-28 2011-02-15 United Microelectronics Corp. Method for fabricating P-channel field-effect transistor (FET)
FR2923079B1 (fr) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech Substrats soi avec couche fine isolante enterree
US7998835B2 (en) * 2008-01-15 2011-08-16 Globalfoundries Singapore Pte. Ltd. Strain-direct-on-insulator (SDOI) substrate and method of forming
JP5466410B2 (ja) * 2008-02-14 2014-04-09 信越化学工業株式会社 Ｓｏｉ基板の表面処理方法
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
FR2931585B1 (fr) * 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100044827A1 (en) * 2008-08-22 2010-02-25 Kinik Company Method for making a substrate structure comprising a film and substrate structure made by same method
TWI479552B (zh) * 2008-09-05 2015-04-01 Kinik Co 表面平滑處理方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
GB2467935B (en) 2009-02-19 2013-10-30 Iqe Silicon Compounds Ltd Formation of thin layers of GaAs and germanium materials
TWI451474B (zh) * 2009-12-14 2014-09-01 Tien Hsi Lee 一種製作可轉移性晶體薄膜的方法
US20110207306A1 (en) * 2010-02-22 2011-08-25 Sarko Cherekdjian Semiconductor structure made using improved ion implantation process
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
US8008175B1 (en) 2010-11-19 2011-08-30 Coring Incorporated Semiconductor structure made using improved simultaneous multiple ion implantation process
US8558195B2 (en) 2010-11-19 2013-10-15 Corning Incorporated Semiconductor structure made using improved pseudo-simultaneous multiple ion implantation process
US8196546B1 (en) 2010-11-19 2012-06-12 Corning Incorporated Semiconductor structure made using improved multiple ion implantation process
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
FR2980916B1 (fr) 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
FR2982071B1 (fr) * 2011-10-27 2014-05-16 Commissariat Energie Atomique Procede de lissage d'une surface par traitement thermique
US9147803B2 (en) 2013-01-02 2015-09-29 Micron Technology, Inc. Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods
WO2015178857A1 (fr) * 2014-05-23 2015-11-26 Massachusetts Institute Of Technology Procédé de fabrication d'un substrat de germanium-sur-isolant
FR3045934B1 (fr) * 2015-12-22 2018-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d’un empilement de dispositifs electroniques
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
CN112262467A (zh) * 2018-06-08 2021-01-22 环球晶圆股份有限公司 将硅薄层移转的方法
FR3134229B1 (fr) * 2022-04-01 2024-03-08 Commissariat Energie Atomique Procede de transfert d’une couche mince sur un substrat support

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4462847A (en) * 1982-06-21 1984-07-31 Texas Instruments Incorporated Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition
US4604304A (en) * 1985-07-03 1986-08-05 Rca Corporation Process of producing thick layers of silicon dioxide
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
JPS63185588A (ja) 1987-01-27 1988-08-01 松下電工株式会社 電動ドリルドライバ−
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH06318588A (ja) 1993-03-11 1994-11-15 Nec Corp 半導体装置の製造方法
US6155909A (en) * 1997-05-12 2000-12-05 Silicon Genesis Corporation Controlled cleavage system using pressurized fluid
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP3412470B2 (ja) * 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
JPH11150287A (ja) * 1997-09-10 1999-06-02 Canon Inc 太陽電池モジュール、太陽電池付き外囲体、太陽電池付き外囲体の設置方法、及び太陽光発電システム
FR2773261B1 (fr) * 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
JP3582566B2 (ja) * 1997-12-22 2004-10-27 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
FR2774510B1 (fr) * 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP3456521B2 (ja) * 1998-05-12 2003-10-14 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
US6989294B1 (en) * 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
JP3358550B2 (ja) 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6352942B1 (en) * 1999-06-25 2002-03-05 Massachusetts Institute Of Technology Oxidation of silicon on germanium
JP2003506883A (ja) * 1999-08-10 2003-02-18 シリコン ジェネシス コーポレイション 低打ち込みドーズ量を用いて多層基板を製造するための劈開プロセス
DE10031388A1 (de) * 2000-07-03 2002-01-17 Bundesdruckerei Gmbh Handsensor für die Echtheitserkennung von Signets auf Dokumenten
EP1309989B1 (fr) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
FR2835096B1 (fr) * 2002-01-22 2005-02-18 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin
US6448152B1 (en) * 2001-02-20 2002-09-10 Silicon Genesis Corporation Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US7238622B2 (en) * 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
JP5055671B2 (ja) * 2001-07-26 2012-10-24 信越半導体株式会社 Ｓｏｉ基板の製造方法
JP2003078116A (ja) * 2001-08-31 2003-03-14 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
JP2003324199A (ja) * 2002-05-01 2003-11-14 Sony Corp 半導体装置の製造方法
FR2839385B1 (fr) 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau
WO2003105189A2 (fr) 2002-06-07 2003-12-18 Amberwave Systems Corporation Structures de dispositif a semi-conducteurs contraints sur isolant
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2842349B1 (fr) 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
FR2842350B1 (fr) 2002-07-09 2005-05-13 Procede de transfert d'une couche de materiau semiconducteur contraint
JP5005170B2 (ja) 2002-07-19 2012-08-22 エーエスエム アメリカ インコーポレイテッド 超高品質シリコン含有化合物層の形成方法
WO2004021420A2 (fr) * 2002-08-29 2004-03-11 Massachusetts Institute Of Technology Systeme de fabrication ameliore et procede pour semi-conducteur monocristallin sur un substrat
FR2844634B1 (fr) 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer

Also Published As

Publication number Publication date
WO2005086226A8 (fr) 2006-10-26
US20050245049A1 (en) 2005-11-03
KR100860271B1 (ko) 2008-09-25
EP1733423A1 (fr) 2006-12-20
EP1721333A1 (fr) 2006-11-15
JP2007526644A (ja) 2007-09-13
JP2007526645A (ja) 2007-09-13
WO2005086227A1 (fr) 2005-09-15
US7276428B2 (en) 2007-10-02
FR2867310A1 (fr) 2005-09-09
FR2867310B1 (fr) 2006-05-26
KR20070085086A (ko) 2007-08-27
JP4876067B2 (ja) 2012-02-15
US7449394B2 (en) 2008-11-11
US20050196937A1 (en) 2005-09-08
WO2005086226A1 (fr) 2005-09-15

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