WO2005086228A1 - Traitement thermique apres detachement smart-cut - Google Patents
Traitement thermique apres detachement smart-cut Download PDFInfo
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- WO2005086228A1 WO2005086228A1 PCT/FR2005/000543 FR2005000543W WO2005086228A1 WO 2005086228 A1 WO2005086228 A1 WO 2005086228A1 FR 2005000543 W FR2005000543 W FR 2005000543W WO 2005086228 A1 WO2005086228 A1 WO 2005086228A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a process for forming a structure comprising a layer of semiconductor material taken from a donor wafer, the process comprising the following successive steps: a) implantation of atomic species to form a weakening zone in the donor wafer at a determined depth; b) bonding of the donor plate to a receiving plate; c) supply of energy to detach or separate the layer removed from the donor wafer at the embrittlement zone; d) treatment of the sampled layer.
- This type of diaper removal is also called Smart-Cut®, and is known to those skilled in the art.
- Step (b) of bonding the receiving wafer (of the removed layer), is typically done at the surface of the donor wafer having undergone implantation, by means of a bonding layer of material dielectric, such as Si0 2 .
- a semiconductor-on-insulator structure such as an SOI structure (in the case where the sampled layer is made of silicon), SiGeOI (in the case where the sampled layer is made of germanium silicon), sSOI (in the case where the sampled layer is in constrained silicon), SGOI (in the case where the sampled layer comprises a layer of relaxed SiGe on which a layer of constrained Si rests) or GeOI (in the case where the sampled layer is in germanium).
- the energy is at least partially supplied, during step (c), in thermal form. This is the thermal budget (the couple temperature / duration of heat treatment) which must be taken into account when determining when the layer to be removed will come off.
- a semiconductor-on-insulator structure 30 is schematically represented (consisting of a receiving plate 20 covered with the sampled layer 1 by means of an electrically insulating layer 5) which has, in its part semiconductor (ie the sampled layer 1), such a reduction in crystal quality. It can thus be observed that the sampled layer 1 comprises a defective zone 1A, this defective zone 1A comprising crystalline defects and an existing surface roughness.
- the defective zone has a thickness typically around 150 nm.
- the implantation step may have caused the layer to be removed to decrease the crystal quality.
- the defective area must be completely removed after detachment, in particular due to the defects present in the sampled layer. It is thus common to take a layer of greater thickness in order to completely remove these defects during finishing operations carried out after detachment.
- the production of a structure comprising a layer taken from 500 angstroms thick requires the transfer from 2000 to 2500 angstroms and the removal from 1500 to 2000 angstroms, for example by polishing, selective etching or sacrificial oxidation.
- Step (d) for processing the removed layer 1 is thus conventionally implemented to remove this defective area 1A, and thus recover at least part of the healthy zone 1 B of the sampled layer 1.
- an oxidation of the defective zone 1A will be implemented first, which will be removed later by means of chemical etching by using hydrofluoric acid HF (thus carrying out a treatment known as “sacrificial oxidation”), then a finishing, by means for example of a mechanical or mechanical-chemical polishing.
- a step (d) of processing the removed layer 1 is thus complex and costly from an economic point of view.
- the implementation of these processing means requires systematically removing the negative from the donor wafer to gain access to the surface of the removed layer 1, and therefore requires removing from the oven (in which the heat treatment of the step (c) has been carried out) the platelets, which represents a waste of time, additional handling of the platelets, and the need to use appropriate equipment.
- Document FR 2 842 349 attempts to overcome these problems by including in the layer to be sampled in SiGe, and between the future defective zone 1 A and the future healthy zone 1B underlying, a stop layer in Si, in order to improve the finishing operations implemented during step (d), by means of a selective double etching (of the defective zone 1 A and of the stop layer) which substantially reduces the roughness measured according to their maximum values (the “peaks to valleys”) and according to their quadratic values (in RMS Angstroms) on the surface of the healthy zone 1 B of SiGe.
- the sampled layer 1 consists of a healthy zone 1B in constrained Si and a defective zone 1A in SiGe, the latter zone then being selectively removed with respect to the healthy zone 1 B.
- step (a) of implantation by implantation of several atomic species (typically by carrying out an implantation of helium and an implantation of hydrogen). This type of implantation is hereinafter designated by the term co-implantation.
- the implementation of a co-implantation in fact makes it possible to use a total dose of co-implanted species lower than the dose used when a single species is implanted.
- the total dose in co-implantation thus typically represents 1/3 of the dose in implantation of a single species.
- the result of this reduction in the total implanted dose is a reduction in the thickness of the defective zone, which in particular makes it possible to reduce or simplify the finishing treatments implemented after detachment.
- a compromise must be made between roughness and the formation of these defects, and the use of co-location therefore does not as such make it possible to satisfactorily resolve the problems mentioned above relating to the presence defects and surface roughness.
- the present invention attempts to overcome these problems by proposing, according to a first aspect, a method for forming a structure comprising a layer taken from material chosen from semiconductor materials from a donor wafer, the method comprising the following steps: ( a) implantation of atomic species to form a zone of embrittlement in the donor wafer at a depth close to the thickness of the layer to be sampled; (b) bonding of the donor wafer to a recipient wafer; (c) providing thermal energy to separate the layer removed from the donor wafer at the embrittlement zone; (d) processing the removed layer; characterized in that step (d) comprises an operation for healing the removed sample layer implemented while the removed layer is still in contact with the remaining part of the donor wafer, and in that the healing operation is implementation by heat treatment at a temperature below the re-a
- re-adhesion temperature is of the order of 800 ° C
- step (c) is carried out at a temperature between 300 ° C and 550 ° C
- - the healing temperature is between 350 ° C and 800 ° C
- - the healing temperature is between 550 ° C and 800 ° C;
- the healing operation is done in an inert atmosphere, such as an Ar or N 2 atmosphere;
- step (d) the healing operation takes place in an oxidizing atmosphere; the healing operation of step (d) is carried out in continuity with step (c), in the same oven;
- step (d) comprises a simple change in the temperature from the separation temperature of step (c) to the chosen healing temperature;
- step (c) is implemented around 500 ° C for a period which can range from approximately 30 minutes to approximately 2 hours;
- - step (a) includes a simple implantation of hydrogen or helium; - step (a) comprises a co-implantation of hydrogen and helium;
- step (d) The healing operation of step (d) is carried out by heat treatment at a temperature substantially between 575 ° C and 625 ° C;
- step (a) is carried out by co-implantation according to conditions suitable for forming the zone of embrittlement in said layer of SiGe and for the helium concentration peak to be located, in the thickness of the donor plate, deeper than the hydrogen spreading zone and also deeper than the embrittlement zone;
- the healing heat treatment is carried out for a period of between 30 minutes and four hours;
- step to remove the contact of the removed layer with the rest of the donor wafer is implemented after the healing operation of step (d), optionally followed by a finishing operation, included in the step (d), comprising at least one of the following operations: CMP, chemical etching, sacrificial oxidation, thermal annealing, - the sampled layer is in Si ⁇ - x Ge x , with 0 ⁇ x ⁇ 1, - the sampled layer comprises Si ⁇ - x Ge x , with x ⁇ O, and a selective etching stop layer, and step (d) comprises such a selective etching carried out after the healing operation, and after removing the contact of the removed layer (1) with the remaining part of the donor plate (10 ′), the donor plate comprises a support substrate in solid Si, a buffer structure in SiGe, and an upper layer comprising Si-i- x Ge x , (x ⁇ O), and the receiving wafer is made of solid Si, - the method further comprises, before step (b), a step of
- the invention proposes an application of said method for forming a structure, to the formation of a semiconductor-on-insulator structure.
- the invention provides a semiconductor-over-insulator structure obtained after the healing operation of the step and after removing the contact of the sampled layer with the remaining part of the donor wafer, having lower roughness at 40 ⁇ RMS.
- FIG. 1 shows a schematic sectional view of a semiconductor-on-insulator structure obtained after the implementation of a Smart-Cut® process according to the prior art
- - Figure 2 shows a sectional view obtained by TEM by the Applicant of a semiconductor-on-insulator structure obtained after the implementation of a method according to the invention
- - Figures 3a to 3f schematically represent the different steps of a method according to the invention to form a structure comprising a layer taken from Smart-Cut®
- - Figure 4 shows a first time evolution of the temperatures of the heat treatments used during the separation step and the healing operation of the layer removed according to the method according to the invention shown in Figures 3a to 3f
- - Figure 5 represents a second temporal evolution of the temperatures of the heat treatments implemented during the separation step and during the healing operation of the layer removed according to the method according to the method according to the
- a first object of the invention is to reduce the duration, the economic cost, and the number of means for processing a layer removed by Smart-Cut®.
- a second objective of the invention is to reduce the amount of material removed during the treatment of the layer removed by Smart-Cut®.
- a third objective of the invention consists in improving the crystalline quality of the sampled layer compared to the state of the art.
- a fourth objective of the invention is to propose a simple method for processing the layer removed by Smart-Cut® and which can be easily integrated into the whole process of removal by Smart-Cut®.
- a fifth objective of the invention is to find a means for implementing a heat treatment for healing the sampled layer both in an inert atmosphere and in an oxidizing atmosphere without substantially altering the properties of the sampled layer.
- a sixth objective of the invention is to produce semiconductor-on-insulator structures having a high crystal quality and a thickness of useful layer which can be very low.
- a seventh objective of the invention is to produce such a semiconductor-on-insulator structure comprising SiGe or Ge for the semiconductor part.
- An eighth objective of the invention is to determine detachment parameters (implantation, energy supply) making it possible both to reduce the thickness of the defective zone, to limit the presence of defects and to minimize the surface roughness.
- a first method of sampling a layer of S _ x Ge x (with x ⁇ 0) is illustrated from a donor plate to transfer it to a receiving plate, according to the invention .
- a donor wafer 10 comprising the Si ⁇ _ x Ge x layer to be sampled (not shown), is illustrated.
- a donor wafer 10 including S _ x Ge x comprises a solid Si substrate on which has been formed a SiGe buffer structure (not shown) composed of different layers, so that the latter has a gradual evolution in thickness of its composition in Ge, ranging from 0% at the level of the solid Si substrate to approximately 100 ⁇ % at the interface with an upper layer of Si-
- the donor wafer 10 can have any other configuration for which a Si ⁇ - x Ge x layer, relaxed or not, is present in its upper part.
- a constrained Si layer is formed, by crystal growth (for example by CVD), on the Si- ⁇ _ x Ge x layer.
- a weakening zone 4 is formed in the donor plate 10 at its upper part in S - ⁇ Ge x . This weakening zone 4 is preferably formed by implantation of atomic species whose dosage, nature, and energy are in particular chosen so as to determine an implant depth and a weakening level.
- the implantation of atomic species can be a simple implantation (ie an implantation of, mainly, a single atomic species), such as for example an implantation of hydrogen, helium or rare gases.
- the implantation of atomic species can be a co-implantation of atomic species (ie an implantation of, mainly, two atomic species), such as for example an implantation of helium followed by an implantation of hydrogen (or vice versa ).
- co-implantation the Applicant has noticed that the weakening zone 4 is generally thinner than in the case of a simple implantation.
- the implant depth is then chosen so as to be close to or greater than the desired thickness of the layer to be sampled 1.
- an implant depth of the order of 300 to 600 nanometers can be obtained.
- an implant depth of the order of 300 to 600 nanometers can be obtained.
- the total dose in co-implantation thus typically represents 1/3 of the dose in implantation of a single species.
- a step of bonding a receiving plate 20 with the side of the donor plate 10 having undergone co-implantation is carried out.
- the receiving plate 20 can be made of solid Si.
- a bonding layer may be formed, such as a layer of Si0 2 , Si 3 N 4 , Si x O y N z on one and / or the other of the Respective surfaces to be glued.
- this or these bonding layer (s) is or are in S1O2
- their formation can be carried out by thermal oxidation or by deposition of Si0 2 .
- Thermal oxidation of the receiving wafer 20 is usually preferred since it implements in most cases an oxidation of Si.
- Thermal oxidation of the donor wafer 10 can be carried out at the level of the layer to be sampled 1 in Si ⁇ - x Ge x .
- a preparation of the surfaces to be bonded Prior to bringing the receiving wafer 20 into contact with the donor wafer 10, a preparation of the surfaces to be bonded can optionally be implemented, using known techniques for cleaning and surface preparation such as solutions SC1 and SC2, ozonated solution, etc. Bonding can be carried out in the first place by molecular adhesion taking into account the hydrophilicity which each of the two surfaces to be bonded presents.
- a heat treatment may possibly be implemented after the healing operation discussed below, to further strengthen the bonding, and in particular by creating covalent bonds. Details of bonding methods that can be used in the context of the invention may in particular be found in the book “Semiconductor wafer bonding science and technology” by KY. Tong and U. Gôsele (Wiley interscience publication, Johnson Wiley &
- the stage of separation is carried out by means of a supply of thermal energy and / or a mechanical energy, sufficient to break the weak bonds at the level of the weakening zone 4, and thus to separate the sampled layer 1 from the rest of the donor wafer 10 '.
- the contribution of thermal energy is for example then sufficient to cause, at the level of the embrittlement zone 4, thermal effects on the gaseous species which are enclosed therein causing the weak bonds to be broken, without it being necessary to make mechanical intervention.
- the separation can be obtained at temperatures between about 300 ° C and about 550 ° C for longer or shorter times depending on whether, respectively, the temperature is lower or higher.
- a heat treatment at a temperature of about 500 ° C for a period which can range from 15 to 30 minutes up to 2 hours.
- a healing operation will be implemented by heat treatment at a chosen temperature T 2 below the re-adhesion temperature from which the layer removed 1 re-adheres (or resolidates) with the remaining part of the donor plate 10 '.
- the re-adhesion temperature is considered here, within the framework of the invention, and based on experiments carried out by the Applicant, equal to approximately 800 ° C.
- This heat treatment for healing the removed layer 1 is carried out in an inert atmosphere (such as an Ar or N 2 atmosphere), slightly oxidizing or oxidizing.
- the temperature T 2 can be higher than the temperature Ti to which the plates 10 and 20 were subjected during the joining step.
- the temperature T2 can thus for example be between 350 ° C and 800 ° C, maintained for 30 minutes to 4 hours.
- the temperature T 2 can more particularly be between 550 ° C. and 800 ° C.
- the remaining part of the donor plate 10 ′ is removed from contact with the removed and cured layer 1 ′, to finally obtain a structure 30, comprising a removed and cured layer Y in Si ⁇ _ x Ge x and the receiving wafer 20.
- This structure 30 has an improved crystalline quality and a reduced roughness, without there being any need to carry out an intermediate sacrificial oxidation operation and therefore without there being any significant loss of '' part of the layer removed 1. Finishing steps can then possibly be implemented to remove the few slight roughness and the few crystalline defects remaining on the surface of the sampled layer 1 ′, such as the implementation of a CMP, of a polishing or of chemical engraving.
- a layer of Si can be epitaxied on the layer of Sh_ x Ge x so as to be elastically stressed.
- a strained Si layer was formed before sampling on the Si- ⁇ _ x Ge x layer.
- the structure 30 layer then comprises in this case a sampled layer 1 ′ having a layer of constrained Si on which rests a layer of Si- ⁇ - x Ge x .
- the Si ⁇ layer. x Ge x is removed (for example by selective etching using for example HF: H 2 0 2 ' : CH 3 COOH) in order to obtain a final sSOI structure.
- the layer sampled in S - x Ge x 1 comprises one or more stop layer (s), such as a layer in Si ⁇ _ y Ge y with ye [0; 1] and y? x (formed in the layer to be removed, prior to removal), it is advantageously possible to implement at least one selective etching (combined or not with polishing) using the known solutions, and making it possible to carry out a finishing step particularly efficient, as taught in particular in documents FR 2 842 349 and FR 2 842 350.
- a structure 30 SGOI at 20% Ge (photographed by TEM) obtained by the Applicant following a post-separation thermal healing treatment at 600 ° C., shows a layer removed healed 1 ′ (covering a layer of Si0 2 5) which includes very few crystal defects and very little roughness compared to that of the semiconductor-on-insulator structure of FIG. 1.
- the healthy zone 1B is much larger in proportion in the SGOI obtained according to the invention than in the semiconductor-on-insulator according to the state of the art. It will be noted that the reduction in the thickness of the defective zone 1A is more particularly observed when the embrittlement zone is formed by co-implantation of atomic species. This is mainly due to the fact, already mentioned above, that the total dose of co-implanted species is much lower than the dose to be implanted when a single species is implanted.
- Co-implantation therefore has the advantage, compared to the implantation of a single species, of reducing the thickness of the defective zone, which in particular makes it possible to reduce or simplify the finishing treatments implemented after detachment .
- Results of roughness measurements on a SGOI structure at 20% Ge, carried out by the Applicant, are presented in the table below. These measurements were carried out just after separation at 500 ° C for 30 minutes following simple implantations or co-implantations, and a healing treatment at 500 ° C or 600 ° C. The roughnesses were measured using an AFM atomic force microscope by scanning surfaces of 10 * 10 ⁇ m 2 , and are expressed in RMS values and in “Peak to Valley” (PV). It should be noted that the Applicant has carried out a sufficient number of measurements to validate the results.
- Particles or organic substances present on one and / or the other of the plates to be bonded can prevent bonding from being carried out satisfactorily in certain regions of the bonding interface.
- the implanted species can then diffuse in the regions of the bonding interface which are weakly bonded, forming blisters (or "blisters" according to English terminology) at the bonding interface.
- blisters or "blisters" according to English terminology
- the energy of bonding may not be sufficient to allow detachment of the donor wafer.
- Certain zones of the sampled layer may thus not be transferred to the receiving package (these zones are commonly designated by the designation of "non-transferred zones" or ZNT).
- crystalline defects of the nanocavity type (having a diameter of a few nanometers) in the thickness of the sampled layer, beyond the defective zone. These defects can result from an agglomeration of Silicum or Germanium atoms displaced during the implantation.
- these nanocavity type defects located beyond the defective zone, but just as undesirable as the defects present in the defective zone
- the appearance of these defects requires post-detachment removal of a thickness of material greater than necessary, and therefore requires the removal of a thicker layer.
- FIG. 6a represents a view obtained by TEM photography of a Si donor plate having been subjected (cf. arrows) to a co-implantation of helium and hydrogen.
- the distribution of these species in the thickness of the donor plate is perceptible (dark dots) in this figure 6a.
- a heat treatment leads to separation at the level of the embrittlement zone (cf. FIG. 6b).
- FIG. 6c represents, for its part (in reverse view with respect to FIG.
- each of the implanted species is distributed, in the thickness of the donor plate, according to a distribution profile having a spreading zone in which the species is mainly concentrated and has a peak of maximum concentration. More precisely, the distribution has a quasi-Gaussian profile presenting a standard deviation (defining said spreading zone in which the species is mainly distributed, for example in which there is 70% of the implanted species) and a concentration peak which depend in particular on the implantation energy.
- Helium atoms diffuse in an Si matrix more easily than hydrogen atoms.
- the risk that blisters and crystal defects beyond the defective zone are formed.
- One approach to overcome this problem is to implant helium deeper than hydrogen, so that the region containing the implanted hydrogen can block the diffusion of helium. More precisely, it involves controlling the co-location parameters so that the helium peak is located deeper than the hydrogen spreading zone.
- the roughness after detachment does not follow the same trend, and tends to increase when helium is implanted. deeper than hydrogen. This means that the implantation conditions (ie implantation doses and energies) do not allow independent control of the roughness and the formation of blisters and crystal defects beyond the defective zone.
- the helium dose representing approximately 40% to 60% of the total dose.
- a possible embodiment of the method according to the present invention thus consists: - in carrying out a co-implantation, typically of helium and hydrogen, in a layer of SiGe, according to implantation parameters suitable for shifting the concentration peaks helium and hydrogen, especially so that the helium peak is located deeper than the hydrogen spreading zone, but also so that the helium peak is located deeper than the embrittlement, - And to implement a post-separation thermal healing treatment at a temperature of the order of 600 ° C (+/- 25 ° C), which can be maintained for 30 minutes to four hours, for example for about one hour.
- the implantation parameters are adapted for
- the helium peak is between 30% and 70% of the total dose (hydrogen + helium), preferably between 40% and 60% of the total dose.
- the total dose typically represents some 10 16 atoms / cm 2 , without this being limiting.
- this embodiment makes it possible, within the framework of this embodiment, to implant helium more deeply than hydrogen, which makes it possible to limit the formation of blisters and crystal defects beyond the defective zone in the sampled layer, the diffusion helium in the transferred layer being blocked by the hydrogen spreading zone. Consequently, this embodiment makes it possible to minimize both the roughness post detachment, the number of blister type defects and the number of defects present in the thickness of the layer removed. This leads to authorizing the removal of a lesser total thickness, which makes it possible to reduce, or at least to simplify, the post-detachment finishing operations (polishing, selective etching, sacrificial oxidation, etc.).
- FIGS. 7 to 9 show post-detachment roughness measurements on an SOI structure and a SGOI structure at 20% Ge. These measurements were carried out just after separation following simple implantations of hydrogen (designated by Honly in these figures) or helium / hydrogen co-implantations (designated by Col in these figures), and a one hour healing treatment. , at 500 ° C or 600 ° C. More precisely, the evolution of the temperature during the separation and healing phases was as follows: maintenance of a plateau at
- FIGS. 7 and 8 thus represent roughness measurements at high frequencies carried out by scanning respectively an area of 2 * 2 ⁇ m 2 and an area of 10 * 10 ⁇ m 2 using an AFM microscope.
- FIG. 9 represents roughness measurements at low frequencies carried out by profilometry using the Dektak® tool from the company Veeco Instruments Inc. In each of these FIGS. 7 to 9, roughness measurement results are shown, expressed on the left in average values (RMS) and on the right in maximum values (PV).
- He / H have been studied.
- the co-implantation parameters were as follows: H: 30kev-1.10 16 / cm 2 He: 52 or 60 keV - 1.010 16 / cm 2
- Figure 7 confirms the very interesting in terms of high frequency roughness linked to He / H co-implantation in comparison with H alone (and this either after a healing treatment at 500 ° C or 600 ° C).
- the Applicant has also carried out measurements aimed at ascertaining the number of defects (ZNT type, blisters) present in the different transferred layers. Macroscopic observation (in grazing light) makes it possible to detect defects of the ZNT type or blisters. We consider here the sum of these defects (ZNT + blisters) as being representative of the specific defects linked to implantation and observed post-detachment. A significant number of faults are noted in the two variants
- He: 48keV and He: 52keV that is to say the variants for which the distribution profile of helium is superimposed or almost superimposed with the profile of hydrogen (the peak of helium then being "at l 'inside' of the hydrogen spreading zone).
- a small number of defects is noted in the He: 56 keV and He: 60 keV variants, that is to say the variants for which the peak of the helium distribution profile is located deeper than the hydrogen spreading zone.
- blister type defects are minimized during a deep implantation of helium (and this, in the case of a cure at 600 ° C., without the roughness being increased).
- those skilled in the art can easily transpose the invention presented here to other materials than S.
Abstract
Description
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JP2007501320A JP4876068B2 (ja) | 2004-03-05 | 2005-03-07 | スマートカット(登録商標)剥離後の熱処理方法 |
EP05737041A EP1726039A1 (fr) | 2004-03-05 | 2005-03-07 | Traitement thermique apres detachement smart-cut |
US11/357,883 US7282449B2 (en) | 2004-03-05 | 2006-02-17 | Thermal treatment of a semiconductor layer |
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FR0402340A FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
FR0402340 | 2004-03-05 |
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US11/058,992 Continuation-In-Part US7285495B2 (en) | 2004-03-05 | 2005-02-16 | Methods for thermally treating a semiconductor layer |
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US11/357,883 Continuation US7282449B2 (en) | 2004-03-05 | 2006-02-17 | Thermal treatment of a semiconductor layer |
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EP (1) | EP1726039A1 (fr) |
JP (1) | JP4876068B2 (fr) |
KR (1) | KR100910687B1 (fr) |
CN (3) | CN1950937B (fr) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007251172A (ja) * | 2006-03-13 | 2007-09-27 | Soi Tec Silicon On Insulator Technologies Sa | 薄膜を製造する方法 |
US7871900B2 (en) | 2007-03-29 | 2011-01-18 | S.O.I. Tec Silicon On Insulator Technologies | Quality of a thin layer through high-temperature thermal annealing |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6717213B2 (en) * | 2001-06-29 | 2004-04-06 | Intel Corporation | Creation of high mobility channels in thin-body SOI devices |
EP1652230A2 (fr) * | 2003-07-29 | 2006-05-03 | S.O.I.Tec Silicon on Insulator Technologies | Procede d' obtention d' une couche mince de qualite accrue par co-implantation et recuit thermique |
FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
US7935613B2 (en) * | 2003-12-16 | 2011-05-03 | International Business Machines Corporation | Three-dimensional silicon on oxide device isolation |
US20070281440A1 (en) * | 2006-05-31 | 2007-12-06 | Jeffrey Scott Cites | Producing SOI structure using ion shower |
FR2923079B1 (fr) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | Substrats soi avec couche fine isolante enterree |
WO2009084311A1 (fr) * | 2007-12-27 | 2009-07-09 | Sharp Kabushiki Kaisha | Dispositif à semi-conducteur, substrat doté d'une couche mince semi-conductrice monocristalline et leurs procédés de fabrication |
JP5303957B2 (ja) * | 2008-02-20 | 2013-10-02 | 株式会社デンソー | グラフェン基板及びその製造方法 |
US8133800B2 (en) * | 2008-08-29 | 2012-03-13 | Silicon Genesis Corporation | Free-standing thickness of single crystal material and method having carrier lifetimes |
JP5493343B2 (ja) | 2008-12-04 | 2014-05-14 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US20110207306A1 (en) * | 2010-02-22 | 2011-08-25 | Sarko Cherekdjian | Semiconductor structure made using improved ion implantation process |
US8558195B2 (en) | 2010-11-19 | 2013-10-15 | Corning Incorporated | Semiconductor structure made using improved pseudo-simultaneous multiple ion implantation process |
US8008175B1 (en) | 2010-11-19 | 2011-08-30 | Coring Incorporated | Semiconductor structure made using improved simultaneous multiple ion implantation process |
US8196546B1 (en) | 2010-11-19 | 2012-06-12 | Corning Incorporated | Semiconductor structure made using improved multiple ion implantation process |
CN102184882A (zh) * | 2011-04-07 | 2011-09-14 | 中国科学院微电子研究所 | 一种形成复合功能材料结构的方法 |
FR2978604B1 (fr) * | 2011-07-28 | 2018-09-14 | Soitec | Procede de guerison de defauts dans une couche semi-conductrice |
FR2980916B1 (fr) * | 2011-10-03 | 2014-03-28 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type silicium sur isolant |
FR2982071B1 (fr) * | 2011-10-27 | 2014-05-16 | Commissariat Energie Atomique | Procede de lissage d'une surface par traitement thermique |
CN103165512A (zh) * | 2011-12-14 | 2013-06-19 | 中国科学院上海微系统与信息技术研究所 | 一种超薄绝缘体上半导体材料及其制备方法 |
CN103165511B (zh) * | 2011-12-14 | 2015-07-22 | 中国科学院上海微系统与信息技术研究所 | 一种制备goi的方法 |
CN105140171B (zh) * | 2015-08-26 | 2018-06-29 | 中国科学院上海微系统与信息技术研究所 | 一种绝缘体上材料的制备方法 |
CN105957831A (zh) * | 2016-07-06 | 2016-09-21 | 中国科学院上海微系统与信息技术研究所 | 一种用于制造支撑衬底上的单晶材料薄层结构的方法 |
CN107195534B (zh) * | 2017-05-24 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Ge复合衬底、衬底外延结构及其制备方法 |
CN109427538B (zh) * | 2017-08-24 | 2021-04-02 | 中国科学院上海微系统与信息技术研究所 | 一种异质结构的制备方法 |
DE112019002290T5 (de) * | 2018-12-28 | 2021-04-08 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und verfahren zum herstellen |
CN111722321A (zh) * | 2020-01-19 | 2020-09-29 | 中国科学院上海微系统与信息技术研究所 | 一种光膜转换器及其制备方法 |
FR3108440A1 (fr) * | 2020-03-23 | 2021-09-24 | Soitec | Procédé de préparation d’une couche mince |
CN111834520B (zh) * | 2020-06-29 | 2021-08-27 | 中国科学院上海微系统与信息技术研究所 | 一种表面均匀性优化的压电单晶薄膜制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999035674A1 (fr) * | 1997-12-30 | 1999-07-15 | Commissariat A L'energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
EP0961312A2 (fr) * | 1998-05-15 | 1999-12-01 | Canon Kabushiki Kaisha | Substrat du type SOI fabriqué par collage |
US20030124815A1 (en) * | 1999-08-10 | 2003-07-03 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4462847A (en) * | 1982-06-21 | 1984-07-31 | Texas Instruments Incorporated | Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition |
US4604304A (en) * | 1985-07-03 | 1986-08-05 | Rca Corporation | Process of producing thick layers of silicon dioxide |
US4722912A (en) * | 1986-04-28 | 1988-02-02 | Rca Corporation | Method of forming a semiconductor structure |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JPH06318588A (ja) | 1993-03-11 | 1994-11-15 | Nec Corp | 半導体装置の製造方法 |
US6155909A (en) * | 1997-05-12 | 2000-12-05 | Silicon Genesis Corporation | Controlled cleavage system using pressurized fluid |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JP3412470B2 (ja) * | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
JP3582566B2 (ja) * | 1997-12-22 | 2004-10-27 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
CN1241803A (zh) * | 1998-05-15 | 2000-01-19 | 佳能株式会社 | 半导体衬底、半导体薄膜以及多层结构的制造工艺 |
JP3358550B2 (ja) | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP4379943B2 (ja) * | 1999-04-07 | 2009-12-09 | 株式会社デンソー | 半導体基板の製造方法および半導体基板製造装置 |
US6352942B1 (en) * | 1999-06-25 | 2002-03-05 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
DE10031388A1 (de) * | 2000-07-03 | 2002-01-17 | Bundesdruckerei Gmbh | Handsensor für die Echtheitserkennung von Signets auf Dokumenten |
US6573126B2 (en) * | 2000-08-16 | 2003-06-03 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
US6448152B1 (en) * | 2001-02-20 | 2002-09-10 | Silicon Genesis Corporation | Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer |
US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
US7238622B2 (en) * | 2001-04-17 | 2007-07-03 | California Institute Of Technology | Wafer bonded virtual substrate and method for forming the same |
US6593625B2 (en) * | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6717213B2 (en) * | 2001-06-29 | 2004-04-06 | Intel Corporation | Creation of high mobility channels in thin-body SOI devices |
US6649492B2 (en) * | 2002-02-11 | 2003-11-18 | International Business Machines Corporation | Strained Si based layer made by UHV-CVD, and devices therein |
US6562703B1 (en) * | 2002-03-13 | 2003-05-13 | Sharp Laboratories Of America, Inc. | Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content |
FR2839385B1 (fr) | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
WO2003105189A2 (fr) | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Structures de dispositif a semi-conducteurs contraints sur isolant |
US7018910B2 (en) * | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
FR2842349B1 (fr) | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
US6953736B2 (en) * | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
FR2842350B1 (fr) * | 2002-07-09 | 2005-05-13 | Procede de transfert d'une couche de materiau semiconducteur contraint | |
JP5005170B2 (ja) | 2002-07-19 | 2012-08-22 | エーエスエム アメリカ インコーポレイテッド | 超高品質シリコン含有化合物層の形成方法 |
US20040137698A1 (en) * | 2002-08-29 | 2004-07-15 | Gianni Taraschi | Fabrication system and method for monocrystaline semiconductor on a substrate |
FR2844634B1 (fr) | 2002-09-18 | 2005-05-27 | Soitec Silicon On Insulator | Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon |
US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
RU2625370C2 (ru) * | 2011-12-07 | 2017-07-13 | Конинклейке Филипс Н.В. | Способ и устройство для обнаружения движения лифта |
-
2004
- 2004-03-05 FR FR0402340A patent/FR2867307B1/fr not_active Expired - Lifetime
-
2005
- 2005-02-16 US US11/058,992 patent/US7285495B2/en active Active
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- 2005-03-07 JP JP2007501320A patent/JP4876068B2/ja active Active
- 2005-03-07 WO PCT/FR2005/000543 patent/WO2005086228A1/fr active Application Filing
- 2005-03-07 EP EP05737041A patent/EP1726039A1/fr not_active Withdrawn
- 2005-03-07 CN CN200580014164A patent/CN100592493C/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999035674A1 (fr) * | 1997-12-30 | 1999-07-15 | Commissariat A L'energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
EP0961312A2 (fr) * | 1998-05-15 | 1999-12-01 | Canon Kabushiki Kaisha | Substrat du type SOI fabriqué par collage |
US20030124815A1 (en) * | 1999-08-10 | 2003-07-03 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
Non-Patent Citations (1)
Title |
---|
AGARWAL A ET AL: "EFFICIENT PRODUCTION OF SILICON-ON-INSULATOR FILMS BY CO- IMPLANTATION OF HE+ WITH H+", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 72, no. 9, 2 March 1998 (1998-03-02), pages 1086 - 1088, XP000742819, ISSN: 0003-6951 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007251172A (ja) * | 2006-03-13 | 2007-09-27 | Soi Tec Silicon On Insulator Technologies Sa | 薄膜を製造する方法 |
US7871900B2 (en) | 2007-03-29 | 2011-01-18 | S.O.I. Tec Silicon On Insulator Technologies | Quality of a thin layer through high-temperature thermal annealing |
Also Published As
Publication number | Publication date |
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JP4876068B2 (ja) | 2012-02-15 |
US7285495B2 (en) | 2007-10-23 |
KR20070088279A (ko) | 2007-08-29 |
CN1950937A (zh) | 2007-04-18 |
US20050196936A1 (en) | 2005-09-08 |
EP1726039A1 (fr) | 2006-11-29 |
CN100592493C (zh) | 2010-02-24 |
KR100910687B1 (ko) | 2009-08-04 |
JP2007526646A (ja) | 2007-09-13 |
FR2867307A1 (fr) | 2005-09-09 |
CN1950937B (zh) | 2010-06-16 |
CN1930674A (zh) | 2007-03-14 |
CN1950938A (zh) | 2007-04-18 |
FR2867307B1 (fr) | 2006-05-26 |
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