WO2005086428A1 - Deep sleep mode for wlan communicatio systems - Google Patents
Deep sleep mode for wlan communicatio systems Download PDFInfo
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- WO2005086428A1 WO2005086428A1 PCT/US2005/006113 US2005006113W WO2005086428A1 WO 2005086428 A1 WO2005086428 A1 WO 2005086428A1 US 2005006113 W US2005006113 W US 2005006113W WO 2005086428 A1 WO2005086428 A1 WO 2005086428A1
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- Prior art keywords
- physical connection
- wlan
- communication device
- oscillator
- deep sleep
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
- H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
- H04W84/10—Small scale networks; Flat hierarchical networks
- H04W84/12—WLAN [Wireless Local Area Networks]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Definitions
- TITLE DEEP SLEEP MODE FOR WLAN COMMUNICATION SYSTEMS
- the present application relates to WLAN (Wireless Local Area Network) communication devices for performing communication in a WLAN network and corresponding integrated circuit chips, computer systems and methods, and in particular to standby modes thereof.
- WLAN Wireless Local Area Network
- a wireless local area network is a flexible data communication system implemented as an extension to or as an alternative for a wired LAN.
- WLAN systems Using radio frequency or infrared technology, WLAN systems transmit and receive data over the air, minimizing the need for, wired connections.
- WLAN systems combine data connectivity with user mobility.
- Today, most WLAN systems use spread spectrum technology, a wideband radio frequency technique developed for use in reliable and secure communication systems.
- the spread spectrum technology is designed to trade off bandwidth efficiency for reliability, integrity and security.
- Two types of spread spectrum radio systems are frequently used: frequency hopping and direct sequence systems.
- the standard defining and governing wireless local area networks that operate in the 2.4 GHz spectrum is the IEEE 802.11 standard.
- WLAN systems comprise one or more access points that connect to a wired network and remote client devices that connect to the access points through wireless links.
- the client devices may also communicate directly with each other.
- the remote client devices are usually portable computer systems with WLAN communication devices, often referred to as WLAN cards or modules, installed. Since remote devices are usually mobile and often use battery power, the power consumption of the system required for WLAN- related activities is an important feature affecting the battery lifetime and therefore the user friendliness of the system.
- many conventional WLAN cards can be operated in a standby mode when no exchange of data packets between the host computer system and an access point is required.
- Two types of standby modes are usually applied: in a listening mode, the WLAN card listens periodically for traffic from the access point including beacon signals announcing the presence and readiness of the access point. However, no data packets are exchanged with the host computer system.
- In a sleep mode the link to the access point is disabled. A majority of the WLAN card circuitry is turned off except for certain critical parts. According to prior art techniques, the parts of the WLAN card circuitry that are kept active during the sleep mode include the very stable reference oscillator that governs the operation of the WLAN card circuitry by providing a base clock signal and stabilizes the operation of the radio circuitry.
- WLAN cards often consume 15-20 mA of current while in the sleep mode, whereof 8-9 mA are consumed solely by the reference oscillator.
- known WLAN cards often extend the time of remaining in the sleep mode. While the WLAN card is in the sleep mode, incoming data packets are buffered at the access point. They may only be retrieved when the WLAN card enters the listening mode in order to find out whether there are data packets queued at the access point and transitions from the standby mode to a communication mode if this is the case. In consequence, conventional WLAN systems often defer the data exchange between the access point and the client device. This may lead to further problems in achieving efficient data rates. Further, the access points buffering the data packets while the client device is in the sleep mode are generally permitted to dump unread data packets after a specified time and these data packets go unretrieved. Therefore, conventional WLAN systems also have the disadvantage of usually suffering from considerable data loss.
- Embodiments may provide a deep sleep mode for operating a WLAN communication device that may have the advantage of consuming significantly less power in the deep sleep mode than in a conventional sleep mode.
- the tradeoff between extending battery lifetime of the host computer system and achieving efficient data rates may be enhanced.
- increased battery lifetime may be achieved while not deferring the exchange of data packets between the access point and the client device.
- battery lifetime may be increased while data loss due to deferred reception may be prevented.
- the physical connection unit is for providing a physical connection of the WLAN communication device to a wireless communication medium.
- the physical connection oscillator is connected to the physical connection unit for providing a physical connection clock signal to the physical connection unit.
- the control unit is connected to the physical connection oscillator for controlling operation of the physical connection oscillator.
- the WLAN communication device is operable in a communication mode for transmitting and/or receiving data packets and in a first standby mode.
- the control unit is adapted to deactivate the physical connection oscillator when the WLAN communication device enters the first standby mode.
- an integrated circuit chip for performing communication in a WLAN network comprising a physical connection circuit, a physical connection oscillator circuit, and a control circuit.
- the physical connection circuit is for providing a physical connection of the integrated circuit chip to a wireless communication medium.
- the physical connection oscillator circuit is connected to the physical connection circuit for providing a physical connection clock signal to the physical connection circuit.
- the control circuit is connected to the physical connection oscillator circuit for controlling operation of the physical connection oscillator circuit.
- the integrated circuit chip is operable in a communication mode for transmitting and/or receiving data packets and in a first standby mode.
- the control circuit is adapted to deactivate the physical connection oscillator circuit when the integrated circuit chip enters the first standby mode.
- a computer system for performing communication in a WLAN network comprising a physical connection device, a physical connection oscillator, and a control device.
- the physical connection device is for providing a physical connection of the computer system to a wireless communication medium.
- the physical connection oscillator is connected to the physical connection device for providing a physical connection clock signal to the physical connection device.
- the control device is connected to DE0419.pct
- a method of operating a WLAN communication device for performing communication in a WLAN network is provided.
- a physical connection unit is operated for providing a physical connection of the WLAN communication device to a wireless communication medium.
- a physical connection oscillator is operated for providing a physical connection clock signal to the physical connection unit.
- a control unit is operated for controlling operation of the physical connection oscillator.
- the WLAN communication device is operated in a communication mode for transmitting and/or receiving data packets and in a first standby mode. The physical connection oscillator is deactivated when the operation of the WLAN communication device enters the first standby mode.
- FIG. 1 is a block diagram illustrating the components of a WLAN-compatible computer system according to an embodiment
- FIG.2 is a block diagram illustrating the components of the deep sleep control circuit comprised within the WLAN-compatible computer system of FIG. 1 according to an embodiment
- FIG. 1 is a block diagram illustrating the components of a WLAN-compatible computer system according to an embodiment
- FIG. 3 is a flow diagram illustrating a clock ramp-up process according to an embodiment
- FIG.4 is a flow diagram illustrating a deep sleep clock determination process according to an embodiment
- FIG. 5 is a flow diagram illustrating a deep sleep entering process according to an embodiment
- FIG. 6 is a flow diagram illustrating a deep sleep abandoning process according to an embodiment.
- the computer system may comprise a WLAN communication device 120.
- the WLAN communication device 120 may comprise a physical connection circuit 145 for providing a physical connection of the WLAN communication device 120 to a wireless communication medium over which communication signals can be exchanged with a WLAN communication counterpart.
- the physical connection circuit 145 may comprise a radio circuit or infrared circuit for sending and/or receiving radio or infrared signals respectively over the wireless communication medium. Other transmission/reception techniques may be applied.
- the physical connection circuit 145 may comprise an internal oscillator for generating the communication signals.
- the WLAN communication device 120 may comprise a physical connection oscillator 150 that is connected to the physical connection circuit 145 for providing a physical connection clock signal to the physical connection circuit 145.
- the physical connection clock signal may be used for stabilizing the frequency generated by the internal oscillator within the physical connection circuit 145.
- the physical connection oscillator 150 may be a quartz oscillator generating the physical connection clock signal at a frequency of 44 MHz. Other types of oscillators operating at other frequencies may be applied.
- the WLAN communication device 120 may comprise a MAC (Medium Access Control) circuit 130 for managing communication in the WLAN network by coordinating access to the wireless communication medium.
- MAC Medium Access Control
- the WLAN communication device 120 may further comprise a BBP (Base Band Processor) circuit 135 for converting the communication signals interchangeable over the wireless communication medium into digital data packets processable by the MAC circuit 130 and/or vice versa.
- the BBP circuit 135 may be connected to the physical connection circuit 145 for exchanging the communication signals and to the MAC circuit 130 for exchanging the digital data packets.
- the WLAN communication device 120 may comprise a deep sleep control circuit 140 connected to the physical connection oscillator 150 for controlling operation of the physical connection oscillator 150.
- the deep sleep control circuit 140 may further be connected to the MAC circuit 130 for exchanging control signals during the processes of entering and/or abandoning a deep sleep mode of the WLAN communication device 120 which will be described below.
- the physical comiection circuit 145 may comprise a frequency divider for generating a main clock signal by dividing the frequency of the physical connection clock signal received from the physical connection oscillator 150.
- the frequency divider of the physical connection circuit 145 may convert a 44 MHz physical connection clock signal into a 22 MHz main clock signal.
- the physical connection circuit 145 may be connected to the MAC circuit 130 and/or the BBP circuit 135 and/or the deep sleep control circuit 140 for providing the main clock signal to the MAC circuit 130 and/or the BBP circuit 135 and/or the deep sleep control circuit 140, respectively.
- the MAC circuit 130 and the BBP circuit 135 may be comprised within an integrated baseband medium access circuit 125.
- the deep sleep control circuit 140 may also be comprised within the integrated baseband medium access circuit 125.
- the WLAN communication device 120 may not comprise an integrated baseband medium access circuit 125, but the MAC circuit 130, the BBP circuit 135, and the deep sleep control circuit 140 as separate individual circuits.
- the WLAN communication device 120 may comprise additional internal oscillators besides the physical connection oscillator 150 for providing clock signals to certain components of the WLAN communication device 120.
- the WLAN device 120 may be installed on a host computer system comprising a CPU (Central Processing Unit) 105 for providing WLAN compatibility to the computer system.
- CPU Central Processing Unit
- the MAC circuit 130 of the present embodiment may be connected to the CPU 105 for exchanging digital data packets and/or control signals for entering and/or abandoning the below-described deep sleep mode of the WLAN communication device 120.
- the CPU 105 may further be connected to the deep sleep control circuit 140 for sending control signals for entering and/or abandoning the below-discussed deep sleep mode to the deep sleep control circuit 140.
- the deep sleep control circuit 140 may be connected to an analog clock oscillator 110 and a digital clock oscillator 115 within the host computer system for receiving a clock signal from the analog clock oscillator 110 and/or the digital clock oscillator 115 while the WLAN communication device 120 is in the below- described deep sleep mode.
- the deep sleep control circuit 140 may be connected to either an analog clock oscillator 110 or a digital clock oscillator 115 only. In further embodiments, the deep sleep control circuit 140 may be connected to a plurality of analog and/or digital clock oscillators. In still a further embodiment, the analog clock oscillator 110 and/or the digital clock oscillator 115 may be comprised within the WLAN communication device 120 or within the integrated baseband medium access circuit 125. Different types of oscillators may serve as the analog clock oscillator 110. For instance, the analog clock oscillator 110 may be a XO (crystal oscillator) oscillator. In one embodiment, the XO oscillator may be an uncompensated XO oscillator.
- XO crystal oscillator
- the XO oscillator may be a compensated XO oscillator, e.g., a voltage-controlled crystal oscillator, a temperature compensated crystal oscillator, or an oven-controlled crystal oscillator.
- the analog clock oscillator 110 may emit a clock signal at a frequency of 32.768 kHz.
- the clock signal generated by the analog clock oscillator 110 may have other frequencies. Combinations of the embodiments may be implemented.
- the digital clock oscillator 115 may be a programmable digital clock oscillator emitting a clock signal at a frequency that can be selected from a certain frequency range.
- a clock signal frequency may be selected from a frequency range extending from 32 kHz to 22 MHz.
- the clock signal frequency may be selected from a frequency range extending from 16 kHz to 1 MHz or from any other frequency range.
- the digital clock oscillator 115 may be a watchdog oscillator for ensuring robust behavior of components of the host computer system in noisy environments with poor or unreliable power supplies. Combinations of the embodiments may be realized. Turning now to FIG. 2, the components of the deep sleep control circuit 140 according to an embodiment are shown.
- the deep sleep control circuit 140 may comprise a timing counter 230 for counting the number of time intervals of a predetermined length that have elapsed since the WLAN communication device 120 has entered the below-discussed deep sleep mode. Accordingly, the deep sleep control circuit 140 may further comprise a timing control circuit 220 connected to the timing counter 230 for making the timing counter 230 start and/or stop counting by sending a start counting signal or a stop counting signal, respectively, to the timing counter 230. Further, the timing control circuit 220 may be connected to the CPU 105 and the MAC circuit 130 for receiving or exchanging, respectively, control signals for entering and/or abandoning the below-described deep sleep mode.
- the timing control circuit 220 may also be connected to the physical connection oscillator 150 for controlling operation of the physical connection oscillator 150.
- the timing control circuit 220 and the timing counter 230 may be combined in one single circuit.
- the deep sleep control circuit 140 further comprises a multiplexer 210 for forwarding the clock signals received from the physical connection circuit 145 and the analog clock oscillator 110 and/or the digital clock oscillator 115 to the timing control circuit 220 and the timing counter 230.
- the multiplexer 210 may be located on the WLAN communication device 120 outside the deep sleep control circuit 140 or outside the integrated baseband medium access circuit 125.
- frequency dividers may be installed between the multiplexer and the physical connection circuit 145 and/or between the multiplexer 210 and the analog clock oscillator 110 and/or between the multiplexer 210 and the digital clock oscillator 115.
- a frequency divider may divide the 22 MHz main clock signal from the physical connection circuit 145 by 2,750 in order to generate an 8 kHz clock signal provided to the multiplexer 210.
- a frequency divider may divide the 32.768 kHz clock signal from the analog clock oscillator 110 by 4 in order to generate a clock signal of about 8 kHz provided to the multiplexer 210.
- a frequency divider may generate a clock signal of about 8 kHz by dividing the clock signal of a programmable frequency from the digital clock oscillator 115 accordingly. Clock signals of other frequencies may be provided to and/or generated by the frequency dividers.
- the deep sleep control circuit 145 may comprise a frequency divider acting on the frequency of the clock signal provided from the multiplexer 210 to the timing control circuit 220 and the timing counter 230. In one embodiment, this frequency divider may convert a clock signal of (about) 8 kHz into a clock signal of (about) 4 kHz. In other embodiments, this frequency divider may convert a clock signal of a frequency other than 8 kHz into a clock signal of a frequency other than 4 kHz.
- the described frequency dividers connected to the multiplexer 210 may be located outside the deep sleep control circuit 140 or outside the integrated baseband medium access circuit 125.
- the timing controller 230 may count the number of time intervals elapsed since the WLAN communication device 120 has entered the below-described deep sleep mode based on the clock signal received over the multiplexer 210. In one embodiment, time intervals of 1/1024 s may be counted. In other embodiments, the counted time intervals may have other lengths.
- the timing counter 230 may be programmable in order to select the length of the time intervals to be counted.
- the deep sleep control circuit 140 of the present embodiment may be adapted to determine whether a clock signal from the analog clock oscillator 110 and/or the digital clock oscillator 115 is available to the multiplexer 210.
- the deep sleep control circuit 140 may further be adapted to determine how many clock signals are available to the multiplexer 210 and/or whether the available clock signals are received from analog or digital clock oscillators. Further, the deep sleep control circuit 140 may be adapted to determine the frequency of the available clock signals.
- the deep sleep control circuit 140 may be capable of determining a preferred clock signal if more than one clock signal is available to the multiplexer 210. For instance, the preferred clock signal may be determined by reading preference values for the individual available clock signals from a preference table.
- the deep sleep control circuit 140 may be arranged for controlling the setting of the multiplexer 210 so that only the preferred clock signal may be passed through the multiplexer 210.
- the above-described determination and control steps may be accomplished by individual or combined dedicated circuits within the deep sleep control circuit 140 and/or the integrated baseband medium access circuit 125 and/or the WLAN communication device 120.
- at least part of the above-described determination and control steps may be accomplished by the timing control circuit 220 and/or the MAC circuit 130. Combinations of the embodiments may be realized.
- the WLAN communication device 120 may be operable in a communication mode for exchanging digital data packets with a host computer system and exchanging corresponding communication signals with a WLAN communication counterpart, e.g., an access point or another WLAN communication device, over the wireless communication medium.
- the communication mode may comprise a reception mode during which the WLAN communication device 120 is detecting the communication signals, demodulating and converting the communication signals into digital data packets and passing the digital data packets to the host computer system.
- the communication mode may comprise a transmission mode during which the WLAN communication device is modulating and converting the digital data packets into communication signals and sending the communication signals over the wireless communication medium.
- all the components of the WLAN communication device 120 may be active during the communication mode.
- the WLAN communication device 120 may further be operable in at least one standby mode.
- the standby mode may comprise a listening mode during which the WLAN communication device 120 is listening for traffic from a WLAN communication counterpart, but is not passing any data to the .host computer system. While the WLAN communication device 120 is in the listening mode, part of its components, e.g., the components only needed for communicating with the host computer system, may be inactive while other components including the physical connection circuit 145 and the physical connection oscillator 150 may be active. The WLAN communication device 120 may consume less power in the listening mode than in the communication mode.
- the standby mode may comprise a sleep mode. While the WLAN communication device 120 is in the sleep mode, no digital data packets may be exchanged with a host computer system.
- no link to a WLAN communication counterpart may be established during the sleep mode.
- a majority of the circuitry of the WLAN communication device 120 may be turned off during the sleep mode except for certain critical parts including the physical connection oscillator 150.
- the WLAN communication device 120 may consume less power in the sleep mode than in the listening mode and/or the communication mode.
- the WLAN communication device 120 may consume 15-20 mA of current while in the sleep mode, whereof 8-9 mA may be consumed by the physical connection oscillator 150.
- the standby mode may comprise a deep sleep mode. While in the deep sleep mode, the WLAN communication device 120 may not exchange any digital data packets with the host computer system. No link to WLAN communication counterparts may be established during the deep sleep mode.
- All the components of WLAN communication device 120 that are inactive during an above-described sleep mode may also be inactive during the deep sleep mode.
- the physical connection oscillator 150 may be inactive during the deep sleep mode.
- the MAC circuit 130 and/or the physical connection circuit 145 may also be inactive during the deep sleep mode.
- the WLAN communication device 120 may consume less power in the deep sleep mode than in the sleep mode and/or the listening mode and/or the communication mode. According to an embodiment, the WLAN communication device 120 may consume 1-2 mA of current during the deep sleep mode.
- Embodiments combining the described communication and standby modes may also be implemented.
- FIG. 3 illustrates a clock ramp-up process that may be performed by the WLAN communication device 120 upon being activated, e.g., after a reset.
- the clock ramp-up process may also be performed when the WLAN communication device 120 abandons the deep sleep mode.
- an activate signal may be sent from the timing control circuit 220 to the physical connection oscillator 150.
- the physical connection oscillator 150 may be activated, i.e. the physical connection oscillator 150 may generate the physical connection clock signal.
- the physical connection circuit 145 may be activated once the physical connection oscillator 150 has started to generate the physical connection clock signal.
- additional internal clock oscillators besides the physical connection oscillator 150 (and besides the analog clock oscillator 110 and the digital clock oscillator 115, in case they are comprised within the WLAN communication device 120) may also be activated.
- an activate signal may be sent from the timing control circuit 220 to the MAC circuit 130 for activating the MAC circuit 130.
- the MAC circuit 130 may return an activate confirmation signal to the timing control circuit 220 in step 330 for acknowledging the activation.
- the clock ramp-up process may last 1-4 ms.
- FIG. 4 a flow diagram illustrating a deep sleep clock determination process according to an embodiment is shown. The deep sleep clock determination process may be performed subsequently to the clock ramp-up process or at any later time prior to entering the deep sleep mode.
- the system may determine whether a clock signal from the analog clock oscillator 110 and/or the digital clock oscillator 115 is available to the multiplexer 210.
- step 420 may comprise determining how many clock signals are available and whether the available clock signals are received from the analog clock oscillator 110 and/or the digital clock oscillator 115.
- step 420 it may be queried whether clock signals from both the analog clock oscillator 110 and the digital clock oscillator 115 are available. If this is the case, the system may determine in step 440 which of the available clock signals is preferred and proceed to step 450. Otherwise, it may be queried in step 430 if a clock signal from either the analog clock oscillator 110 or the digital clock oscillator 115 is available. If so, the multiplexer may be set in step 450 to the input from the available or preferred clock oscillator, respectively. Otherwise, the multiplexer may be set in step 460 to the input from the physical connection circuit 145.
- FIG. 5 is a flow diagram illustrating a deep sleep entering process according to an embodiment.
- a deep sleep request signal may be sent from the MAC circuit 130 to the timing control circuit 220.
- the deep sleep request signal may be sent to the timing control circuit from the CPU 105 and/or a communication counterpart, e.g., an access point, within the WLAN network.
- the deep sleep request signal may be sent to the timing control circuit 220 directly and/or over the MAC circuit 130.
- a request confirmation signal may be sent from the timing control circuit 220 to the MAC circuit 130 if the deep sleep request signal has been received.
- the request confirmation signal may be returned to the sender of the deep sleep request signal which may be different from the MAC circuit 130, as indicated above.
- the MAC circuit 130 may send a deep sleep duration signal to the timing control circuit 220 in step 530.
- the deep sleep duration signal may indicate a number of time intervals of a predetermined length corresponding to the intended duration of the deep sleep mode, after which the deep sleep mode may be abandoned automatically.
- the deep sleep duration signal may indicate an indeterminate duration of the deep sleep mode. In this embodiment, the deep sleep mode may not be abandoned automatically but, e.g., upon reception of a deep sleep abandon signal from the CPU 105 or upon a reset of the WLAN communication device 120.
- the deep sleep duration signal may be sent from the CPU 105 and/or an access point within the WLAN network to the timing control circuit 220.
- the deep sleep duration signal may be sent to the timing control circuit 220 directly or over the MAC circuit 130.
- the WLAN communication device 120 may be capable of negotiating a duration of the deep sleep mode with the CPU 105 and/or a communication counterpart, e.g., an access point, within the WLAN network.
- the order of magnitude of the deep sleep duration may extend from milliseconds to seconds.
- a counting start signal may be sent from the timing control circuit 220 to the timing counter 230 for making the timing counter 230 start counting the number of time intervals that elapse.
- the timing counter 230 may continuously count the elapsed time intervals.
- the WLAN communication device 120 may comprise additional internal oscillators besides the physical connection oscillator 150 (and besides the analog clock oscillator 110 and the digital clock oscillator 115 in case they are comprised within the WLAN communication device 120) for providing clock signals to certain components of the WLAN communication device 120. These additional internal oscillators may be deactivated once the timing counter 230 has started counting.
- a deactivate signal may be sent from the timing control circuit 220 to the MAC circuit 130.
- the MAC circuit 130 may be deactivated upon reception of the deactivate signal.
- step 560 it may be queried whether at least one clock signal from the analog clock oscillator 110 and/or the digital clock oscillator 115 is available to the multiplexer 210. If this is the case, a deactivate signal may be sent from the timing control circuit 220 to the physical connection oscillator 150 in step 570. Upon reception of the deactivate signal, the physical connection oscillator 150 may be deactivated. Subsequently, the physical connection circuit 145 may also be deactivated according to an embodiment. If no clock signal is available, neither from the analog clock oscillator 110 nor from the digital clock oscillator 115, the deactivate signal may not be sent to the physical connection oscillator 150 and the deep sleep entering process may be complete at this point. Referring now to FIG.
- the deep sleep abandoning process may lead to a transition of the WLAN communication device 120 from the deep sleep mode to the sleep mode, the listening mode or the communication mode.
- the timing control circuit 220 may determine whether the value of the timing counter 230 indicating the number of time intervals that have elapsed corresponds to the intended duration of the deep sleep mode. If this is the case, the system may proceed to step 630. If this is not the case, it may be determined in step 620 whether a deep sleep abandon signal is received from the CPU 105. In one embodiment, the deep sleep abandon signal may be sent from the CPU 105 to the timing control circuit 220.
- the deep sleep abandon signal may be sent from the CPU 105 to the MAC circuit 130 which may forward the deep sleep abandon signal to the timing control circuit 220. If no deep sleep abandon signal is received, the deep sleep mode may not be abandoned. If a deep sleep abandon signal is received, the system may proceed to step 630. In step 630, a stop signal may be sent from the timing control circuit 220 to the timing counter 230 for making the timing counter stop counting the number of elapsed time intervals. In other embodiments, the timing control circuit 220 may set the counter value to the number of time intervals corresponding to the intended deep sleep duration during the deep sleep entering process. In such embodiments, the timing counter 230 may count backwards and automatically stop counting when the counter value reaches zero.
- the WLAN communication device 120 may perform the clock ramp-up process in step 640 once the timing counter 230 has stopped counting. Subsequently, or at any later time prior to reentering the deep sleep mode, the deep sleep clock determination may be performed in step 650.
- data packet strings containing a plurality of data packets may be sent to and/or received from a communication counterpart, e.g., an access point or another WLAN communication device, within the WLAN network. Within a data packet string, the individual data packets may be separated by time intervals of a certain length, e.g., 100 ms.
- the WLAN communication device 120 may periodically switch between the communication mode and the deep sleep mode so that it may be in the deep sleep mode during the time intervals separating the data packets.
- the WLAN communication device 120 may be in the deep sleep mode and periodically interrupt the deep sleep mode for transitioning to the listening mode or any other mode for maintaining WLAN network connectivity. For instance, the WLAN communication device 120 may abandon the deep sleep mode for entering the listening mode or the communication mode each time a beacon signal indicating the presence and readiness of a WLAN communication counterpart is sent to the WLAN communication device 120.
- the beacon signal may include a DTIM (Delivery Traffic Indication Message) message informing the WLAN communication device 120 whether a data packet is awaiting delivery.
- DTIM Delivery Traffic Indication Message
- the WLAN communication device 120 may enter or remain in the communication mode, respectively, for receiving the waiting data packet. Otherwise, the WLAN communication device 120 may reenter the deep sleep mode upon reception of the beacon signal. In further embodiments, not every beacon signal may include a DTIM message and the WLAN communication device 120 may abandon the deep sleep mode for receiving only those beacon signals that contain a DTIM message. In still other embodiments, the WLAN communication device 120 may negotiate the duration of the deep sleep mode with the WLAN communication counterpart before entering the deep sleep mode. According to an embodiment, the WLAN communication device 120 may automatically enter the sleep mode upon being activated, e.g., after a reset of the WLAN communication device 120.
- embodiments may improve the efficiency of a WLAN-compatible computer system by reducing the system power consumption.
- System efficiency may be measured, e.g., in terms of the amount of data transmitted/received in proportion to the power consumed.
- the described embodiments may provide an extended power reduction for a WLAN system with main crystal oscillator switch-off.
- the WLAN system may be switched off between two receive data frames. This may contain a switch-off of the chips and the main crystal oscillator.
- a separate clock source may be used for the wakeup timer and the system may have a controller which computes the next wakeup event.
- the presented deep sleep mode for a WLAN system may be applied in combination with AMD's Aml770 and/or Aml773 WLAN products.
- This invention may generally be applicable to WLAN communication devices.
Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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GB0616319A GB2427987B (en) | 2004-02-27 | 2005-02-24 | Deep sleep mode for WLAN communication systems |
JP2007501010A JP2007526695A (en) | 2004-02-27 | 2005-02-24 | Deep sleep mode of WLAN communication system |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004009695.3 | 2004-02-27 | ||
DE102004009695A DE102004009695A1 (en) | 2004-02-27 | 2004-02-27 | Efficient power-saving mode for WLAN communication systems |
US10/925,112 US7561541B2 (en) | 2004-02-27 | 2004-08-24 | Deep sleep mode for WLAN communication systems |
US10/925,112 | 2004-08-24 |
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WO2005086428A1 true WO2005086428A1 (en) | 2005-09-15 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2005/006113 WO2005086428A1 (en) | 2004-02-27 | 2005-02-24 | Deep sleep mode for wlan communicatio systems |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP2007526695A (en) |
KR (1) | KR20070001977A (en) |
GB (1) | GB2427987B (en) |
WO (1) | WO2005086428A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1777856A1 (en) * | 2005-10-19 | 2007-04-25 | ATMEL Germany GmbH | Receiving and transmitting device |
JP2008072414A (en) * | 2006-09-14 | 2008-03-27 | Hitachi Ltd | Sensor net system and sensor node |
WO2014130138A1 (en) * | 2013-02-21 | 2014-08-28 | Apple Inc. | Scheduled absence on a wireless local area network |
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US5790941A (en) * | 1993-06-29 | 1998-08-04 | Pacific Communication Sciences, Inc. | Method and apparatus for regenerating the symbol clock of a cellular telephone following a sleep cycle |
US5910944A (en) * | 1997-02-28 | 1999-06-08 | Motorola, Inc. | Radio telephone and method for operating a radiotelephone in slotted paging mode |
WO2001069859A1 (en) * | 2000-03-17 | 2001-09-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Mobile terminal sleep phase assignment and announcement in a wireless local area network |
US20030212531A1 (en) * | 2002-05-13 | 2003-11-13 | Kerr John S. | Synchronizing clock enablement in an electronic device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2713197B2 (en) * | 1994-12-22 | 1998-02-16 | 日本電気株式会社 | Wireless data communication device |
JPH10190568A (en) * | 1996-12-27 | 1998-07-21 | Matsushita Electric Ind Co Ltd | Radio receiving device |
JP2004040373A (en) * | 2002-07-02 | 2004-02-05 | Canon Inc | Wireless terminal and control method thereof |
-
2005
- 2005-02-24 GB GB0616319A patent/GB2427987B/en not_active Expired - Fee Related
- 2005-02-24 JP JP2007501010A patent/JP2007526695A/en active Pending
- 2005-02-24 WO PCT/US2005/006113 patent/WO2005086428A1/en active Application Filing
- 2005-02-24 KR KR1020067017399A patent/KR20070001977A/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5790941A (en) * | 1993-06-29 | 1998-08-04 | Pacific Communication Sciences, Inc. | Method and apparatus for regenerating the symbol clock of a cellular telephone following a sleep cycle |
US5910944A (en) * | 1997-02-28 | 1999-06-08 | Motorola, Inc. | Radio telephone and method for operating a radiotelephone in slotted paging mode |
WO2001069859A1 (en) * | 2000-03-17 | 2001-09-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Mobile terminal sleep phase assignment and announcement in a wireless local area network |
US20030212531A1 (en) * | 2002-05-13 | 2003-11-13 | Kerr John S. | Synchronizing clock enablement in an electronic device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1777856A1 (en) * | 2005-10-19 | 2007-04-25 | ATMEL Germany GmbH | Receiving and transmitting device |
US7596365B2 (en) | 2005-10-19 | 2009-09-29 | Atmel Germany Gmbh | Device for transmitting and receiving |
JP2008072414A (en) * | 2006-09-14 | 2008-03-27 | Hitachi Ltd | Sensor net system and sensor node |
WO2014130138A1 (en) * | 2013-02-21 | 2014-08-28 | Apple Inc. | Scheduled absence on a wireless local area network |
US8917709B2 (en) | 2013-02-21 | 2014-12-23 | Apple Inc. | Scheduled absence on a wireless local area network |
Also Published As
Publication number | Publication date |
---|---|
KR20070001977A (en) | 2007-01-04 |
JP2007526695A (en) | 2007-09-13 |
GB2427987B (en) | 2008-12-17 |
GB2427987A (en) | 2007-01-10 |
GB0616319D0 (en) | 2006-09-27 |
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