WO2005101499A3 - Methods of forming solder bumps on exposed metal pads and related structures - Google Patents

Methods of forming solder bumps on exposed metal pads and related structures Download PDF

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Publication number
WO2005101499A3
WO2005101499A3 PCT/US2005/012029 US2005012029W WO2005101499A3 WO 2005101499 A3 WO2005101499 A3 WO 2005101499A3 US 2005012029 W US2005012029 W US 2005012029W WO 2005101499 A3 WO2005101499 A3 WO 2005101499A3
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WO
WIPO (PCT)
Prior art keywords
methods
related structures
barrier layer
solder bumps
metal pads
Prior art date
Application number
PCT/US2005/012029
Other languages
French (fr)
Other versions
WO2005101499A2 (en
Inventor
J Daniel Mis
Original Assignee
Unitive Int Ltd
J Daniel Mis
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Publication date
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Application filed by Unitive Int Ltd, J Daniel Mis filed Critical Unitive Int Ltd
Publication of WO2005101499A2 publication Critical patent/WO2005101499A2/en
Publication of WO2005101499A3 publication Critical patent/WO2005101499A3/en

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Abstract

A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.
PCT/US2005/012029 2004-04-13 2005-04-12 Methods of forming solder bumps on exposed metal pads and related structures WO2005101499A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56186304P 2004-04-13 2004-04-13
US60/561,863 2004-04-13

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Publication Number Publication Date
WO2005101499A2 WO2005101499A2 (en) 2005-10-27
WO2005101499A3 true WO2005101499A3 (en) 2006-01-05

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