WO2005109649A1 - Clock capture in clock synchronization circuitry - Google Patents
Clock capture in clock synchronization circuitry Download PDFInfo
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- WO2005109649A1 WO2005109649A1 PCT/US2005/015904 US2005015904W WO2005109649A1 WO 2005109649 A1 WO2005109649 A1 WO 2005109649A1 US 2005015904 W US2005015904 W US 2005015904W WO 2005109649 A1 WO2005109649 A1 WO 2005109649A1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
Definitions
- This invention relates to the "capture" of a synchronized clock signal in clock synchronization circuitry. More particularly, this invention relates to clock synchronization circuitry that temporarily provides a synchronized clock output signal without a reference clock input signal . This invention also relates to clock synchronization circuitry that provides a synchronized clock output signal with little or no jitter caused by the reference clock input signal .
- Clock synchronization circuitry is used to generate a synchronized clock signal based on a reference clock signal.
- the synchronized clock signal is ideally in phase with the reference clock signal.
- One type of clock synchronization circuit is a delay- locked loop (DLL) .
- DLL uses a variable delay circuit to add phase delay to the input reference clock signal before it is output from the DLL.
- the DLL uses a phase detector to measure the phase difference between the output of the DLL and the reference clock and to adjust the variable delay to minimize the phase difference.
- Another type of clock synchronization circuit is a synchronous mirror delay (SMD) .
- SMD synchronous mirror delay
- the SMD uses a matched pair of delay arrays, a forward delay array and a backward delay array, to output a delayed clock signal synchronized to the input reference clock signal.
- the reference clock signal is input into the forward delay array.
- a mirror control circuit is triggered to transfer the clock signal from the forward delay array to the same delay stage of the backward delay array.
- the clock signal spends the same amount of time in the backward delay array as it does in the forward delay array before being output by the SMD.
- the total delay through both delay arrays synchronizes the output clock signal to the reference clock signal.
- MCD measure-controlled delay
- the input reference clock signal is provided to two delay arrays, a measure delay array and a forward delay array. After a set number of clock cycles, a measure circuit is triggered to (1) measure the progress of the clock signal propagating through the measure delay array and (2) output the clock signal from the forward delay array at the same delay point as measured in the measure delay array.
- these types of clock synchronization circuits may be used to control the precise timing of memory access. Each of these circuits requires an input reference signal in order to generate the synchronized clock signal. During a power-down state, turning off as much circuitry as possible reduces power consumption.
- the reference signal, its associated clock distribution circuitry, and the clock synchronization circuitry are not typically turned off during a power-down state. This is so because many clock cycles are needed to output a valid synchronized clock signal after exiting a power-down state, and high speed memory devices require the presence of synchronized clock signals immediately upon exiting the power-down state.
- the reference clock signal distribution circuitry may be powered-down.
- the output of synchronization circuitry may also be susceptible to the jitter of the input signal.
- Jitter is short-term random variations in the timing of a periodic signal. In a clocked system, these random variations in the timing of a clock signal may cause timing errors. [0008] In view of the foregoing, it would be desirable to be able to provide clock synchronization circuitry that reduces input referred jitter in the synchronized clock signal .
- clock synchronization circuitry is provided with a clock capturing feedback loop. After the clock synchronization circuitry is locked to the input reference clock signal, the clock synchronization circuitry can switch its input from the input reference clock signal to the fed back synchronized clock output signal. The clock synchronization circuitry can then continue to oscillate with the captured synchronized clock output signal independent of the reference clock signal. This allows the clock synchronization circuitry to provide a synchronized clock output while the input reference clock signal distribution circuitry is shut down (e.g., because of a power down) .
- the invention also provides clock capturing synchronization circuitry with a duty cycle correction circuit (DCC) or a pulse generator to correct or regenerate the oscillating synchronized clock signal and to reduce any signal degradation which may occur in the circuit. This advantageously allows the clock synchronization circuitry to operate for longer periods of time without the input reference clock signal.
- the invention also provides clock synchronization circuitry that reduces input referred jitter. When the synchronized clock signal is fed back and processed at the input of the clock synchronization circuitry instead of the reference clock signal, the jitter present in the reference clock signal is no longer propagated through the clock synchronization circuitry to the synchronized clock output .
- FIG. 1 is a block diagram of a typical delay- locked loop (DLL) ;
- FIG. 2 is a block diagram of a clock capturing DLL according to the invention;
- FIG. 3 is a timing diagram of input and output signals of an unlocked clock in a clock capturing DLL according to the inven ion;
- FIG. 4 is a timing diagram of input and output signals of a locked clock in a clock capturing DLL according to the invention;
- FIG. 5 is a block diagram of a clock capturing DLL including a pulse generator according to the invention;
- FIG. 6 is a block diagram of a typical Synchronous Mirror Delay (SMD) ;
- FIG. 7 is a block diagram of a clock capturing SMD according to the invention;
- FIG. 8 is a block diagram of a typical Measure-Controlled Delay (MCD) ;
- FIG. 9 is a block diagram of a clock capturing MCD according to the invention; and
- FIG. 10 is a block diagram of a system that incorporates the invention.
- FIG. l shows a typical delay-locked loop (DLL) synchronization circuit 100.
- Reference clock signal RCLK is input to DLL 100, and output signal DLLCLK is a delayed, synchronized version of clock signal RCLK.
- the phase difference between RCLK and DLLCLK is ideally zero.
- DLL 100 typically includes input buffer 102, variable delay 104, output buffer 106, delay model 108, phase detector 110, and delay control 112.
- variable delay 104 Following forward signal path 101, reference clock signal RCLK enters variable delay 104 through input buffer 102.
- Input buffer 102 delays the input clock signal RCLK by delay Dl .
- Variable delay 104 adds an adjustable amount of delay and outputs the clock signal through output buffer 106 as DLL output signal, DLLCLK.
- Output buffer 106 delays the clock signal by delay D2.
- Delay D2 may also include other delays at the output of DLL 100, such as, for example, a clock distribution tree delay or output driver delay.
- Variable delay 104 is ideally set to a value that causes DLLCLK to be in phase with RCLK. In order for DLLCLK to be in phase with RCLK, the total delay of forward signal path 101 should be a multiple of the
- variable delay 104 is ideally set to
- N*tck - (Dl + D2) i.e., the total desired delay minus
- Delay model 108 models the approximate delay of (Dl + D2) (i.e., the sum of the approximate delays of input buffer 102 and output buffer 106) .
- the sum of the delays of variable delay 104 and delay model 108 is ideally equal to the
- Phase detector 110 measures the phase difference between reference input clock signal RCLK and synchronized output clock signal DLLCLK. Phase detector 110 controls delay control 112, which adjusts the delay of variable delay 104. Variable delay 104 is adjusted to minimize, if not eliminate, the phase difference measured by phase detector 110 between RCLK and DLLCLK. After variable delay 104 has been adjusted to its optimal setting, the DLL is said to be locked.
- FIG. 2 shows clock capturing DLL 200 in accordance with the invention.
- clock capturing DLL 200 includes input buffer 202, variable delay 204, output buffer 206, delay model 208, phase detector 210, and delay control 212, which all operate similarly or identically to their corresponding counterparts in DLL 100.
- DLL 200 also preferably includes multiplexer 214. The delay introduced by multiplexer 214 is accounted for by delay model 208. [0032] After variable delay 204 is adjusted and DLL 200 is locked, multiplexer 214 can be switched using control input SEL to pass the feedback signal from path 203 instead of input reference clock RCLK. Thus, feedback signal path 203 can be coupled to forward signal path 201, forming a signal loop.
- DLL 200 will ideally continue to oscillate with the same phase and period in this "clock captured configuration.”
- phase detector 210 may be disabled when the clock is captured or it may continue to measure phase difference and adjust variable delay 204, if necessary.
- Phase detector 210 may also be adjusted just prior to switching into the clock captured configuration to compensate for a phase error which may occur after the clock is captured.
- FIGS. 3 and 4 show signal timings before and after the clock is captured, respectively. To simplify the illustrations, the delays of input buffer 202 (Dl) , output buffer 106 (D2) , and delay model 108 (D1+D2) are assumed to be zero.
- SCLK is the clock signal passed through multiplexer 214.
- SEL is set to pass RCLK through multiplexer 214 to variable delay 204.
- the phase difference between the output of multiplexer 214, SCLK, and FBCLK at 302 shows that the DLL is not yet locked.
- SEL is set at 402 to pass RCLK through multiplexer 214 to variable delay 204.
- SCLK and FBCLK are shown in-phase (i.e., no phase difference), so SEL can be switched to pass the feedback signal through multiplexer 214 to variable delay 204.
- the clock is now captured and DLL 200 will continue to oscillate and maintain its locked state.
- the reference clock signal can be removed (and/or its associated distribution circuitry disabled) without affecting the oscillation of the circuit. This may be desirable, for example, in double data rate (DDR) synchronous dynamic random access memory (SDRAM) .
- DDR double data rate
- SDRAM synchronous dynamic random access memory
- the reference clock and the clock synchronization circuitry are not turned off, because they provide the necessary clocking to allow a read operation one clock cycle after exiting the power-down state. If the clock synchronization circuitry were turned off, it would take many clock cycles for it to be turned back on and to output a properly synchronized clock signal.
- the clock synchronization circuitry can capture the clock signal before entering a power-down state, .
- the reference clock distribution circuitry can be shut down, removing the reference clock.
- the synchronization circuitry continues to oscillate temporarily with the proper period and phase.
- the clock synchronization circuitry remains on and ready for the system to exit the power down state, but power is saved by shutting down the reference clock distribution circuitry.
- This embodiment of the invention has the advantage of reducing power consumption during an active power-down, while producing the necessary clock signal edges to allow the memory to be read when the active power-down state is exited.
- SEL can be switched back to pass the reference clock signal through multiplexer 214 to variable delay 204.
- the reference clock once again oscillates through DLL 200 instead of the captured clock signal. Throughout the transitions from the clock captured state and back, there is usually little, if any disturbance to the output clock signal.
- multiplexer 214 may be replaced with phase mixing circuitry. Phase mixing circuitry may be able to transition more smoothly between the fed-back clock signal and the reference clock signal and may avoid sudden discontinuity. [0038] Furthermore, capturing the clock signal in the clock synchronization circuitry reduces jitter in the synchronized clock output signal caused by the jitter in the reference signal.
- reference clock signal RCLK is no longer used to generate DLL output DLLCLK. Therefore, any jitter in reference clock signal RCLK will no longer propagate through the synchronization circuit and affect output signal DLLCLK. However, if RCLK is still available, it can be used by phase detector 204 to maintain the phase synchronization of DLLCLK even though it is no longer used to generate DLLCLK.
- FIG. 5 shows another embodiment of a clock capturing DLL in accordance with the invention.
- clock capturing DLL 500 includes input buffer 502, variable delay 504, output buffer 506, delay model 508, phase detector 510, delay control 512, and multiplexer 514, which all operate similarly or identically to their corresponding counterparts in DLL 200.
- DLL 500 also preferably includes pulse generator 516.
- Pulse generator 516 connected to the output of variable delay 504, generates a pulse with a predetermined width synchronized to the oscillating clock signal. This pulse maintains the duty cycle and general integrity of the oscillating clock signal and prevents the oscillating clock signal from degrading. Thus, the synchronized output clock signal can be provided for a longer period of time.
- pulse generator 516 may be replaced by a duty cycle correction circuit (DCC) .
- the DCC corrects the duty cycle distortion of the oscillating clock signal and also prevents the clock signal from degrading.
- FIG. 6 shows a typical Synchronous Mirror Delay (SMD) and FIG. 7 shows a clock capturing SMD according to the invention.
- FIG. 8 shows a typical Measure- Controlled Delay (MCD) and FIG. 9 shows a clock capturing MCD according to the invention.
- FIG. 6 shows a typical Synchronous Mirror Delay (SMD)
- FIG. 7 shows a clock capturing SMD according to the invention.
- FIG. 8 shows a typical Measure- Controlled Delay (MCD)
- FIG. 9 shows a clock capturing MCD according to the invention.
- Forward delay array 606 and backward delay array 610 are made up of a series of delay elements. Ideally, the delay characteristics of forward delay array 606 and backward delay array 610 are identical. Forward delay array 606 has a series of parallel outputs corresponding respectively to each delay element, and backward delay array 610 has a series of parallel inputs corresponding respectively to each of its delay elements. After a clock signal is input to forward delay array 606, it begins to propagate through the delay elements.
- mirror control circuit 608 driven by divide-by-n counter 612, causes the clock signal to be output from the Kth delay element of forward delay array 606 and input to the Kth delay element of backward delay array 610.
- the clock signal After the clock signal is input to backward delay array 610, it propagates through the same number of delay elements as it did in forward delay array 606 before exiting backward delay array 610.
- the clock signal delay introduced by forward delay array 606 is equal to the delay introduced by backward delay array 610 and the total array delay is equal to 2* (tck- (D1+D2) ) .
- reference clock signal RCLK is input through input buffer 602 and delay model 604 and enters forward delay array 606.
- Input and output buffers 602 and 614 and delay model 604 have similar delay characteristics as in the previously described DLL circuitry.
- divide-by-N counter 606 counts N clock cycles, it triggers mirror control circuit 608.
- the number N is based on the length of the delay array and speed of the clock signal. N may be fixed by the design of the clock synchronization circuitry or may be variable.
- Mirror control circuit 608 causes the clock signal in forward delay array 606 to be transferred to backward delay array 610. After N more clock cycles, the synchronized output clock signal is output through output buffer 614.
- FIG. 7 illustrates clock capturing SMD 700 in accordance with the invention.
- SMD 700 includes input buffer 702, delay model 704, forward delay array 706, mirror control circuit 708, backward delay array 710, divide-by-N counter 712, and output buffer 714, which all operate similarly or identically to their corresponding counterparts in SMD 600.
- SMD 700 also includes feedback path 703 which preferably includes multiplexer 716 and delay model 718.
- Input reference clock signal RCLK is delayed and synchronously output as DLLCLK. However, additional feedback path 703 allows the synchronized clock signal to be captured and oscillated.
- Delay model 718 is preferably identical to delay model 704 and provides a total feedback signal path delay that equals the total delay of forward signal path 701 (i.e. , 2*N*tck) .
- FIG. 8 illustrates typical MCD 800, which includes input buffer 802, delay model 804, measure delay array 806, measure circuit 808, forward delay array 810, divide-by-n counter 812, and output buffer 814.
- Measure delay array 806 and forward delay array 810 each include a series of delay elements. Ideally, measure delay array 806 and forward delay array 810 provide identical amounts of delay.
- the reference clock signal is input to measure delay array 806 and forward delay array 810.
- the reference clock signal propagates through the delay elements of both delay arrays.
- Measure circuit 808 is enabled before the clock signal reaches the final delay element in measure delay array 806.
- Measure circuit 808 measures the progress of the clock signal through the delay elements of measure delay array 806, and sets forward delay array 810 to output its clock signal after that same number of delay elements. Thus, for example, if the clock signal had propagated through the Kth delay element of measure delay array 806, forward delay array 810 will be set to output the clock signal after K delay elements.
- reference clock signal RCLK is input though input buffer 802 and delay model 804 and enters measure delay array 806. RCLK is simultaneously input through input buffer 802 to forward delay array 810. The clock signal is propagated through delay model 804 and measure delay array 806 to measure the proper delay to set for the forward delay array 810.
- the input and output buffers 802 and 814 and delay model 804 have delay characteristics similar to the previously described DLL and SMD circuits.
- Measure circuit 808 measures the number of unit delays that the clock signal has propagated in measure delay array 806 and sets forward delay array 810 to use the same number of unit delay elements.
- the clock signal is then output from forward delay array 810 at the delay element set by measure circuit 808. (Note that reference clock signal RCLK propagates through delay model 804 before being input to measure delay array 806, and the RCLK is input to forward delay array 810 without this additional delay.
- the clock signal propagates through forward delay array 810 more quickly than through measure delay array 806. Therefore, some clock pulses may be lost (or have incorrect phase) before the proper delay element of forward delay array 810 is selected by measure delay array 806. This delay (or time with incorrect phase) is part of the initialization of the SMD.) The total
- FIG. 9 illustrates clock capturing MCD 900 in accordance with the invention.
- MCD 900 includes input buffer 902, delay model 904, forward delay array 906, mirror control circuit 908, backward delay array 910, divide-by-n counter 912, and output buffer 914, which all operate similarly or identically to their corresponding counterparts in MCD 800.
- MCD 900 also includes feedback path 903 which preferably includes multiplexers 916 and 918.
- input reference clock signal RCLK is delayed and synchronously output as DLLCLK.
- Feedback path 903 allows the synchronized clock signal to be captured and oscillated through MCD 900.
- Multiplexers 916 and 918 allow the feedback signal to be fed to delay model 904 and forward delay array 910.
- the total delay of feedback signal path 903 is equal to
- forward signal path 901 (i.e., N*tck) .
- FIG. 10 shows a system that incorporates the invention.
- System 1000 includes a plurality of DRAM chips 1010, a processor 1070, a memory controller 1072, input devices 1074, output devices 1076, and optional storage devices 1078. Data and control signals are transferred between processor 1070 and memory controller 1072 via bus 1071. Similarly, data and control signals are transferred between memory controller 1072 and DRAM chips 1010 via bus 1073.
- One or more DRAM chips 1010 include clock capturing synchronization circuitry in accordance with the invention. The clock capturing circuitry may also be included in memory controller 1072. Moreover, clock capturing synchronization circuitry in accordance with the invention may be included in any part of the system that requires clock synchronization.
- Such synchronization circuitry can be used to perform read operations when entering power down states and/or to reduce input referred jitter.
- Input devices 1074 can include, for example, a keyboard, a mouse, a touch-pad display screen, or any other appropriate device that allows a user to enter information into system 1000.
- Output devices 1076 can include, for example, a video display unit, a printer, or any other appropriate device capable of providing output data to a user. Note that input devices 1074 and output devices 1076 can alternatively be a single input/output device.
- Storage devices 1078 can include, for example, one or more disk or tape drives .
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2007511647A JP5035544B2 (en) | 2004-05-05 | 2005-05-05 | Clock capture in clock synchronization circuit |
EP05751961A EP1751869A1 (en) | 2004-05-05 | 2005-05-05 | Clock capture in clock synchronization circuitry |
Applications Claiming Priority (2)
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US10/840,015 US7095261B2 (en) | 2004-05-05 | 2004-05-05 | Clock capture in clock synchronization circuitry |
US10/840,015 | 2004-05-05 |
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WO2005109649A1 true WO2005109649A1 (en) | 2005-11-17 |
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PCT/US2005/015904 WO2005109649A1 (en) | 2004-05-05 | 2005-05-05 | Clock capture in clock synchronization circuitry |
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US (5) | US7095261B2 (en) |
EP (1) | EP1751869A1 (en) |
JP (1) | JP5035544B2 (en) |
KR (1) | KR20070005016A (en) |
TW (1) | TW200623645A (en) |
WO (1) | WO2005109649A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100739822B1 (en) | 2006-08-08 | 2007-07-13 | 한국표준과학연구원 | A synchronization method of remote clock by using pulse second |
US8094769B2 (en) | 2008-07-25 | 2012-01-10 | Freescale Semiconductor, Inc. | Phase-locked loop system with a phase-error spreading circuit |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6839301B2 (en) * | 2003-04-28 | 2005-01-04 | Micron Technology, Inc. | Method and apparatus for improving stability and lock time for synchronous circuits |
US6937077B2 (en) * | 2003-09-23 | 2005-08-30 | Micron Technology, Inc. | Apparatus and method for suppressing jitter within a clock signal generator |
US7095261B2 (en) * | 2004-05-05 | 2006-08-22 | Micron Technology, Inc. | Clock capture in clock synchronization circuitry |
US7516029B2 (en) * | 2004-06-09 | 2009-04-07 | Rambus, Inc. | Communication channel calibration using feedback |
KR100632368B1 (en) * | 2004-11-23 | 2006-10-09 | 삼성전자주식회사 | Internal Clock Generation Circuit with Improved Locking Speed and Included Analog Synchronous Mirror Delay |
US7119596B2 (en) * | 2004-12-22 | 2006-10-10 | Lsi Logic Corporation | Wide-range programmable delay line |
US7130226B2 (en) * | 2005-02-09 | 2006-10-31 | Micron Technology, Inc. | Clock generating circuit with multiple modes of operation |
KR100713082B1 (en) * | 2005-03-02 | 2007-05-02 | 주식회사 하이닉스반도체 | Delay locked loop for controlling duty rate of clock |
US8164368B2 (en) * | 2005-04-19 | 2012-04-24 | Micron Technology, Inc. | Power savings mode for memory systems |
JP4520394B2 (en) * | 2005-10-27 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | DLL circuit and test method thereof |
US7405996B2 (en) * | 2006-04-21 | 2008-07-29 | Infineon Technologies Ag | System and method to synchronize signals in individual integrated circuit components |
KR100811263B1 (en) * | 2006-06-29 | 2008-03-07 | 주식회사 하이닉스반도체 | DCC circuit and DLL circuit with DCC |
KR100809692B1 (en) * | 2006-08-01 | 2008-03-06 | 삼성전자주식회사 | Delay locked loop circuit having low jitter and jitter reducing method thereof |
US7671648B2 (en) * | 2006-10-27 | 2010-03-02 | Micron Technology, Inc. | System and method for an accuracy-enhanced DLL during a measure initialization mode |
US7865756B2 (en) * | 2007-03-12 | 2011-01-04 | Mosaid Technologies Incorporated | Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices |
US7495487B2 (en) * | 2007-04-09 | 2009-02-24 | Micron Technology, Inc. | Delay-locked loop (DLL) system for determining forward clock path delay |
US7965111B2 (en) * | 2008-04-29 | 2011-06-21 | Qualcomm Incorporated | Method and apparatus for divider unit synchronization |
KR100949272B1 (en) * | 2008-07-10 | 2010-03-25 | 주식회사 하이닉스반도체 | Semiconductor device and operation method thereof |
US7999585B2 (en) * | 2009-06-25 | 2011-08-16 | Analog Devices, Inc. | Calibrating multiplying-delay-locked-loops (MDLLS) |
US7969216B2 (en) * | 2009-11-06 | 2011-06-28 | Bae Systems Information And Electronic Systems Integration Inc. | System and method for improved timing synchronization |
TWI551056B (en) * | 2011-03-07 | 2016-09-21 | 國立交通大學 | A programmable clock generator for being used in dynamic-voltage-and-frequency-scaling (dvfs) operated in sub- and near-threshold region |
US8604850B2 (en) * | 2011-03-29 | 2013-12-10 | Micron Technology, Inc. | Measurement initialization circuitry |
EP2512033B1 (en) * | 2011-04-13 | 2013-09-11 | Siemens Aktiengesellschaft | A clock generation system |
KR101899084B1 (en) * | 2011-10-20 | 2018-09-18 | 에스케이하이닉스 주식회사 | Semiconductor integrated circuit and method of driving the same |
DE102013200033B4 (en) * | 2012-10-10 | 2023-06-15 | Rohde & Schwarz GmbH & Co. Kommanditgesellschaft | Method and system for determining the scattering parameters of a frequency-converting test object |
US8957714B2 (en) * | 2013-03-14 | 2015-02-17 | Qualcomm Incorporated | Measure-based delay circuit |
CN105337611A (en) * | 2014-07-04 | 2016-02-17 | 硅存储技术公司 | Numerical control delay-locked ring reference generator |
US9825618B2 (en) * | 2015-01-20 | 2017-11-21 | Mediatek Singapore Pte. Ltd. | Tunable delay circuit and operating method thereof |
US11595032B2 (en) | 2021-05-27 | 2023-02-28 | Skyworks Solutions, Inc. | Signal delay control using a recirculating delay loop and a phase interpolator |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6208183B1 (en) * | 1999-04-30 | 2001-03-27 | Conexant Systems, Inc. | Gated delay-locked loop for clock generation applications |
US20020190766A1 (en) * | 2000-08-28 | 2002-12-19 | Micron Technology, Inc. | Scheme for delay locked loop reset protection |
US20030081472A1 (en) * | 2001-08-29 | 2003-05-01 | Feng Lin | System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal |
US20040044918A1 (en) * | 2002-08-29 | 2004-03-04 | Dermott Ross E. | Measure-controlled delay circuit with reduced playback error |
US20040057331A1 (en) * | 2001-05-25 | 2004-03-25 | Micron Technology, Inc. | Synchronous mirror delay with reduced delay line taps |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6216617A (en) * | 1985-07-15 | 1987-01-24 | Nec Corp | Pll frequency synthesizer |
DE3544342C1 (en) * | 1985-12-14 | 1987-05-07 | Philips Patentverwaltung | Control circuit for balancing a runtime line |
JPH0348526A (en) * | 1989-07-17 | 1991-03-01 | Toyo Commun Equip Co Ltd | Oscillating circuit |
JPH0355923A (en) * | 1989-07-25 | 1991-03-11 | Toyo Commun Equip Co Ltd | Control method for local oscillation circuit of receiver |
JP2710214B2 (en) * | 1994-08-12 | 1998-02-10 | 日本電気株式会社 | Phase locked loop circuit |
JP3630870B2 (en) * | 1996-04-03 | 2005-03-23 | 株式会社ルネサステクノロジ | System clock generation circuit |
JPH10149682A (en) * | 1996-09-20 | 1998-06-02 | Hitachi Ltd | Semiconductor device and computer system including the semiconductor device |
US5910740A (en) * | 1997-06-18 | 1999-06-08 | Raytheon Company | Phase locked loop having memory |
JPH11110065A (en) * | 1997-10-03 | 1999-04-23 | Mitsubishi Electric Corp | Internal clock signal generating circuit |
KR100269316B1 (en) * | 1997-12-02 | 2000-10-16 | 윤종용 | Delayed locked loop & phase locked loop merged with synchronous delay circuit |
JPH11316617A (en) * | 1998-05-01 | 1999-11-16 | Mitsubishi Electric Corp | Semiconductor circuit device |
JP2000076852A (en) * | 1998-08-25 | 2000-03-14 | Mitsubishi Electric Corp | Synchronous semiconductor storage |
JP2000235791A (en) * | 1999-02-15 | 2000-08-29 | Toshiba Corp | Clock synchronism delay control circuit |
KR100335499B1 (en) * | 1999-12-30 | 2002-05-08 | 윤종용 | Clock generating circuit for compensating a delay difference using a closed loop synchronous mirror delay structure |
US6556289B1 (en) * | 2000-06-28 | 2003-04-29 | Roygbiv, Llc | System for measuring radiance |
JP2002093167A (en) * | 2000-09-08 | 2002-03-29 | Mitsubishi Electric Corp | Semiconductor memory |
US6617936B2 (en) * | 2001-02-20 | 2003-09-09 | Velio Communications, Inc. | Phase controlled oscillator |
US6586979B2 (en) * | 2001-03-23 | 2003-07-01 | Micron Technology, Inc. | Method for noise and power reduction for digital delay lines |
US6556489B2 (en) * | 2001-08-06 | 2003-04-29 | Micron Technology, Inc. | Method and apparatus for determining digital delay line entry point |
US6850107B2 (en) * | 2001-08-29 | 2005-02-01 | Micron Technology, Inc. | Variable delay circuit and method, and delay locked loop, memory device and computer system using same |
US6759911B2 (en) * | 2001-11-19 | 2004-07-06 | Mcron Technology, Inc. | Delay-locked loop circuit and method using a ring oscillator and counter-based delay |
KR100424180B1 (en) * | 2001-12-21 | 2004-03-24 | 주식회사 하이닉스반도체 | A delay locked loop circuit with duty cycle correction function |
US6774687B2 (en) * | 2002-03-11 | 2004-08-10 | Micron Technology, Inc. | Method and apparatus for characterizing a delay locked loop |
US6621316B1 (en) * | 2002-06-20 | 2003-09-16 | Micron Technology, Inc. | Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line |
US6727740B2 (en) * | 2002-08-29 | 2004-04-27 | Micron Technology, Inc. | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals |
US6839301B2 (en) * | 2003-04-28 | 2005-01-04 | Micron Technology, Inc. | Method and apparatus for improving stability and lock time for synchronous circuits |
US6937077B2 (en) * | 2003-09-23 | 2005-08-30 | Micron Technology, Inc. | Apparatus and method for suppressing jitter within a clock signal generator |
US7199741B2 (en) * | 2003-10-24 | 2007-04-03 | Infineon Technologies Ag | Method for digital/analog conversion and corresponding digital/analog converter device |
US7098714B2 (en) * | 2003-12-08 | 2006-08-29 | Micron Technology, Inc. | Centralizing the lock point of a synchronous circuit |
US6982579B2 (en) * | 2003-12-11 | 2006-01-03 | Micron Technology, Inc. | Digital frequency-multiplying DLLs |
US7095261B2 (en) * | 2004-05-05 | 2006-08-22 | Micron Technology, Inc. | Clock capture in clock synchronization circuitry |
-
2004
- 2004-05-05 US US10/840,015 patent/US7095261B2/en not_active Expired - Fee Related
-
2005
- 2005-05-05 JP JP2007511647A patent/JP5035544B2/en not_active Expired - Fee Related
- 2005-05-05 EP EP05751961A patent/EP1751869A1/en not_active Ceased
- 2005-05-05 WO PCT/US2005/015904 patent/WO2005109649A1/en active Application Filing
- 2005-05-05 TW TW094114577A patent/TW200623645A/en unknown
- 2005-05-05 KR KR1020067025208A patent/KR20070005016A/en not_active Application Discontinuation
-
2006
- 2006-07-18 US US11/489,117 patent/US7414444B2/en not_active Expired - Fee Related
- 2006-07-18 US US11/489,367 patent/US7423462B2/en not_active Expired - Fee Related
- 2006-07-18 US US11/489,693 patent/US7423463B2/en not_active Expired - Fee Related
- 2006-07-18 US US11/489,369 patent/US7368965B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6208183B1 (en) * | 1999-04-30 | 2001-03-27 | Conexant Systems, Inc. | Gated delay-locked loop for clock generation applications |
US20020190766A1 (en) * | 2000-08-28 | 2002-12-19 | Micron Technology, Inc. | Scheme for delay locked loop reset protection |
US20040057331A1 (en) * | 2001-05-25 | 2004-03-25 | Micron Technology, Inc. | Synchronous mirror delay with reduced delay line taps |
US20030081472A1 (en) * | 2001-08-29 | 2003-05-01 | Feng Lin | System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal |
US20040044918A1 (en) * | 2002-08-29 | 2004-03-04 | Dermott Ross E. | Measure-controlled delay circuit with reduced playback error |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100739822B1 (en) | 2006-08-08 | 2007-07-13 | 한국표준과학연구원 | A synchronization method of remote clock by using pulse second |
US8094769B2 (en) | 2008-07-25 | 2012-01-10 | Freescale Semiconductor, Inc. | Phase-locked loop system with a phase-error spreading circuit |
Also Published As
Publication number | Publication date |
---|---|
JP5035544B2 (en) | 2012-09-26 |
US20060255845A1 (en) | 2006-11-16 |
US7095261B2 (en) | 2006-08-22 |
US7423463B2 (en) | 2008-09-09 |
KR20070005016A (en) | 2007-01-09 |
US7414444B2 (en) | 2008-08-19 |
US7368965B2 (en) | 2008-05-06 |
TW200623645A (en) | 2006-07-01 |
US20060255846A1 (en) | 2006-11-16 |
US7423462B2 (en) | 2008-09-09 |
EP1751869A1 (en) | 2007-02-14 |
JP2007536831A (en) | 2007-12-13 |
US20060255844A1 (en) | 2006-11-16 |
US20050248377A1 (en) | 2005-11-10 |
US20060255847A1 (en) | 2006-11-16 |
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