WO2005111874A3 - Integrated circuit layout design methodology with process variation bands - Google Patents

Integrated circuit layout design methodology with process variation bands Download PDF

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Publication number
WO2005111874A3
WO2005111874A3 PCT/US2005/016115 US2005016115W WO2005111874A3 WO 2005111874 A3 WO2005111874 A3 WO 2005111874A3 US 2005016115 W US2005016115 W US 2005016115W WO 2005111874 A3 WO2005111874 A3 WO 2005111874A3
Authority
WO
WIPO (PCT)
Prior art keywords
variations
integrated circuit
circuit layout
layout design
process variation
Prior art date
Application number
PCT/US2005/016115
Other languages
French (fr)
Other versions
WO2005111874A2 (en
Inventor
Robles Juan A Torres
Original Assignee
Mentor Graphics Corp
Robles Juan A Torres
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=35385625&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2005111874(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Mentor Graphics Corp, Robles Juan A Torres filed Critical Mentor Graphics Corp
Priority to EP05746436.4A priority Critical patent/EP1747520B1/en
Priority to JP2007511692A priority patent/JP2007536581A/en
Publication of WO2005111874A2 publication Critical patent/WO2005111874A2/en
Publication of WO2005111874A3 publication Critical patent/WO2005111874A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/80—Technologies aiming to reduce greenhouse gasses emissions common to all road transportation technologies
    • Y02T10/82—Elements for improving aerodynamics

Abstract

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.
PCT/US2005/016115 2004-05-07 2005-05-06 Integrated circuit layout design methodology with process variation bands WO2005111874A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05746436.4A EP1747520B1 (en) 2004-05-07 2005-05-06 Integrated circuit layout design methodology with process variation bands
JP2007511692A JP2007536581A (en) 2004-05-07 2005-05-06 Integrated circuit layout design method using process variation band

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US56884904P 2004-05-07 2004-05-07
US60/568,849 2004-05-07
US65583705P 2005-02-23 2005-02-23
US60/655,837 2005-02-23

Publications (2)

Publication Number Publication Date
WO2005111874A2 WO2005111874A2 (en) 2005-11-24
WO2005111874A3 true WO2005111874A3 (en) 2006-04-13

Family

ID=35385625

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/016115 WO2005111874A2 (en) 2004-05-07 2005-05-06 Integrated circuit layout design methodology with process variation bands

Country Status (5)

Country Link
US (4) US8799830B2 (en)
EP (1) EP1747520B1 (en)
JP (5) JP2007536581A (en)
TW (1) TW200604870A (en)
WO (1) WO2005111874A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9361424B2 (en) 2004-05-07 2016-06-07 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands

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* Cited by examiner, † Cited by third party
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