WO2005117111A2 - Adhesive/spacer island structure for multiple die package - Google Patents

Adhesive/spacer island structure for multiple die package Download PDF

Info

Publication number
WO2005117111A2
WO2005117111A2 PCT/US2005/017893 US2005017893W WO2005117111A2 WO 2005117111 A2 WO2005117111 A2 WO 2005117111A2 US 2005017893 W US2005017893 W US 2005017893W WO 2005117111 A2 WO2005117111 A2 WO 2005117111A2
Authority
WO
WIPO (PCT)
Prior art keywords
die
adhesive
spacer
package
bonding region
Prior art date
Application number
PCT/US2005/017893
Other languages
French (fr)
Other versions
WO2005117111A3 (en
WO2005117111B1 (en
Inventor
Sang Ho Lee
Jong Wook Ju
Hyeog Chan Kwon
Marcos Karnezos
Original Assignee
Chippac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/969,116 external-priority patent/US20050258527A1/en
Application filed by Chippac, Inc. filed Critical Chippac, Inc.
Publication of WO2005117111A2 publication Critical patent/WO2005117111A2/en
Publication of WO2005117111A3 publication Critical patent/WO2005117111A3/en
Publication of WO2005117111B1 publication Critical patent/WO2005117111B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • a multi-chip package includes one or more integrated circuit semiconductor chips, often referred to as circuit die, stacked one onto another to provide the advantages of light weight, high density, and enhanced electrical performance.
  • each chip can be lifted by a chip-bonding tool, which is usually mounted at the end of a pick-and-place device, and mounted onto the substrate or onto a semiconductor chip mounted previously.
  • the upper die can be attached directly to the lower die without the use of spacers.
  • spacer die that is die without circuitry
  • adhesives containing spacer elements typically micro spheres, are often used to properly separate the upper and lower die. See U.S. patent numbers 5,323,060; 6,333,562; 6,340,846; 6,388,313; 6,472,758; 6,569,709; 6,593,662; 6,441,496; and U.S. patent publication number US 2003/0178710.
  • bonding pads of the chips are connected to bonding pads of the substrate with Au or Al wires during a wire bonding process to create an array of semiconductor chip devices.
  • the semiconductor chips and their associated wires connected to the substrate are encapsulated, typically using an epoxy-molding compound, to create an array of encapsulated semiconductor devices.
  • the molding compound protects the semiconductor devices from the external environment, such as physical shock and humidity. After encapsulation, the encapsulated devices are separated, typically by sawing, into individual semiconductor chip packages.
  • the invention features adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly.
  • the adhesive/spacer structure according to the invention includes a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package.
  • a package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an "upper" package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
  • the invention features an adhesive/spacer structure used to adhere first and second devices to one another at a chosen separation in a multiple-device semiconductor chip package.
  • the adhesive/spacer structure comprises a plurality of spaced- apart adhesive/spacer islands securing the first and second devices to one another at a chosen separation.
  • both the first and the second devices are die; in some embodiments the first device is a die, and the second device is a package or a heat spreader. In some embodiments both the first and the second devices are packages.
  • the adhesive/spacer structure can in some embodiments serve to provide a separation between the device that accommodates wire bonds connected to pads on a surface of one of the two devices. In other embodiments the adhesive/spacer structure serves to raise an upper device over a lower substrate to provide space for an additional component such as another die, adjacent a lower die.
  • the first die is mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate.
  • a second surface of a second device (which may be a die, or a package, or a heat spreader, for example) is positioned opposite the first surface to define a die bonding region therebetween.
  • a plurality of spaced-apart adhesive/spacer islands are within the die bonding region and secure the first die and the second device to one another at a chosen separation to create a multiple-die assembly.
  • the adhesive/spacer islands comprise spacer elements within an adhesive.
  • a material encapsulates the multiple-device assembly to create a multiple-device semiconductor chip package.
  • the invention features an adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package.
  • the adhesive/spacer structure comprises a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation.
  • the adhesive/spacer structure in such embodiments serves to provide a separation between the device that accommodates wire bonds connected to pads on a surface of one of the two die.
  • the adhesive/spacer structure serves to raise an upper die over a lower substrate to provide space for an additional component such as another die, adjacent a lower die.
  • the invention features a multiple-die semiconductor chip package having the adhesive/spacer island structure securing first and second die to one another at a chosen separation.
  • a first die is mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate.
  • a second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween.
  • a plurality of spaced-apart adhesive/spacer islands are within the die bonding region and secure the first and second die to one another at a chosen separation to create a multiple-die assembly.
  • the adhesive/spacer islands comprise spacer elements within an adhesive.
  • a material encapsulates the multiple-die assembly to create a multiple-die semiconductor chip package.
  • the invention features an adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple- die semiconductor chip assembly.
  • the first and second die define a die bonding region therebetween.
  • the adhesive/spacer structure comprises spacer elements within an adhesive.
  • the adhesive/spacer structure secures the first and second die to one another and occupies at most about 50% of the die bonding region.
  • the invention features a multiple-die semiconductor chip package.
  • a first die is mounted to a substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface.
  • Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate.
  • a second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween.
  • An adhesive/spacer structure within the die bonding region secures the first and second surfaces to one another at a chosen separation to create a multiple-die assembly.
  • the adhesive/spacer structure comprises spacer elements within an adhesive.
  • the adhesive/spacer structure occupies at most about 50% of the die bonding region.
  • a material encapsulates the multiple- die assembly to create a multiple-die semiconductor chip package.
  • the invention features a method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package assembly.
  • An adhesive/spacer material having spacer elements within an adhesive is selected.
  • the adhesive/spacer material is deposited onto a first surface of a first die at a plurality of spaced- apart positions.
  • a second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby securing the first and second die to one another at a chosen separation.
  • the selecting and depositing steps are carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.
  • the invention features a method for creating a multiple-die semiconductor chip package.
  • a first die is mounted to a substrate, the first die having a first surface with bond pads at the first surface.
  • the bond pads are connected to the substrate with wires.
  • An adhesive/spacer material comprising spacer elements within an adhesive, is selected.
  • the adhesive/spacer material is deposited onto the first surface of the first die at a plurality of spaced-apart positions.
  • a second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die assembly.
  • the selecting and depositing steps are carried out to create a plurality of spaced- apart adhesive/spacer islands following the securing step.
  • the multiple-die assembly is encapsulated to create a multiple-die semiconductor chip package.
  • the invention features a method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package assembly.
  • An adhesive/spacer material having spacer elements within an adhesive, is selected.
  • An amount of the adhesive/spacer material is chosen.
  • the chosen amount the adhesive/spacer material is deposited onto a first surface of a first die.
  • a second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation.
  • the choosing and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step.
  • the invention features a method for creating a multiple-die semiconductor chip package.
  • a first die comprising a first surface with bond pads at the first surface, is mounted to a substrate.
  • the bond pads and the substrate are connected with wires.
  • An adhesive/spacer material having spacer elements within an adhesive is selected.
  • the adhesive/spacer material is deposited onto a first surface of the first die at a plurality of spaced-apart positions.
  • a second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die assembly.
  • the selecting and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region.
  • the multiple-die assembly is encapsulated to create a multiple-die semiconductor chip package, with the encapsulating material occupying a second percentage of the die bonding region.
  • the invention features adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly.
  • the adhesive/spacer structure according to the invention includes a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation.
  • the first devices is a die; in other embodiments the first deice is a package; in still other embodiments the second device is be a package.
  • a package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an "upper" package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
  • the present invention provides several potential advantages over conventional die stacking structures, specifically silicon spacer die and conventional spacer adhesives. The number of processing steps is reduced compared to conventional packages using silicon spacer wafers. According to the present invention, material processing can be simplified, the amount of spacer material used can be reduced and package reliability and productivity can be potentially increased. [0018] Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGs. 1 and 2 are side views of conventional multiple die assemblies using a spacer die and an adhesive/spacer material to separate the upper and lower die, respectively;
  • FIGs. 3 - 5 illustrate deposition of adhesive/spacer material onto a lower die using a shower head-type of dispenser according to an aspect of the invention;
  • FIG. 6 is a side view of a multiple-die assembly made according to an aspect of the invention following the deposition step of FIG. 5 and placement of an upper die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the upper die on and securing the upper die to the lower die;
  • FIG. 7 is a top view of the assembly of FIG. 6 with the top die removed to illustrate the adhesive/spacer islands;
  • FIG. 8 illustrates an alternative embodiment of the structure shown in FIG. 7;
  • FIGs. 9 - 11 illustrate alternative embodiments of the lower die of FIG. 7 with adhesive/spacer islands having various sizes and shapes;
  • FIG. 12 illustrates a multiple-die semiconductor chip package made according to the invention by encapsulating the multiple-die assembly of FIG. 6 with an encapsulating material
  • FIGs. 13 - 15 illustrate continuous expanses of adhesive/spacer material instead of spaced-apart adhesive/spacer islands;
  • FIG. 16 is a simplified plan view of a center bonded die with adhesive/spacer material applied thereto;
  • FIG. 17 is a side view of a multiple-die assembly made according an aspect of to the invention having a third die mounted upon the second die in a assembly as in FIG. 6, following deposition of adhesive/spacer material as illustrated in FIG. 5 onto the second die, and placement of the third die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the third die on and securing the third die to the second die; and
  • FIGs. 18 through 21 illustrate embodiments of assemblies according to various aspects of the invention in which a package and a die are stacked.
  • FIG. 1 illustrates a conventional multiple die assembly 10 comprising a substrate 12 to which a first, lower die 14 is adhered using an adhesive 16.
  • a second, upper die 18 is mounted to first die 14 by a spacer die 20, the spacer die being adhered to first and second die 14, 18 by adhesive layers 22, 24.
  • Wires 26 connect bond pads 28, 30 of first and second die 14, 18 with bond pads 32 on substrate 12.
  • FIG. 2 shows a conventional multiple die assembly 34 similar to that of FIG. 1 but using a spacer/adhesive material 36 instead of spacer die 20 and adhesive layers 22, 24. Spacer/adhesive material 36 completely fills the die-bonding region 38 defined between first and second die 14, 18.
  • FIGs. 3 - 6 illustrate one procedure according to the invention for applying adhesive/spacer material 36 to a first die 14.
  • a shower head-type dispenser 40 is used to apply material 36 at four spaced apart positions on first die 14. It is typically preferred to use a dot pattern type of shower head-type dispenser 40 instead of a conventional dispenser capillary because the one-step injection process can reduce dispensing time. Also, the amount and position for each deposit 42 can also be more easily controlled.
  • Each deposit 42 of material 36 comprises adhesive 44 and at least one spacer element 46.
  • Material 36 may be a conventional material such as Loctite® QMI536-3, 4, or 6, which uses nominal 3, 4 or 6 mil (75, 100 and 150 micrometers) diameter organic polymer spherical particles as spacer elements 46, or a spacer adhesive from the Ablestik 2025 Sx series. It is preferred that spacer elements 46 be an organic polymer material and pliable and large enough to accommodate the wires 26 extending from bond pads 28 on, in this embodiment, first die 14. Spacer elements 46 are typically about 30 - 250 micrometers in diameter. Material 36 also helps to provide bond line thickness control and die tilt control. Examples of suitable materials for spacer elements 46 include PTFE and other polymers.
  • Spacer elements 46 prior to use, are typically spherical, ellipsoidal, cylindrical with hemispherical or ellipsoidal ends, or the like. After assembly, assuming spacer elements 46 are compressible, spacer elements 46 are compressed to some degree and have flattened areas where they contact lower and upper die 14, 18; the shape of such spacers is collectively referred to as generally ellipsoidal. For example, an initially spherical spacer element 46 having an 8 mil (200 micrometer) diameter will typically compress to a height of about 7.5 mil (188 micrometers).
  • the height of spacers 46 which is equal to chosen separation 53, is usually at least equal to the wire loop height, is more usually greater than the wire loop height, and can be at least about 10% greater than the wire loop height, of wires 26 extending from bond pads 28 of first, lower die 14.
  • the selection of the spacer elements includes selecting spacer elements so that chosen separation 53 is equal to at least a design wire loop height plus an allowance for manufacturing tolerance build-up resulting from making the wire bonds, the variance in the size and compressibility the of spacer elements 46 and other appropriate variables.
  • FIG. 8 illustrates an alternative embodiment in which dispenser 40 previously dispensed five spaced apart deposits 42 of material 36 onto first die 14.
  • second, upper die 18, preferably having a dielectric layer 48 at its second, lower surface 50 is secured to first, lower die 14 by deposits 42 of material 36 to create a multiple-die assembly 51 with upper and lower die 14, 18 separated by a chosen separation 53. See FIG. 6. This causes deposits 42 to spread out somewhat, see FIGs. 7 and 8, creating adhesive/spacer islands 52 spaced apart from one another. In the embodiment of FIGs. 3 - 8, each deposit 42 of material 36 creates a separate adhesive/spacer island 52; that is, none of the deposits 42 merge.
  • the dielectric layer 48 serves to prevent electrical shorting in the event of contact between the die 18 and the wire loops between it and the die 14 upon which it is mounted. This provides a significant advantage in manufacturing, according to the invention. Where no dielectric layer is provided on the underside of the upper die in a stack, the finished separation between the lower surface of the upper die and the upper surface of the lower die must necessarily be at least as great as the design wire loop height above the upper surface of the lower die.
  • the specified separation must be made considerably greater than the design wire loop height; particularly, for example, some allowance must be made for variation in the actual heights of the loops, variation in the size of the spacer elements (particularly, variation in the height dimension of the compressed spacer elements). These allowances can result in significant addition to the separation in the finished stack and, therefore, these allowances can result significant increase in the overall thickness of the finished package. The effect is greater where a multiple die package includes more than two separated (spaced apart) stacked die.
  • the allowance may be considerably reduced.
  • the wire loops may not be particularly desirable for the wire loops to contact the underside of the upper die (that is, to contact dielectric layer), it is not fatal to the package if contact sometimes results during manufacture and, accordingly, it is not necessary to add significantly to the separation specification or to the resulting package height.
  • the multiple spacer island embodiments of FIGs. 6 - 11 may be designed so that each of the adhesive/spacer islands 52 is the same size, such as in FIGs. 6 and 7, or of different sizes, such as adhesive/spacer islands 52A in FIGs. 9 - 11.
  • Adhesive/spacer islands 52, 52A occupy only a percentage of die bonding region 38, preferably at most about 50% and more preferably about 20 - 50 percent of die bonding region 38.
  • an encapsulating material 54 is used to create a multiple-die semiconductor chip package 56 as shown in FIG. 12. The encapsulating process typically occurs under a vacuum so that encapsulating material 54 also effectively fills the open regions between islands 52, 52A so that encapsulating material 54, wires 26 and islands 52 occupied about 100% of die bonding region 38 therefore effectively eliminating voids within the die bonding region.
  • Encapsulating material 54 may be a conventional material comprising a filled epoxy; filled epoxy materials typically comprise about 80 - 90 percent small, hard filler material, typically 5 - 10 micrometer glass or ceramic particles. Therefore, conventional encapsulating material 54 may not be suitable for use as adhesive 58 because the small, hard filler material could be captured between spacer element 46 and either or both of die 14, 18, resulting in damage to the die. Boundaries 58 are created between adhesive/spacer islands 52 and encapsulating material (molding compound) 54.
  • the materials of the spacer/adhesive island structure can be selected to optimize package stability as follows. Molding compounds (encapsulation materials) typically have very different properties from conventional (polymer) adhesives. Molding compounds (or encapsulating materials) are typically highly-filled epoxies; that is, they are composed of an epoxy filled with a high proportion of a fine (submicron size) particulate filler (as much as 80% - 90%, for example) such as silicon or glass. Conventional polymer adhesives, in contrast, are not filled, or are filled to a much lesser extent. Molding compound epoxies are typically selected as having strong adhesion to both silicon (die) and to various substrates.
  • preferred materials for adhesive component 44 of spacer islands 52 are epoxies having qualities similar to those of a molding compound.
  • the adhesive component 44 may be selected so that various of the physical characteristics (for example, thermal expansion coefficient) of the cured adhesive component 44 of the spacer islands 52 match those of the molding compound 54.
  • preferred materials for the adhesive component 44 of the spacer islands 52 are, like at least some molding compounds, less likely to absorb moisture. Selection of the adhesive component of the spacer islands according to these criteria can improve the mechanical stability of the completed package, reducing the incidence, for example, of delamination of the various components in the completed package or warpage of the completed package.
  • the height of spacers 46 is selected to provide a chosen separation 53, large enough to accommodate the wires 26 extending from bond pads 28 on, in this embodiment, first die 14.
  • Spacer elements 46 can accordingly typically be about 30 - 250 micrometers in diameter.
  • the separation 53 must nevertheless be selected to be great enough to allow for flow of the molding compound between the stacked devices during the encapsulation process.
  • the minimum separation which can be readily determined without undue experimentation, depends upon, among other factors, the characteristics of the molding compound itself (for example its rheology), and the extent of the opposed surfaces between which the molding compound must flow.
  • a separation of about 150 urn between the opposed device surfaces may be expected to suffice; if the length of travel is about 3 - 4 mm, the gap typically can be as small as about 50 urn.
  • pressure, time, temperature for molding compound flow-in are known in the art, and various algorithms are routinely employed to determine what separation may be required, or conversely, what conditions may be used to achieve void-free encapsulation using a selected molding compound and a given separation between components.
  • Computer programs can be employed without undue experimentation to model optimal sizes, numbers, and arrangements of adhesive/spacer islands according to the invention.
  • the plurality of spaced-apart adhesive/spacer islands 52, 52A may be replaced by a continuous expanses 60 of adhesive/spacer material 36 such as illustrated in FIGs. 13 - 15.
  • Continuous expanse 60 of material 36 may be deposited so that it preferably occupies at most about 50% of die bonding region 38, and more preferably about 20 - 50% of die bonding region 38.
  • the present invention finds particular utility for use with a center bonded die 64, see FIG. 16, such as a DRAM, having peripheral edges 68 - 71 and having bond pads 28 at a central region 66 of die 64. Wires 26 extending from bond pads 28 extend past peripheral edges 68, 70.
  • the distance between the bond pads and the corresponding peripheral edges for a center bonded die is preferably much more than 100 micrometers. More preferably, the distance between a bond pad 28 for a center bonded die 64 and the nearest peripheral edge is at least about 40% of the corresponding length or width of the die. For example, the distance between a bond pad 28A and peripheral edge 68 is at least about 40% of the length of peripheral edge 69. Assuming peripheral edge 69 is 8 mm long, the distance between bond pad 68A and peripheral edge 68 is at least about 3.2 mm.
  • the multiple die packages illustrated by way of example in FIG. 12 have two die in the stack, a first die and a second die.
  • Multiple die packages according to the invention may have three or more die in the stack.
  • a multiple die stack having three stacked die can be made by providing a multiple-die assembly as in FIG. 6, and mounting an additional die upon the second die by depositing adhesive/spacer material onto the second die generally as shown in FIG. 5 and placing the third die onto the deposits to make a three-die assembly as shown generally at 172 in FIG. 17.
  • a two die assembly as in FIG. 6 has a die 18 stacked over a die 14, which is mounted onto a substrate 12 using an adhesive (in this instance, adhesive spots are used to attach the die 14 to the substrate 12).
  • the die 18 is separated from the die 14 by adhesive/spacer islands 52, each including adhesive 44 and at least one spacer element 46.
  • a dielectric layer 48 applied onto the lower surface 50 of the die 18 serves to prevent electrical shorting between the die 18 and wire bonds interconnecting the die 14 and the substrate 12, and thereby allows for reduction of tolerances for the spacer dimension, as described above. Interconnection of the die 18 with the substrate 12 is made by wire bonds 26 connected to bond pads 30 on die 18.
  • deposits of adhesive/spacer material including adhesive 74 and at least one spacer element 76, are applied on the surface of die 18, generally as described above with reference to FIGs.
  • die 78 having a dielectric layer 88 applied onto the lower surface 170, is placed upon the adhesive/spacer material deposits.
  • the resulting adhesive/spacer islands 72 provide a sufficient between the die 78 and the die 18 equal to a design wire loop height for wire bonds 26 plus an allowance for manufacturing tolerance.
  • Electrical interconnect between the die 78 and the substrate is then made, using a wire bonding tool to connect to bond pads 80.
  • further additional die can be added to the stack.
  • an encapsulating process is employed to complete the package and, where the package is made in an array of packages on a ultipackage substrate, the packages are separated from one another by saw- or punch-singulation.
  • the adhesive/spacer structures are shown in FIGs. 6 and 17 as constituting islands having regular size and shape; according to the invention the islands may have any of various shapes and sizes, as described above with reference, for example, to FIGs. 9 - 11 and 13 - 16.
  • At least two die in the stack are separated by an adhesive/spacer structure; or, at least the lower die in the stack is separated from the substrate by an adhesive/spacer structure. All the die may be separated by spacers, at least two of them being separated by a adhesive/spacer structure; or, in some instances where one or more die is narrower than the die upon which it is stacked, no spacer may be required between those two die.
  • a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies.
  • FIGs. 18 and 19 illustrate examples 102, 103 of such assemblies, in which an inverted package is stacked over a die.
  • a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120.
  • An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements arranged as discrete islands as described above with reference to adhesive/spacer structures 58.
  • An upper package 100 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 18 is mounted upon adhesive/spacer structure 52 in the stacked die assembly 51, for example, of FIG. 6.
  • the upper package 100 in this example is a land grid array package, having a die 242 mounted onto a die attach side on upper package substrate 212. Die 242 in this example is wire bonded to substrate 212, and the die and wire bonds are enclosed in an encapsulation 217.
  • the package 100 is inverted so that the land side of the substrate 212 faces away from the first die 142 and substrate 212, and so that an upper surface of the encapsulation 217 faces toward the first die 142 and substrate 212.
  • the land side of the inverted upper package 212 is upward-facing, and the upper package is electrically interconnected with the bottom substrate 212 by wire bonds between bond pads on the land side of the upper package substrate 212 and bond pads on the upward-facing side of the lower substrate 112.
  • the assembly is then encapsulated (not shown in FIG. 18) to form a package, substantially as the stacked die assembly 51 of FIG. 6 is encapsulated to form the package 56 of FIG. 12.
  • Solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard.
  • Multiple chip modules having inverted package stacked over a die, in which the adhesive/spacer structures described herein may be particularly suitable, are described in U.S. Patent Application No. 11/014,257.
  • two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 19.
  • a die 142 is mounted onto a lower substrate 112, and a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies.
  • Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220.
  • An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 18.
  • either or both of the spacers, between the die, and between the die and the inverted package may be an island adhesive/spacer structure as described above with reference to stacked die assemblies.
  • any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention.
  • Stacked multi-package modules having inverted upper packages are described in U.S. Patent Application No. 10/681 ,572; and examples of suitable upper inverted package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 18 and 19, bump chip carrier packages; and the upper package may include more than one die.
  • the upper package encapsulant has a generally planar surface that contacts the adhesive/spacer structure, that surface (termed the "second" surface) is itself electrically nonconductive and application of an additional insulating layer (as layer 48 in FIG. 6) may be optional in such embodiments.
  • the second surface of the upper package is an electrically conductive material (such as a metal heat spreader, for example) or includes exposed electrically conductive areas or elements, an insulating layer 48 should be applied, as described above with reference for example to FIG. 6.
  • a stacked semiconductor assembly in which a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies, the upper package is not inverted.
  • FIGs. 20 and 21 illustrate examples 104, 105 of such assemblies.
  • a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120.
  • An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements as described above with reference to adhesive/spacer structure 52.
  • An upper package 400 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 18 is mounted upon adhesive/spacer structure 52 in the stacked die assembly 51, for example, of FIG. 6.
  • the upper package 400 in this example is a land grid array package, having a die 442 mounted onto a die attach side on upper package substrate 412. Die 442 in this example is wire bonded to substrate 412, and the die and wire bonds are enclosed in a mold cap 417.
  • the package 400 is oriented so that the land side of the substrate 412 faces toward the first die 142 and substrate 212, and so that the land side of the upper package substrate 412 faces toward the first die 142 and substrate 212. In the orientation of FIG.
  • the land side of the inverted upper package 412 is downward-facing, and the upper package is electrically interconnected with the bottom substrate 112 by wire bonds between bond pads on the upward-facing (die attach) side of the upper package substrate 412 and bond pads on the upward-facing side of the lower substrate 112.
  • the assembly is then encapsulated (not shown in FIG. 20) to form a package, substantially as the stacked die assembly 51 of FIG. 6 is encapsulated to form the package 56 of FIG. 12.
  • Solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard.
  • two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 21.
  • a die 142 is mounted onto a lower substrate 112
  • a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies.
  • Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220.
  • An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 19.
  • the spacers, between the die, and between the die and the inverted package may be an adhesive/spacer structre as described above with referenbce to stacked die assemblies.
  • Any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention. Stacked multi-package modules suitable upper packages are described in U.S. Patent Applications Nos.
  • 10/632,549; 10/632,568; 10/632,551 ; 10/632,552; 10/632,553; and 10/632,550; and examples of suitable upper package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 20 and 21 , bump chip carrier packages, and flip chip packages; and the upper package may include more than one die. Where the downward-facing surface of the upper package ("second" surface) had electrically conductive elements or areas, application of an additional insulating layer (as layer 48 in FIG. 6) may be required and may be applied as described above with reference for example to FIG. 6, and as shown for example at 450 in FIGs. 20 and 21.
  • an additional insulating layer as layer 48 in FIG. 6
  • both the element 18 and the element 14 may be a package, comprising a die mounted onto and electrically connected with a substrate.
  • Other devices may be stacked over the first die, and separated therefrom by an adhesive/spacer structure as described above, and provided with an insulating layer as appropriate.
  • a metal heat spreader may be stacked upon an adhesive/spacer structure over the first die in place of the upper die or upper package in the descriptions above.
  • the assemblies and packages according to the invention can be useful in any of a variety of products, such as for example computers, mobile telecommunications devices, personal digital assistance devices, media storage devices, particularly portable cameras and audio and video equipment.

Abstract

Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an 'upper' package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate. Also, methods are disclosed for making assemblies including the adhesive/spacer island structures.

Description

ADHESIVE/SPACER ISLAND STRUCTURE FOR MULTIPLE DIE PACKAGE CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation-ln-Part of U.S. Application No. 10/969,116, filed October 20, 2004, titled "Adhesive/spacer island structure for multiple die package". The said U.S. Application No. 10/969,116 claims priority from U.S. Provisional Application
No. 60/573,903, filed May 24, 2004, titled "Adhesive spacer island structure for multiple die package"; and also claims priority from related U.S. Provisional Application No. 60/573,956, filed May 24, 2004, titled "Multiple die package with adhesive/spacer structure and insulated die surface". This application is related to U.S. Application No. 11/ , , Attorney Docket CPAC 1071-3, filed on the same day as this application. BACKGROUND
[0002] To obtain the maximum function and efficiency from a package having minimum dimensions, various types of increased density packages have been developed. Among these various types of packages is the multiple-die semiconductor chip package, commonly referred to as a multi-chip module, multi-chip package or stacked chip package. A multi-chip package includes one or more integrated circuit semiconductor chips, often referred to as circuit die, stacked one onto another to provide the advantages of light weight, high density, and enhanced electrical performance. To stack the semiconductor chips, each chip can be lifted by a chip-bonding tool, which is usually mounted at the end of a pick-and-place device, and mounted onto the substrate or onto a semiconductor chip mounted previously.
[0003] In some circumstances, such as when the upper die is smaller than the lower die, the upper die can be attached directly to the lower die without the use of spacers. However, when spacers are needed between the upper and lower die, spacer die, that is die without circuitry, can be used between the upper and lower die. In addition, adhesives containing spacer elements, typically micro spheres, are often used to properly separate the upper and lower die. See U.S. patent numbers 5,323,060; 6,333,562; 6,340,846; 6,388,313; 6,472,758; 6,569,709; 6,593,662; 6,441,496; and U.S. patent publication number US 2003/0178710. [0004] After the chip mounting process, bonding pads of the chips are connected to bonding pads of the substrate with Au or Al wires during a wire bonding process to create an array of semiconductor chip devices. Finally, the semiconductor chips and their associated wires connected to the substrate are encapsulated, typically using an epoxy-molding compound, to create an array of encapsulated semiconductor devices. The molding compound protects the semiconductor devices from the external environment, such as physical shock and humidity. After encapsulation, the encapsulated devices are separated, typically by sawing, into individual semiconductor chip packages. SUMMARY
[0005] In general, the invention features adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly. The adhesive/spacer structure according to the invention includes a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an "upper" package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate. [0006] In one general aspect the invention features an adhesive/spacer structure used to adhere first and second devices to one another at a chosen separation in a multiple-device semiconductor chip package. The adhesive/spacer structure comprises a plurality of spaced- apart adhesive/spacer islands securing the first and second devices to one another at a chosen separation. In some embodiments both the first and the second devices are die; in some embodiments the first device is a die, and the second device is a package or a heat spreader. In some embodiments both the first and the second devices are packages. The adhesive/spacer structure can in some embodiments serve to provide a separation between the device that accommodates wire bonds connected to pads on a surface of one of the two devices. In other embodiments the adhesive/spacer structure serves to raise an upper device over a lower substrate to provide space for an additional component such as another die, adjacent a lower die.
[0007] Where the first device is a die, the first die is mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate. A second surface of a second device (which may be a die, or a package, or a heat spreader, for example) is positioned opposite the first surface to define a die bonding region therebetween. A plurality of spaced-apart adhesive/spacer islands are within the die bonding region and secure the first die and the second device to one another at a chosen separation to create a multiple-die assembly. The adhesive/spacer islands comprise spacer elements within an adhesive. A material encapsulates the multiple-device assembly to create a multiple-device semiconductor chip package.
[0008] In another aspect the invention features an adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. The adhesive/spacer structure comprises a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation. The adhesive/spacer structure in such embodiments serves to provide a separation between the device that accommodates wire bonds connected to pads on a surface of one of the two die. In other embodiments the adhesive/spacer structure serves to raise an upper die over a lower substrate to provide space for an additional component such as another die, adjacent a lower die.
[0009] In another aspect the invention features a multiple-die semiconductor chip package having the adhesive/spacer island structure securing first and second die to one another at a chosen separation. A first die is mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate. A second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween. A plurality of spaced-apart adhesive/spacer islands are within the die bonding region and secure the first and second die to one another at a chosen separation to create a multiple-die assembly. The adhesive/spacer islands comprise spacer elements within an adhesive. A material encapsulates the multiple-die assembly to create a multiple-die semiconductor chip package. [0010] In another aspect the invention features an adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple- die semiconductor chip assembly. The first and second die define a die bonding region therebetween. The adhesive/spacer structure comprises spacer elements within an adhesive. The adhesive/spacer structure secures the first and second die to one another and occupies at most about 50% of the die bonding region. [0011] In another aspect the invention features a multiple-die semiconductor chip package. A first die is mounted to a substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface. Wires are bonded to and extend from the bond pads outwardly past the periphery to the substrate. A second surface of a second die is positioned opposite the first surface to define a die bonding region therebetween. An adhesive/spacer structure within the die bonding region secures the first and second surfaces to one another at a chosen separation to create a multiple-die assembly. The adhesive/spacer structure comprises spacer elements within an adhesive. The adhesive/spacer structure occupies at most about 50% of the die bonding region. A material encapsulates the multiple- die assembly to create a multiple-die semiconductor chip package. [0012] In another aspect the invention features a method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package assembly. An adhesive/spacer material having spacer elements within an adhesive is selected. The adhesive/spacer material is deposited onto a first surface of a first die at a plurality of spaced- apart positions. A second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby securing the first and second die to one another at a chosen separation. The selecting and depositing steps are carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.
[0013] In another aspect the invention features a method for creating a multiple-die semiconductor chip package. A first die is mounted to a substrate, the first die having a first surface with bond pads at the first surface. The bond pads are connected to the substrate with wires. An adhesive/spacer material, comprising spacer elements within an adhesive, is selected. The adhesive/spacer material is deposited onto the first surface of the first die at a plurality of spaced-apart positions. A second surface of a second die is located opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die assembly. The selecting and depositing steps are carried out to create a plurality of spaced- apart adhesive/spacer islands following the securing step. The multiple-die assembly is encapsulated to create a multiple-die semiconductor chip package. [0014] In another aspect the invention features a method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package assembly. An adhesive/spacer material, having spacer elements within an adhesive, is selected. An amount of the adhesive/spacer material is chosen. The chosen amount the adhesive/spacer material is deposited onto a first surface of a first die. A second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation. The choosing and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step. [0015] In another aspect the invention features a method for creating a multiple-die semiconductor chip package. A first die, comprising a first surface with bond pads at the first surface, is mounted to a substrate. The bond pads and the substrate are connected with wires. An adhesive/spacer material having spacer elements within an adhesive is selected. The adhesive/spacer material is deposited onto a first surface of the first die at a plurality of spaced-apart positions. A second surface of a second die is located opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces, and securing the first and second die to one another at a chosen separation to create a multiple-die assembly. The selecting and depositing steps are carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region. The multiple-die assembly is encapsulated to create a multiple-die semiconductor chip package, with the encapsulating material occupying a second percentage of the die bonding region.
[0016] In another aspect the invention features adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly. The adhesive/spacer structure according to the invention includes a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. In some embodiments the first devices is a die; in other embodiments the first deice is a package; in still other embodiments the second device is be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an "upper" package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate. [0017] The present invention provides several potential advantages over conventional die stacking structures, specifically silicon spacer die and conventional spacer adhesives. The number of processing steps is reduced compared to conventional packages using silicon spacer wafers. According to the present invention, material processing can be simplified, the amount of spacer material used can be reduced and package reliability and productivity can be potentially increased. [0018] Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIGs. 1 and 2 are side views of conventional multiple die assemblies using a spacer die and an adhesive/spacer material to separate the upper and lower die, respectively; [0020] FIGs. 3 - 5 illustrate deposition of adhesive/spacer material onto a lower die using a shower head-type of dispenser according to an aspect of the invention; [0021] FIG. 6 is a side view of a multiple-die assembly made according to an aspect of the invention following the deposition step of FIG. 5 and placement of an upper die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the upper die on and securing the upper die to the lower die; [0022] FIG. 7 is a top view of the assembly of FIG. 6 with the top die removed to illustrate the adhesive/spacer islands;
[0023] FIG. 8 illustrates an alternative embodiment of the structure shown in FIG. 7;
[0024] FIGs. 9 - 11 illustrate alternative embodiments of the lower die of FIG. 7 with adhesive/spacer islands having various sizes and shapes;
[0025] FIG. 12 illustrates a multiple-die semiconductor chip package made according to the invention by encapsulating the multiple-die assembly of FIG. 6 with an encapsulating material;
[0026] FIGs. 13 - 15 illustrate continuous expanses of adhesive/spacer material instead of spaced-apart adhesive/spacer islands; [0027] FIG. 16 is a simplified plan view of a center bonded die with adhesive/spacer material applied thereto;
[0028] FIG. 17 is a side view of a multiple-die assembly made according an aspect of to the invention having a third die mounted upon the second die in a assembly as in FIG. 6, following deposition of adhesive/spacer material as illustrated in FIG. 5 onto the second die, and placement of the third die onto the deposits of adhesive/spacer material creating adhesive/spacer islands supporting the third die on and securing the third die to the second die; and
[0029] FIGs. 18 through 21 illustrate embodiments of assemblies according to various aspects of the invention in which a package and a die are stacked. DETAILED DESCRIPTION
[0030] The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs. Terms of orientation, such as "upper" and "lower" and the like are employed for reference to the relative orientation of the various features as shown in the FIGs., it being understood that any of the various assemblies can be deployed in any orientation in use. [0031] Several prior art structures and embodiments made according to the invention are discussed below. Like reference numerals refer to like elements.
[0032] FIG. 1 illustrates a conventional multiple die assembly 10 comprising a substrate 12 to which a first, lower die 14 is adhered using an adhesive 16. A second, upper die 18 is mounted to first die 14 by a spacer die 20, the spacer die being adhered to first and second die 14, 18 by adhesive layers 22, 24. Wires 26 connect bond pads 28, 30 of first and second die 14, 18 with bond pads 32 on substrate 12. FIG. 2 shows a conventional multiple die assembly 34 similar to that of FIG. 1 but using a spacer/adhesive material 36 instead of spacer die 20 and adhesive layers 22, 24. Spacer/adhesive material 36 completely fills the die-bonding region 38 defined between first and second die 14, 18.
[0033] The invention will now be described with reference to a stacked die assembly, in which a spacer/adhesive island structure provides a separation between adjacent stacked die. [0034] FIGs. 3 - 6 illustrate one procedure according to the invention for applying adhesive/spacer material 36 to a first die 14. In this embodiment a shower head-type dispenser 40 is used to apply material 36 at four spaced apart positions on first die 14. It is typically preferred to use a dot pattern type of shower head-type dispenser 40 instead of a conventional dispenser capillary because the one-step injection process can reduce dispensing time. Also, the amount and position for each deposit 42 can also be more easily controlled.
[0035] Each deposit 42 of material 36, see also FIGs. 5 - 7, comprises adhesive 44 and at least one spacer element 46. Material 36 may be a conventional material such as Loctite® QMI536-3, 4, or 6, which uses nominal 3, 4 or 6 mil (75, 100 and 150 micrometers) diameter organic polymer spherical particles as spacer elements 46, or a spacer adhesive from the Ablestik 2025 Sx series. It is preferred that spacer elements 46 be an organic polymer material and pliable and large enough to accommodate the wires 26 extending from bond pads 28 on, in this embodiment, first die 14. Spacer elements 46 are typically about 30 - 250 micrometers in diameter. Material 36 also helps to provide bond line thickness control and die tilt control. Examples of suitable materials for spacer elements 46 include PTFE and other polymers.
[0036] Spacer elements 46, prior to use, are typically spherical, ellipsoidal, cylindrical with hemispherical or ellipsoidal ends, or the like. After assembly, assuming spacer elements 46 are compressible, spacer elements 46 are compressed to some degree and have flattened areas where they contact lower and upper die 14, 18; the shape of such spacers is collectively referred to as generally ellipsoidal. For example, an initially spherical spacer element 46 having an 8 mil (200 micrometer) diameter will typically compress to a height of about 7.5 mil (188 micrometers). The height of spacers 46, which is equal to chosen separation 53, is usually at least equal to the wire loop height, is more usually greater than the wire loop height, and can be at least about 10% greater than the wire loop height, of wires 26 extending from bond pads 28 of first, lower die 14. If desired, the selection of the spacer elements includes selecting spacer elements so that chosen separation 53 is equal to at least a design wire loop height plus an allowance for manufacturing tolerance build-up resulting from making the wire bonds, the variance in the size and compressibility the of spacer elements 46 and other appropriate variables. [0037] FIG. 8 illustrates an alternative embodiment in which dispenser 40 previously dispensed five spaced apart deposits 42 of material 36 onto first die 14. The number, size and position of deposits 42 will depend upon various factors including the size of the die and the package description. [0038] Following the deposition of deposits 42, second, upper die 18, preferably having a dielectric layer 48 at its second, lower surface 50, is secured to first, lower die 14 by deposits 42 of material 36 to create a multiple-die assembly 51 with upper and lower die 14, 18 separated by a chosen separation 53. See FIG. 6. This causes deposits 42 to spread out somewhat, see FIGs. 7 and 8, creating adhesive/spacer islands 52 spaced apart from one another. In the embodiment of FIGs. 3 - 8, each deposit 42 of material 36 creates a separate adhesive/spacer island 52; that is, none of the deposits 42 merge. In some situations certain of the deposits 42 of material 36 may merge while still creating a plurality of adhesive/spacer islands 52. See, for example, the adhesive/spacer islands 52A of FIGs. 9 and 10. [0039] The dielectric layer 48 serves to prevent electrical shorting in the event of contact between the die 18 and the wire loops between it and the die 14 upon which it is mounted. This provides a significant advantage in manufacturing, according to the invention. Where no dielectric layer is provided on the underside of the upper die in a stack, the finished separation between the lower surface of the upper die and the upper surface of the lower die must necessarily be at least as great as the design wire loop height above the upper surface of the lower die. Because of variations in manufacture the specified separation must be made considerably greater than the design wire loop height; particularly, for example, some allowance must be made for variation in the actual heights of the loops, variation in the size of the spacer elements (particularly, variation in the height dimension of the compressed spacer elements). These allowances can result in significant addition to the separation in the finished stack and, therefore, these allowances can result significant increase in the overall thickness of the finished package. The effect is greater where a multiple die package includes more than two separated (spaced apart) stacked die.
[0040] In contrast, where the underside of the upper die in a stacked pair of die according to the invention is provided with a dielectric layer, the allowance may be considerably reduced. Although it may not be particularly desirable for the wire loops to contact the underside of the upper die (that is, to contact dielectric layer), it is not fatal to the package if contact sometimes results during manufacture and, accordingly, it is not necessary to add significantly to the separation specification or to the resulting package height. [0041] The multiple spacer island embodiments of FIGs. 6 - 11 may be designed so that each of the adhesive/spacer islands 52 is the same size, such as in FIGs. 6 and 7, or of different sizes, such as adhesive/spacer islands 52A in FIGs. 9 - 11. Adhesive/spacer islands 52, 52A occupy only a percentage of die bonding region 38, preferably at most about 50% and more preferably about 20 - 50 percent of die bonding region 38. [0042] Thereafter, an encapsulating material 54 is used to create a multiple-die semiconductor chip package 56 as shown in FIG. 12. The encapsulating process typically occurs under a vacuum so that encapsulating material 54 also effectively fills the open regions between islands 52, 52A so that encapsulating material 54, wires 26 and islands 52 occupied about 100% of die bonding region 38 therefore effectively eliminating voids within the die bonding region. [0043] Encapsulating material 54 may be a conventional material comprising a filled epoxy; filled epoxy materials typically comprise about 80 - 90 percent small, hard filler material, typically 5 - 10 micrometer glass or ceramic particles. Therefore, conventional encapsulating material 54 may not be suitable for use as adhesive 58 because the small, hard filler material could be captured between spacer element 46 and either or both of die 14, 18, resulting in damage to the die. Boundaries 58 are created between adhesive/spacer islands 52 and encapsulating material (molding compound) 54.
[0044] The materials of the spacer/adhesive island structure can be selected to optimize package stability as follows. Molding compounds (encapsulation materials) typically have very different properties from conventional (polymer) adhesives. Molding compounds (or encapsulating materials) are typically highly-filled epoxies; that is, they are composed of an epoxy filled with a high proportion of a fine (submicron size) particulate filler (as much as 80% - 90%, for example) such as silicon or glass. Conventional polymer adhesives, in contrast, are not filled, or are filled to a much lesser extent. Molding compound epoxies are typically selected as having strong adhesion to both silicon (die) and to various substrates. According to the invention, preferred materials for adhesive component 44 of spacer islands 52 are epoxies having qualities similar to those of a molding compound. The adhesive component 44 may be selected so that various of the physical characteristics (for example, thermal expansion coefficient) of the cured adhesive component 44 of the spacer islands 52 match those of the molding compound 54. Also, preferred materials for the adhesive component 44 of the spacer islands 52 are, like at least some molding compounds, less likely to absorb moisture. Selection of the adhesive component of the spacer islands according to these criteria can improve the mechanical stability of the completed package, reducing the incidence, for example, of delamination of the various components in the completed package or warpage of the completed package. [0045] As noted above, in these embodiments the height of spacers 46 is selected to provide a chosen separation 53, large enough to accommodate the wires 26 extending from bond pads 28 on, in this embodiment, first die 14. Spacer elements 46 can accordingly typically be about 30 - 250 micrometers in diameter. However, in the event where the wire loop height may be substantially reduced (as, for example, where reverse wire bonding is employed), the separation 53 must nevertheless be selected to be great enough to allow for flow of the molding compound between the stacked devices during the encapsulation process. The minimum separation, which can be readily determined without undue experimentation, depends upon, among other factors, the characteristics of the molding compound itself (for example its rheology), and the extent of the opposed surfaces between which the molding compound must flow. For a typical molding compound, for example, if the molding compound must travel over a distance of about 10 mm between the stacked devices, a separation of about 150 urn between the opposed device surfaces may be expected to suffice; if the length of travel is about 3 - 4 mm, the gap typically can be as small as about 50 urn. These parameters, and other pertinent ones (pressure, time, temperature for molding compound flow-in), are known in the art, and various algorithms are routinely employed to determine what separation may be required, or conversely, what conditions may be used to achieve void-free encapsulation using a selected molding compound and a given separation between components. Computer programs can be employed without undue experimentation to model optimal sizes, numbers, and arrangements of adhesive/spacer islands according to the invention.
[0046] In some situations the plurality of spaced-apart adhesive/spacer islands 52, 52A may be replaced by a continuous expanses 60 of adhesive/spacer material 36 such as illustrated in FIGs. 13 - 15. Continuous expanse 60 of material 36 may be deposited so that it preferably occupies at most about 50% of die bonding region 38, and more preferably about 20 - 50% of die bonding region 38.
[0047] The present invention finds particular utility for use with a center bonded die 64, see FIG. 16, such as a DRAM, having peripheral edges 68 - 71 and having bond pads 28 at a central region 66 of die 64. Wires 26 extending from bond pads 28 extend past peripheral edges 68, 70. The distance between the bond pads and the corresponding peripheral edges for a center bonded die is preferably much more than 100 micrometers. More preferably, the distance between a bond pad 28 for a center bonded die 64 and the nearest peripheral edge is at least about 40% of the corresponding length or width of the die. For example, the distance between a bond pad 28A and peripheral edge 68 is at least about 40% of the length of peripheral edge 69. Assuming peripheral edge 69 is 8 mm long, the distance between bond pad 68A and peripheral edge 68 is at least about 3.2 mm.
[0048] The multiple die packages illustrated by way of example in FIG. 12 have two die in the stack, a first die and a second die. Multiple die packages according to the invention may have three or more die in the stack. A multiple die stack having three stacked die, for example, can be made by providing a multiple-die assembly as in FIG. 6, and mounting an additional die upon the second die by depositing adhesive/spacer material onto the second die generally as shown in FIG. 5 and placing the third die onto the deposits to make a three-die assembly as shown generally at 172 in FIG. 17. Referring to FIG. 17, a two die assembly as in FIG. 6 has a die 18 stacked over a die 14, which is mounted onto a substrate 12 using an adhesive (in this instance, adhesive spots are used to attach the die 14 to the substrate 12). The die 18 is separated from the die 14 by adhesive/spacer islands 52, each including adhesive 44 and at least one spacer element 46. A dielectric layer 48 applied onto the lower surface 50 of the die 18 serves to prevent electrical shorting between the die 18 and wire bonds interconnecting the die 14 and the substrate 12, and thereby allows for reduction of tolerances for the spacer dimension, as described above. Interconnection of the die 18 with the substrate 12 is made by wire bonds 26 connected to bond pads 30 on die 18. To mount an additional die 78, deposits of adhesive/spacer material, including adhesive 74 and at least one spacer element 76, are applied on the surface of die 18, generally as described above with reference to FIGs. 3 - 5, and then die 78, having a dielectric layer 88 applied onto the lower surface 170, is placed upon the adhesive/spacer material deposits. The resulting adhesive/spacer islands 72 provide a sufficient between the die 78 and the die 18 equal to a design wire loop height for wire bonds 26 plus an allowance for manufacturing tolerance. Electrical interconnect between the die 78 and the substrate is then made, using a wire bonding tool to connect to bond pads 80. According to the invention, further additional die can be added to the stack. When the stack is complete, an encapsulating process is employed to complete the package and, where the package is made in an array of packages on a ultipackage substrate, the packages are separated from one another by saw- or punch-singulation.
[0049] The adhesive/spacer structures are shown in FIGs. 6 and 17 as constituting islands having regular size and shape; according to the invention the islands may have any of various shapes and sizes, as described above with reference, for example, to FIGs. 9 - 11 and 13 - 16.
[0050] In multiple die packages according to the invention, at least two die in the stack are separated by an adhesive/spacer structure; or, at least the lower die in the stack is separated from the substrate by an adhesive/spacer structure. All the die may be separated by spacers, at least two of them being separated by a adhesive/spacer structure; or, in some instances where one or more die is narrower than the die upon which it is stacked, no spacer may be required between those two die.
[0051] According to the invention, and generally with reference to FIGs. 6 and 12, either 14 or 18, or both 14 and 18 could constitute, rather than a die, a package including at least one die attached to and electrically connected to a substrate. [0052] Accordingly, for example, in other embodiments, a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies. FIGs. 18 and 19 illustrate examples 102, 103 of such assemblies, in which an inverted package is stacked over a die. Referring to FIG. 18, a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120. An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements arranged as discrete islands as described above with reference to adhesive/spacer structures 58. An upper package 100 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 18 is mounted upon adhesive/spacer structure 52 in the stacked die assembly 51, for example, of FIG. 6. [0053] The upper package 100 in this example is a land grid array package, having a die 242 mounted onto a die attach side on upper package substrate 212. Die 242 in this example is wire bonded to substrate 212, and the die and wire bonds are enclosed in an encapsulation 217. The package 100 is inverted so that the land side of the substrate 212 faces away from the first die 142 and substrate 212, and so that an upper surface of the encapsulation 217 faces toward the first die 142 and substrate 212. In the orientation of FIG. 18, the land side of the inverted upper package 212 is upward-facing, and the upper package is electrically interconnected with the bottom substrate 212 by wire bonds between bond pads on the land side of the upper package substrate 212 and bond pads on the upward-facing side of the lower substrate 112. The assembly is then encapsulated (not shown in FIG. 18) to form a package, substantially as the stacked die assembly 51 of FIG. 6 is encapsulated to form the package 56 of FIG. 12. Solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard. Multiple chip modules having inverted package stacked over a die, in which the adhesive/spacer structures described herein may be particularly suitable, are described in U.S. Patent Application No. 11/014,257. [0054] In other embodiments, two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 19. Here, a die 142 is mounted onto a lower substrate 112, and a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies. Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220. An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 18. As will be appreciated, either or both of the spacers, between the die, and between the die and the inverted package, may be an island adhesive/spacer structure as described above with reference to stacked die assemblies.
[0055] Any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention. Stacked multi-package modules having inverted upper packages are described in U.S. Patent Application No. 10/681 ,572; and examples of suitable upper inverted package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 18 and 19, bump chip carrier packages; and the upper package may include more than one die. Where the upper package encapsulant has a generally planar surface that contacts the adhesive/spacer structure, that surface (termed the "second" surface) is itself electrically nonconductive and application of an additional insulating layer (as layer 48 in FIG. 6) may be optional in such embodiments. Where, however, the second surface of the upper package is an electrically conductive material (such as a metal heat spreader, for example) or includes exposed electrically conductive areas or elements, an insulating layer 48 should be applied, as described above with reference for example to FIG. 6.
[0056] In still other embodiments, in which a stacked semiconductor assembly includes a package stacked with a die, separated by an adhesive/spacer material generally as described above for stacked die assemblies, the upper package is not inverted. FIGs. 20 and 21 illustrate examples 104, 105 of such assemblies. Referring to FIG. 20, a lower, peripheral bonded die 142 is mounted upon a substrate 112, and bond pads on the die are electrically interconnected with bond pads on the substrate by wire bonds 120. An adhesive/spacer structure 146 is formed upon the die 142 including an adhesive and spacer elements as described above with reference to adhesive/spacer structure 52. An upper package 400 is inverted and mounted upon the adhesive/spacer structure 146, in substantially the same manner as the upper die 18 is mounted upon adhesive/spacer structure 52 in the stacked die assembly 51, for example, of FIG. 6.
[0057] The upper package 400 in this example is a land grid array package, having a die 442 mounted onto a die attach side on upper package substrate 412. Die 442 in this example is wire bonded to substrate 412, and the die and wire bonds are enclosed in a mold cap 417. Here the package 400 is oriented so that the land side of the substrate 412 faces toward the first die 142 and substrate 212, and so that the land side of the upper package substrate 412 faces toward the first die 142 and substrate 212. In the orientation of FIG. 20, the land side of the inverted upper package 412 is downward-facing, and the upper package is electrically interconnected with the bottom substrate 112 by wire bonds between bond pads on the upward-facing (die attach) side of the upper package substrate 412 and bond pads on the upward-facing side of the lower substrate 112. The assembly is then encapsulated (not shown in FIG. 20) to form a package, substantially as the stacked die assembly 51 of FIG. 6 is encapsulated to form the package 56 of FIG. 12. Solder balls 118 are mounted onto pads on the downward-facing side of the substrate 112, for interconnection of the package to, for example, a motherboard. [0058] In other embodiments, two (or more) die may be stacked using an adhesive/spacer structure over one another on a lower substrate, and a package may be stacked over the uppermost one of the stacked die, using an adhesive/spacer structure, as shown by way of example in FIG. 21. Here, as in FIG. 20, a die 142 is mounted onto a lower substrate 112, and a die 144 is stacked over the die 142, and separated from it by an adhesive/spacer structure 246 as described above for stacked die assemblies. Die 142 and 144 are electrically interconnectedd with substrate 112 by wire bonds 220. An inverted pachage 100 is mounted over the stacked die 142, 144, separated by the die 144 by and adhesive/spacer structure 246, as described above with reference to FIG. 19. As will be appreciated, either or both of the spacers, between the die, and between the die and the inverted package, may be an adhesive/spacer structre as described above with referenbce to stacked die assemblies. [0059] Any of a variety of packages may be stacked over the die in assemblies according to these embodiments of the invention. Stacked multi-package modules suitable upper packages are described in U.S. Patent Applications Nos. 10/632,549; 10/632,568; 10/632,551 ; 10/632,552; 10/632,553; and 10/632,550; and examples of suitable upper package types are described therein. These include, for example, besides land grid array packages as illustrated in FIGs. 20 and 21 , bump chip carrier packages, and flip chip packages; and the upper package may include more than one die. Where the downward-facing surface of the upper package ("second" surface) had electrically conductive elements or areas, application of an additional insulating layer (as layer 48 in FIG. 6) may be required and may be applied as described above with reference for example to FIG. 6, and as shown for example at 450 in FIGs. 20 and 21. This additional insulating layer may be applied as a film to the land side of the upper package substrate, and voids between the film and the substrate surface removed by heating at low pressure, according to techniques known in the art. [0060] In other embodiments (with reference again to FIG. 6, both the element 18 and the element 14 may be a package, comprising a die mounted onto and electrically connected with a substrate.
[0061] Other devices may be stacked over the first die, and separated therefrom by an adhesive/spacer structure as described above, and provided with an insulating layer as appropriate. For example, a metal heat spreader may be stacked upon an adhesive/spacer structure over the first die in place of the upper die or upper package in the descriptions above.
[0062] Other modification and variation can be made to the disclosed embodiments without departing from the subject of the invention as defined in the following claims. For example, although the above embodiments disclose the use of adhesive/spacer material 36 between lower and upper die 14, 18, material 36 may also be used with multiple die semiconductor chip packages having, for example, four die with material 36 used between one, two or three of the pairs of adjacent die. Also, although the above described embodiments show the bump reverse bonding method for attaching wires 26 to bond pads 28, 30, the conventional forward wire bonding method can also be used.
[0063] The assemblies and packages according to the invention can be useful in any of a variety of products, such as for example computers, mobile telecommunications devices, personal digital assistance devices, media storage devices, particularly portable cameras and audio and video equipment.
[0064] Any and all patents, patent applications and printed publications referred to above are incorporated by reference.
[0065] Other embodiments are within the scope of the invention.

Claims

CLAIMS What is claimed is:
1. An adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the adhesive/spacer structure comprising: a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation; and said adhesive/spacer islands comprising an adhesive/spacer material, said adhesive/spacer material comprising deformable spacer elements embedded within adhesive.
2. The structure according to claim 1 comprising at least three of said spaced-apart adhesive/spacer islands.
3. The structure according to claim 1 wherein at least one of said adhesive/spacer islands comprises a plurality of said spacer elements.
4. The structure according to claim 1 wherein the spacer elements are all substantially the same size.
5. The structure according to claim 1 wherein the spacer elements comprise generally ellipsoidal spacer elements.
6. The structure according to claim 5 wherein the generally ellipsoidal spacer elements comprise flattened generally spherical spacer elements.
7. The structure according to claim 1 wherein the spacer elements are deformable polymer spacer elements.
8. The structure according to claim 7 wherein the deformable polymer spacer elements comprise PTFE.
9. The structure according to claim 1 wherein each of the adhesive/spacer islands are about the same size.
10. The structure according to claim 1 wherein a first of the adhesive/spacer islands is at least twice the size of a second of the adhesive/spacer islands.
11. A multiple-die semiconductor chip package comprising: a substrate; a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery to the substrate; a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer; a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple- die assembly, the adhesive/spacer islands occupying a first percentage of the die bonding region; the adhesive/spacer islands comprising at least one spacer element within an adhesive; and a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.
12. The package according to claim 11 wherein the first percentage is between about 20 - 50 percent.
13. The package according to claim 11 wherein the first percentage is at most about 50%.
14. The package according to claim 11 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100 percent thereby effectively eliminating voids within the die bonding region.
15. The package according to claim 11 wherein: the adhesive comprises epoxy; and the encapsulating material comprises a filled epoxy.
16. The package according to claim 11 wherein the adhesive and the encapsulating material create an adhesive/encapsulating material boundary within the die bonding region.
17. An adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the multiple-die semiconductor chip package comprising the first and second die defining a die bonding region therebetween, the adhesive/spacer structure comprising: adhesive/spacer structure comprising spacer elements within an adhesive, the spacer elements comprising a deformable material; and the adhesive/spacer structure securing the first and second die to one another and occupying at most about 50% of the die bonding region.
18. The structure according to claim 17 wherein the adhesive/spacer structure comprises first and second adhesive/spacer structures spaced apart from one another.
19. The structure according to claim 17 wherein the adhesive/spacer structure comprises at least three adhesive/spacer structures spaced apart from one another.
20. The structure according to claim 17 wherein the adhesive/spacer structure occupies about 20 - 50% of the die bonding region.
21. A stacked semiconductor assembly comprising: a first semiconductor device having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first die; a package, comprising a package die mounted to and electrically interconnected with a package substrate, the package having an electrically non-conductive second surface positioned opposite the first surface; the first device and the package defining a first region therebetween; an adhesive/spacer structure within the first region, the adhesive/spacer structure contacting the first and second surfaces and adhering the first device and the package to one another at a chosen separation, the adhesive/spacer structure comprising spacer elements within an adhesive.
22. The stacked semiconductor assembly of claim 21 wherein the upper package is oriented so that the die attach side of the upper package substrate faces the first device.
23. The stacked semiconductor assembly of claim 21 wherein the upper package is oriented so that side of the upper package substrate opposite the die attach side faces the first die.
24. Stacked semiconductor packages comprising the assembly of claim 21.
25. A method for adhering a die and a package to one another at a chosen separation in a stacked semiconductor package, the method comprising: Selecting an adhesive/spacer material having spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of a first die, the first die having a first surface bounded by a periphery, bond pads at the first surface, and wires bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first die, the wires comprising a set of generally parallel wires, the set of generally parallel wires defining a wire span portion of the first surface; Selecting a package having an electrically non-conductive second surface; locating the second surface of the package opposite the first surface of the first die and in contact with the adhesive/spacer material there between thereby securing the package and the first die to one another at a chosen separation, the wire span portion of the first surface defining a wire span region between the first and second surfaces; and Preventing any spacer elements from entering the wire span region.
21. A multiple-die semiconductor chip package comprising: a substrate; a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery to the substrate; a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer; adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die assembly; the adhesive/spacer structure comprising spacer elements within an adhesive; the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%; and a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.
22. The package according to claim 21 wherein the first percentage is about 20 - 50%.
23. The package according to claim 21 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.
24. A method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: selecting an adhesive/spacer material having spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of a first die at a plurality of spaced-apart positions; providing a second surface of the second die with a dielectric layer; locating the second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: securing the first and second die to one another at a chosen separation; and the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.
25. The method according to claim 24 wherein the selecting step comprises choosing spacer elements having the same size and shape.
26. The method according to claim 24 wherein the depositing step is carried out to create a plurality of generally equal-size islands of the adhesive/spacer material after the securing step.
27. The method according to claim 24 wherein the depositing step is carried out to create at least three generally equal-size islands of the adhesive/spacer material after the securing step.
28. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die having a first surface with bond pads at the first surface; connecting the bond pads and the substrate with wires; selecting an adhesive/spacer material comprising spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions; providing a second surface of the second die with a dielectric layer; locating a second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation to create a multiple-die assembly; the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step, the adhesive/spacer islands occupying a first percentage of the die bonding region; and encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.
29. The method according to claim 28 wherein the depositing step is carried out so that the first percentage is about 20 - 50 percent.
30. The method according to claim 28 wherein the depositing step is carried out so that the first percentage is at most about 50 %.
31. The method according to claim 28 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.
32. A method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: selecting an adhesive/spacer material having spacer elements within an adhesive; choosing an amount of the adhesive/spacer material; depositing the chosen amount the adhesive/spacer material onto a first surface of a first die; providing a second surface of the second die with a dielectric layer; locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation; and the choosing and depositing steps carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step.
33. The method according to claim 32 wherein the depositing step is carried out to create a single, continuous expanse of the adhesive/spacer material after the securing step.
34. The method according to claim 32 wherein the choosing step is carried out so that the adhesive/spacer material occupies about 20 - 50% of the die bonding region.
35. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die comprising a first surface with bond pads at the first surface; connecting the bond pads and the substrate with wires; selecting an adhesive/spacer material having spacer elements within an adhesive; depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions; locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; and securing the first and second die to one another at a chosen separation to create a multiple-die assembly; the selecting and depositing steps carried out so that the adhesive/spacer material occupies a first percentage of the die bonding region, the first percentage being at most about 50%; and encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.
36. The method according to claim 35 wherein the depositing step is carried out so that the first percentage is about 20 - 50%.
37. The method according to claim 35 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.
38. An adhesive/spacer structure for adhering a first device to a second device in a stacked semiconductor assembly, wherein the adhesive/spacer structure comprises a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation.
39. The adhesive/spacer structure of claim 38, wherein the first device is a die.
40. The adhesive/spacer structure of claim 38, wherein the first device is a package.
41. The adhesive/spacer structure of claim 38, wherein the second device is a package.
PCT/US2005/017893 2004-05-24 2005-05-20 Adhesive/spacer island structure for multiple die package WO2005117111A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US57390304P 2004-05-24 2004-05-24
US60/573,903 2004-05-24
US10/969,116 2004-10-20
US10/969,116 US20050258527A1 (en) 2004-05-24 2004-10-20 Adhesive/spacer island structure for multiple die package

Publications (3)

Publication Number Publication Date
WO2005117111A2 true WO2005117111A2 (en) 2005-12-08
WO2005117111A3 WO2005117111A3 (en) 2006-02-23
WO2005117111B1 WO2005117111B1 (en) 2006-04-06

Family

ID=35451552

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/017893 WO2005117111A2 (en) 2004-05-24 2005-05-20 Adhesive/spacer island structure for multiple die package

Country Status (1)

Country Link
WO (1) WO2005117111A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006037512A1 (en) * 2006-08-10 2008-02-14 Infineon Technologies Ag Stacked module of semiconductor chips has elastic spheres, for movement, compressed between the layers by fasteners in a compact structure
US7993969B2 (en) 2006-08-10 2011-08-09 Infineon Technologies Ag Method for producing a module with components stacked one above another

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US20040039127A1 (en) * 2002-08-26 2004-02-26 Satoru Amou Electronic device using low dielectric loss tangent insulators for high frequency signals
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
US20040039127A1 (en) * 2002-08-26 2004-02-26 Satoru Amou Electronic device using low dielectric loss tangent insulators for high frequency signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006037512A1 (en) * 2006-08-10 2008-02-14 Infineon Technologies Ag Stacked module of semiconductor chips has elastic spheres, for movement, compressed between the layers by fasteners in a compact structure
DE102006037512B4 (en) * 2006-08-10 2010-04-15 Infineon Technologies Ag Module and method for manufacturing a module with stacked components
US7993969B2 (en) 2006-08-10 2011-08-09 Infineon Technologies Ag Method for producing a module with components stacked one above another

Also Published As

Publication number Publication date
WO2005117111A3 (en) 2006-02-23

Similar Documents

Publication Publication Date Title
US8030134B2 (en) Stacked semiconductor package having adhesive/spacer structure and insulation
US8552551B2 (en) Adhesive/spacer island structure for stacking over wire bonded die
US6919627B2 (en) Multichip module
US7298032B2 (en) Semiconductor multi-chip package and fabrication method
US8623704B2 (en) Adhesive/spacer island structure for multiple die package
KR100996318B1 (en) Semiconductor Multipackage Module Including Die and Inverted Land Grid Array Package Stacked Over Ball Grid Array Package
US20050258545A1 (en) Multiple die package with adhesive/spacer structure and insulated die surface
US8143727B2 (en) Adhesive on wire stacked semiconductor package
US6759737B2 (en) Semiconductor package including stacked chips with aligned input/output pads
US20080026506A1 (en) Semiconductor multi-chip package and fabrication method
US20030038355A1 (en) Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US20040262774A1 (en) Multi-chip packages having a plurality of flip chips and methods of manufacturing the same
US20090317947A1 (en) Semiconductor package with heat sink, stack package using the same and manufacturing method thereof
US20140175625A1 (en) Semiconductor device including at least one element
JP2003078105A (en) Stacked chip module
KR20060125574A (en) Epoxy bump for overhang die
US20060063306A1 (en) Semiconductor package having a heat slug and manufacturing method thereof
WO2005117111A2 (en) Adhesive/spacer island structure for multiple die package
TWI445157B (en) Adhesive/spacer island structure for multiple die package
TWI431729B (en) Stacked semiconductor package having adhesive/spacer structure and insulation
CN213071106U (en) Semiconductor packaging structure
WO2005117092A2 (en) Stacked semiconductor package having adhesive/spacer structure and insulation
KR101096441B1 (en) Thin package and multi package using the same
WO2002009181A1 (en) Vertically integrated chip on chip circuit stack
TWI443788B (en) Semiconductor package and fabrication method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
B Later publication of amended claims

Effective date: 20060113

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

122 Ep: pct application non-entry in european phase