WO2005117111A3 - Adhesive/spacer island structure for multiple die package - Google Patents

Adhesive/spacer island structure for multiple die package Download PDF

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Publication number
WO2005117111A3
WO2005117111A3 PCT/US2005/017893 US2005017893W WO2005117111A3 WO 2005117111 A3 WO2005117111 A3 WO 2005117111A3 US 2005017893 W US2005017893 W US 2005017893W WO 2005117111 A3 WO2005117111 A3 WO 2005117111A3
Authority
WO
WIPO (PCT)
Prior art keywords
package
die
adhesive
spacer
devices
Prior art date
Application number
PCT/US2005/017893
Other languages
French (fr)
Other versions
WO2005117111B1 (en
WO2005117111A2 (en
Inventor
Sang Ho Lee
Jong Wook Ju
Hyeog Chan Kwon
Marcos Karnezos
Original Assignee
Chippac Inc
Sang Ho Lee
Jong Wook Ju
Hyeog Chan Kwon
Marcos Karnezos
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/969,116 external-priority patent/US20050258527A1/en
Application filed by Chippac Inc, Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon, Marcos Karnezos filed Critical Chippac Inc
Publication of WO2005117111A2 publication Critical patent/WO2005117111A2/en
Publication of WO2005117111A3 publication Critical patent/WO2005117111A3/en
Publication of WO2005117111B1 publication Critical patent/WO2005117111B1/en

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an 'upper' package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate. Also, methods are disclosed for making assemblies including the adhesive/spacer island structures.
PCT/US2005/017893 2004-05-24 2005-05-20 Adhesive/spacer island structure for multiple die package WO2005117111A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US57390304P 2004-05-24 2004-05-24
US60/573,903 2004-05-24
US10/969,116 2004-10-20
US10/969,116 US20050258527A1 (en) 2004-05-24 2004-10-20 Adhesive/spacer island structure for multiple die package

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WO2005117111A2 WO2005117111A2 (en) 2005-12-08
WO2005117111A3 true WO2005117111A3 (en) 2006-02-23
WO2005117111B1 WO2005117111B1 (en) 2006-04-06

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Publication number Priority date Publication date Assignee Title
US7993969B2 (en) 2006-08-10 2011-08-09 Infineon Technologies Ag Method for producing a module with components stacked one above another
DE102006037512B4 (en) * 2006-08-10 2010-04-15 Infineon Technologies Ag Module and method for manufacturing a module with stacked components

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US20040039127A1 (en) * 2002-08-26 2004-02-26 Satoru Amou Electronic device using low dielectric loss tangent insulators for high frequency signals
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441496B1 (en) * 2000-11-22 2002-08-27 Wen Chuan Chen Structure of stacked integrated circuits
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
US20040039127A1 (en) * 2002-08-26 2004-02-26 Satoru Amou Electronic device using low dielectric loss tangent insulators for high frequency signals

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