WO2005117416A1

WO2005117416A1 - Apparatus and method for filtering signals

Info

Publication number: WO2005117416A1
Application number: PCT/US2005/015862
Authority: WO
Inventors: Mark Francis Rumreich
Original assignee: Thomson Licensing S.A.
Priority date: 2004-05-20
Filing date: 2005-05-05
Publication date: 2005-12-08

Abstract

An apparatus (100) for filtering signals reduces gate requirements by using a shared front-end and a statistically pipelined back-end. According to an exemplary embodiment, the apparatus (100) includes circuitry (641-650) operative to generate a plurality of signals representing a respective plurality of filter tap values. A first filter (660) generates a first filtered carrier signal using the plurality of filter tap values. A second filter (665) generates a second filtered carrier signal using the plurality of filter tap values.

Description

TITLE APPARATUS AND METHOD FOR FILTERING SIGNALS

CROSS REFERENCE TO RELATED APPLICATION This application claims priority to and all benefits accruing from a provisional application filed in the United States Patent and Trademark Office on May 20, 2004, and having assigned serial number 60/572,925.

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to signal processing in an apparatus such as a television signal receiver, and more particularly, to an apparatus and method for filtering signals that reduces gate requirements by using a shared front-end and a statistically pipelined back-end.

Background Information Apparatuses such as television signal receivers often employ signal processing functions that include signal filtering. For example, certain conventional analog television signal receivers often utilize a surface acoustic wave (SAW) filter to remove adjacent channel energy from a desired channel and provide in-band filtering within the desired channel. Television signal receivers capable of processing signals digitally may also utilize a SAW filter to remove adjacent channel energy from a desired signal, but may use digital filtering techniques to provide in-band filtering within the desired channel. Such digital filtering techniques may for example provide multiple, simultaneous, high-order finite impulse response filter outputs for a given input signal. At present, the implementation of such digital filtering techniques typically requires a relatively large number of gates, including signal multipliers, which can increase the complexity and cost of an end product.

Accordingly, there is a need for an apparatus and method for filtering signals that addresses the foregoing issues and thereby reduces the number of gates required for implementation. The present invention addresses these and/or other issues.

SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, an apparatus for filtering signals is disclosed. According to an exemplary embodiment, the apparatus comprises means for generating a plurality of signals representing a respective plurality of filter tap values, first filtering means for generating a first filtered carrier signal using the plurality of filter tap values, and second filtering means for generating a second filtered carrier signal using the plurality of filter tap values.

In accordance with another aspect of the present invention, a method for performing signal processing is disclosed. According to an exemplary embodiment, the method comprises steps of generating a plurality of signals representing a respective plurality of filter tap values, generating a first filtered

■ carrier signal using the plurality of filter tap values, and generating a second filtered carrier signal using the plurality of filter tap values. In accordance with yet another aspect of the present invention, a television signal receiver is disclosed. According to an exemplary embodiment, the television signal receiver comprises circuitry operative to generate a plurality of signals representing a respective plurality of filter tap values, a first filter operative to generate a first filtered carrier signal using the plurality of filter tap values, and a second filter operative to generate a second filtered carrier signal using the plurality of filter tap values.

BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other features and advantages of this invention, and the manner of attaining them, will become more apparent and the invention will be better understood by reference to the following description of embodiments of the invention taken in conjunction with the accompanying drawings, wherein: FIG. 1 is a block diagram of an apparatus according to an exemplary embodiment of the present invention; FIG. 2 is a diagram providing further details of the IF processing block of FIG. 1 according to an exemplary embodiment of the present invention; FIG. 3 is a diagram providing further details of the front end filters of

FIG. 2 according to an exemplary embodiment of the present invention; FIG. 4 is a diagram providing further details of the P, S and VSB filters of FIG. 3 according to an exemplary embodiment of the present invention; and FIG. 5 is a flowchart illustrating steps according to an exemplary embodiment of the present invention. The exemplifications set out herein illustrate preferred embodiments of the invention, and such exemplifications are not to be construed as limiting the scope of the invention in any manner. . . DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, and more particularly to FIG. 1 , a block diagram of an apparatus 100 according to an exemplary embodiment of the present invention is shown. As shown in FIG. 1 , apparatus 100 comprises signal receiving means such as signal receiving element 10, tuning means such as tuner 20, filtering means such as SAW filter 30, amplifying means such as amplifier 40, analog-to-digital converting means such as analog-to- digital converter (ADC) 50, and intermediate frequency (IF) processing means such as IF processing block 60. Some of the foregoing elements of FIG. 1 may be embodied using integrated circuits (ICs), and some elements may for example be included on one or more ICs. For clarity of description, certain conventional elements associated with apparatus 100 such as certain control signals, power signals, clock signals and/or other elements may not be shown in FIG. 1. According to an exemplary embodiment, apparatus 100 is embodied as a television signal receiver, but may be embodied as another type of apparatus or device.

Signal receiving element 10 is operative to receive an RF signal from one or more signal sources such as terrestrial, cable, satellite, internet and/or other signal sources. According to an exemplary embodiment, signal receiving element 10 is embodied as an antenna, but may also be embodied as any type of signal receiving element such as an input terminal and/or other element. 5 Tuner 20 is operative to perform a signal tuning function. According to an exemplary embodiment, tuner 20 receives the RF input signal from signal receiving element 10, and performs the signal tuning function by filtering and frequency downconverting (i.e., single or multiple stage downconversion) the

J O RF input signal to thereby generate an IF signal. The RF input signal and IF signal may include audio, video and/or data content, and may be of an analog modulation scheme (e.g., NTSC, PAL, SECAM, etc.) and/or a digital modulation scheme (e.g., ATSC, QAM, etc.). According to an exemplary embodiment, tuner 20 produces at its output a picture carrier having a carrier

15 frequency of 45.75 MHz and a sound carrier having a carrier frequency of 41 .25 MHz. Also according to an exemplary embodiment, tuner 20 receives an RF AGC signal from IF processing block 60 which enables an RF AGC function.

20 SAW filter 30 is operative to filter the IF signal provided from tuner 20 to thereby generate a filtered IF signal. According to an exemplary embodiment, SAW filter 30 includes one or more individual SAW filters which remove a substantial portion of the undesired, adjacent channel energy from, the IF signal provided from tuner 20 to generate the filtered IF signal. 5 Amplifier 40 is operative to amplify the filtered IF signal provided from SAW filter 30 to thereby generate an amplified IF signal. According to an exemplary embodiment, amplifier 40 receives an IF AGC signal from IF processing block 60 which enables an IF AGC function. 0 ADC 50 is operative to perform an analog-to-digital conversion function. According to an exemplary embodiment, ADC 50 converts the amplified IF signal provided from amplifier 40 from an analog format to a digital format to thereby generate a digital IF signal. According to this exemplary embodiment, the clock frequency of ADC 50 (and the digital processing after it) is 25.1429 MHz, although other clock frequencies may also be used.

IF processing block 60 is operative to perform various IF processing functions. According to an exemplary embodiment, IF processing block 60 processes the digital IF signal provided from ADC 50 to thereby generate various digitally processed signals. As will be described later herein, IF processing block 60 includes filtering means that reduce gate requirements by using a shared front-end and a statistically pipelined back-end.

Referring to FIG. 2, a diagram providing further details of IF processing block 60 of FIG. 1 according to an exemplary embodiment of the present invention is shown. As indicated in FIG. 2, digital IF processing block 60 comprises automatic gain control (AGC) and distortion canceling means such as AGC and distortion canceling block 600, front end filtering means such as front end filter 640, phase lock loop (PLL) means such as PLL 680, fine tuning means such as automatic fine tuning (AFT) block 720, video detecting and filtering means such as video detector and filter 760, fine gain adjusting means such as fine gain adjustment block 800, AGC detecting means such as AGC detector 840, digital-to-analog converting means such as digital-to- analog converter (DAC) 880, audio detecting and filtering means such as audio detector and filter 920, and wide band audio means such as wide band audio block 960. The foregoing elements of FIG. 2 may be embodied using ICs, and some elements may for example be included on one or more ICs. Although not expressly shown, the elements of FIG. 2 are clocked in accordance with a_. clock signal, which according to an exemplary embodiment has a frequency of 25.1429 MHz. Other clock frequencies may also be used according to the present invention. Also in FIG. 2, the number above each signal line represents the bit width of each signal according to an exemplary embodiment, although other bit widths may also be used. The "*" symbol indicates that the signal is unsigned. AGC and distortion canceling block 600 is operative to perform AGC and distortion canceling functions. According to an exemplary embodiment, AGC and distortion canceling block 600 receives and processes the 10-bit digital IF signal (IFJN) provided from ADC 50 to thereby generate a 10-bit digitally processed IF signal. As indicated in FIG. 2, AGC and distortion canceling block 600 performs its functions responsive to certain control signals including a 10-bit DIGAGC signal, a 4-bit NONLIN PHASE signal, and an 8-bit NONLINEARITY signal. According to an exemplary embodiment, the 10-bit DIGAGC signal is used to control a digital AGC function, while the 4-bit NONLIN_PHASE signal and the 8-bit NONLINEARITY signals are used to control a distortion canceling function. The values of the DIGAGC, NONLIN_PHASE and NONLINEARITY signals may be selected by an application circuit designer as a matter of design choice and programmed into a non-volatile memory (not shown in FIGS.) of apparatus 100. AGC and distortion canceling block 600 may receive the DIGAGC, NONLIN_PHASE and NONLINEARITY signals via an inter-integrated circuit (IIC) bus.

Front end filters 640 are operative to perform front end filtering functions, and may for example provide in-band filtering within a desired channel. According to an exemplary embodiment, front end filters 640 process the 10-bit digitally processed IF signal provided from AGC and distortion canceling block 600 to thereby generate three digitally filtered signals, namely, a P_FILTER signal, an S_FILTER signal, and a VSB_FILTER signal. As indicated in FIG. 2, each of these filtered signals is a

12-bit digital signal. The P_FILTER signal is a narrow bandpass filtered signal, centered on the picture carrier. The S_FILTER signal is a narrow bandpass filtered signal, centered on the sound carrier. The VSB_FILTER signal is a vestigial sideband signal having a specified vestigial slope in the vicinity of the picture carrier and approximately flat passband to beyond a chroma subcarrier frequency. In other words, the VSB_FILTER signal is a composite video signal having vestigial sideband filtering. Further details regarding front end filters 640 will be provided later herein with reference to FIG. 3.

PLL 680 is operative to generate in-phase and quadrature picture subcarrier signals. According to an exemplary embodiment, PLL 680 generates a 10-bit in-phase picture subcarrier signal, LSUBCARRIER, and a 10-bit quadrature picture subcarrier signal, Q_SUBCARRIER, responsive to the 12-bit P_FILTER signal provided from front end filters 640. In particular, the P_FILTER signal drives PLL 680 to enable generation of the sinusoidal LSUBCARRIER and Q_SUBCARRIER signals used by other elements of IF processing block 60, as will be described later herein. Also according to an exemplary embodiment, PLL 680 is operative to generate a 19-bit frequency error signal that represents a detected frequency error in PLL 680. AFT block 720 is operative to control an automatic fine tuning function.

According to an exemplary embodiment, AFT block 720 generates an 8-bit AFT signal responsive to the 19-bit frequency error signal provided from PLL 680, and provides the 8-bit AFT signal to a processor (not shown in FIGS.) to thereby control the automatic fine tuning function.

Video detector and filter 760 is operative to perform video detection and filtering functions. According to an exemplary embodiment, video detector and filter 760 multiplies the 12-bit VSB_FILTER signal with the 12-bit l-SUBCARRIER signal and filters the resultant multiplied signal to remove sound and undesired adjacent channel energy and thereby generate a 12-bit filtered video signal.

Fine gain adjustment block 800 is operative to perform a fine gain adjustment function. According to an exemplary embodiment, fine gain adjustment block 800 performs the fine gain adjustment function responsive to a 5-bit FINE_VID_ATTEN signal provided via an IIC bus to thereby generate a 10-bit VIDEO signal. The value of the FINE_VID_ATTEN signal may be selected by an application circuit designer as a matter of design choice and programmed into a non-volatile memory (not shown in FIGS.) of apparatus 100.

AGC detector 840 is operative to perform AGC detection functions. According to an exemplary embodiment, AGC detector 840 performs the AGC detection functions responsive to various RF and IF AGC signals including an 8-bit RFAGC DFFSET signal, a 6-bit RFAGC_GAIN signal, an 8-bit IFAGC_OFFSET signal, a 6-bit IFAGCJ3AIN ...signal, an 8-bit DIGAGC_OFFSET signal, and a 6-bit DIGAGC 3AIN signal. The aforementioned signals are provided to AGC detector 840 via an IIC bus, and are used to generate a 10-bit RFAGC signal, a 10-bit IFAGC signal, and a 10- bit DIGAGC signal that control the loop gain and offset (i.e., delay point) for RF and IF AGC functions. The values of the aforementioned signals may be selected by an application circuit designer as a matter of design choice and programmed into a non-volatile memory (not shown in FIGS.)' of apparatus 100.

DAC 880 is operative to perform a digital-to-analog conversion function. According to an exemplary embodiment, DAC 880 converts the 10- bit RFAGC signal and the 10-bit IFAGC signal to an analog RFAGC_NTSC signal and an analog IFAGC_NTSC signal, respectively. The RFAGC_NTSC signal and the IFAGC_NTSC signal are provided to tuner 20 and amplifier 40, respectively, as shown in FIG. 1 to thereby provide RF and IF AGC functions. DAC 880 may for example be embodied as a binary rate multiplier.

Audio detector and filter 920 is operative to an audio detection and filtering function. According to an exemplary embodiment, audio detector and filter 920 multiplies the 12-bit S_FILTER' signal with the 12-bit Q- SUBCARRIER signal and filters the resultant multiplied signal to thereby generate a 12-bit filtered audio signal representing a 4.5 MHz sound subcarrier. Wide band audio block 960 is operative to generate a wide band audio signal. According to an exemplary embodiment, wide band audio block 960 generates a 16-bit wide band audio signal responsive to the 12-bit filtered audio signal provided from audio detector and filter 920.

Referring to FIG. 3, a diagram providing further details of front end filters 640 of FIG. 2 according to an exemplary embodiment of the present invention is shown. As indicated in FIG. 3, front end filters 640 comprise shared front-end means such as circuitry 641 to 650 for generating a plurality of filter tap values, first filtering means such as P filter 660, second filtering means such as S filter 665, and third filtering means such as VSB filter 670. The foregoing elements of FIG. 3 may be embodied using ICs, and some elements may for example be included on one or more ICs. Although not expressly shown, the elements of FIG. 3 are clocked in accordance with a clock signal, which according to an exemplary embodiment has a frequency of 25.1429 MHz. Other clock frequencies may also. be used according to the present invention. Also in FIG. 3, the number above each signal line represents the bit width of each signal according to an exemplary embodiment, although other bit widths may also be used.

In FIG. 3, circuitry 641 to 650 comprises D-type flip-flops 641 to 646, adders 647 and 648, and dividers 649 and 650. As indicated in FIG. 3, circuitry 641 to 650 is shown as an abbreviated version of the shared front- end means that generates a plurality of filter tap values according to the present invention. In practice, additional D-type flip-flops, adders and dividers are utilized to form a delay line that provides sixty-nine delay taps (i.e., DLY 0 to DLY 68). As indicated in FIG. 3, the delay line providing the sixty-nine delay taps is folded to produce thirty-five filter tap values (i.e., TERM 0 to TERM 34). In particular, the first filter tap value TERM 0 is the sum of the values provided by the first and last delay taps (i.e., DLY 0 and DLY 68) divided by two. Similarly, the second filter tap value TERM 1 is the sum of the values provided by the second and next-to-last delay taps (i.e., DLY 1 and DLY 67) divided by two. The third through thirty-fourth filter tap values TERM 2 to TERM 33 are computed in a similar manner. The thirty-fifth filter tap value TERM 34 is simply the value provided by the thirty-fifth delay tap DLY 34. P filter 660 is operative to generate the 12-bit P_FILTER signal using the filter tap values (i.e., TERM 0 to TERM 34) provided from the circuitry including elements 641 to 650. As previously described herein, the P_FILTER signal is a narrow bandpass filtered signal centered.,øn the picture carrier. S filter 665 is operative to generate the 12-bit S_FILTER signal using the filter tap values (i.e., TERM 0 to TERM 34) provided from the circuitry including elements 641 to 650. As previously described herein, the S_FILTER signal is a narrow bandpass filtered signal centered on the sound carrier. VSB filter 670 is operative to generate the 12-bit VSB_FILTER signal using the filter tap values (i.e., TERM 0 to TERM 34) provided from the circuitry including elements 641 to 650. As previously described herein, the

VSB_FILTER signal is a vestigial sideband signal having a specified vestigial slope in the vicinity of the picture carrier and approximately flat passband to beyond a chroma subcarrier frequency. Accordingly, P filter 660, S filter 665, and VSB filter 670 all share and utilize the same filter tap values (i.e., TERM 0 to TERM 34) generated by the shared front-end means of front end filters 640, and thereby reduce the gate requirements of apparatus 100.

Referring now to FIG. 4, a diagram providing further details of P filter 660, S filter 665 and VSB filter 670 of FIG. 3 according to an exemplary embodiment of the present invention is shown. In particular, P filter 660, S filter 665 and VSB filter 670 of FIG. 3 each have the same statistically pipelined architecture represented in FIG. 4, but use different filter coefficient values. For purposes of example and explanation, however, FIG. 4 is shown as representing P filter 660.

As shown in FIG. 4, P filter 660 comprises four parallel processing paths providing outputs that are processed by a fifth processing path. The first processing path comprises coefficient blocks 401 and 402, adding means such as sum block 403, divider 404, and D-type flip-flop 405. The second processing path comprises coefficient blocks 41 1 and 412, adding means such as sum block 413, divider 414, and D-type flip-flop 415. The third processing path comprises coefficient blocks 421 and 422, adding means such as sum block 423, divider 424, and D-type flip-flop 425. The fourth processing path comprises coefficient blocks 431 and 432, adding means such as sum block 433, divider 434, D-type flip-flop 435, and divider 436. The fifth processing path comprises adding means such as sum block 441 , a ten times block 442, an adder 443, a divider 444, a limiter 445, and a D-type flip- flop 446. Although not expressly shown, the elements of FIG. 4 are clocked in accordance with a clock signal, which according to an exemplary embodiment has a frequency of 25.1429 MHz. Other clock frequencies may also be used according to the present invention. Also in FIG. 4, the number above each signal line represents the bit width of each signal according to an exemplary embodiment, although other bit widths may also be used.

Functionally, the first, second, third and fourth processing paths of P filter 660 described above are operative to calculate the weighted sum of the thirty-five filter tap values (i.e., TERM 0 to TERM 34) provided from the shared front-end means of FIG. 3 represented by circuitry 641 to 650. According to an exemplary embodiment, filter coefficient values a_0 to a_34 used in FIG. 4 are fixed values selected as a matter of design choice, and are respectively multiplied by filter tap values TERM 0 to TERM 34 without using multipliers. That is, coefficient blocks 401 , 402, 41 1 , 412, 421 , 422, 431 and 432 and sum blocks 403, 413, 423 and 433 use adders (and subtractors), but do not use multipliers. According to the present invention, multiplication operations are performed using adding, subtracting and bit shifting operations. For example, to calculate nine times a term, the present invention adds eight times the term (left shift by three bits) to one times the term.

The exact number of terms to be added together in FIG. 4 depends on filter coefficient values a_0 to a_34. In FIG. 4, filter coefficient values a_30 to a_34 used in the fourth processing path are respectively multiplied (using adding and bit shifting operations) by centermost filter tap values TERM 30 to TERM 34 produced near the centermost tap of the shared front-end means of FIG. 3. Accordingly, filter coefficient values a_30 to a_34 tend to have relatively large magnitudes, and therefore statistically generate more terms that need to be added together. Conversely, filter coefficient values a_0 to a_12 used in the first processing path of FIG. 4 are respectively multiplied (using adding and bit shifting operations) by outermost filter tap values TERM 0 to TERM 12 produced near the outermost taps of the shared front-end means of FIG. 3. Accordingly, filter coefficient values a_0 to a_12 tend to have relatively small magnitudes, and therefore statistically generate fewer terms that need to be added together. The aforementioned statistical properties are taken advantage of in FIG. 4 through the pipelined architecture of the first, second, third and fourth processing paths which each process a different number of the filter tap values (i.e., TERM 0 to TERM 34).

In FIG. 4, the weighted sum of filter tap values TERM 0 to TERM 12 (i.e., the thirteen outermost filter tap values) are calculated and processed by the first processing path. Similarly, the weighted sum of filter tap values TERM 13 to TERM 21 are calculated and processed by the second processing path. The weighted sum of filter tap values TERM 22 to TERM 29 are calculated and processed by the third processing path. The weighted sum of filter tap values TERM 30 to TERM 34 (i.e., the five centermost filter tap values) are calculated and processed by the fourth processing path. According to the present invention, the first, second, third and fourth processing paths of FIG. 4 each process a different number of the filter tap values TERM 0 to TERM 34, but produce similar numbers of terms for their respective sum blocks 403, 413, 423 and 433. This maximizes the number of adding operations that can be performed in each clock cycle, and thereby optimizes the statistical pipelining operation of the present invention.

As indicated in FIG. 4, the outputs from the first, second, third and fourth processing paths are added together via sum block 441 to thereby generate a 20-bit combined sum signal. Ten times block 442 is operative to multiply (using adding and bit shifting operations) the 20-bit combined sum signal provided from sum block 441 by a value of ten to thereby generate a 25-bit output signal. Adder 443 is operative to add the 25-bit output signal provided from ten times block 442 to a value of 512 to thereby generate a 26- bit sum signal. Divider 444 is operative to divide the 26-bit sum signal provided from adder 443 by a value of 1024 to thereby generate a 16-bit divided signal. Limiter 445 is operative to limit the 16-bit divided signal provided from divider 444 to a range of predetermined values, which may be set as a matter of design choice, to thereby generate a 12-bit limited signal. D-type flip-flop 446 is operative to receive and output the 12-bit limited signal provided from limiter 445 in accordance with the applicable clock signal to thereby provide the 12-bit P_FILTER signal previously described herein.

To facilitate a better understanding of the present invention, an example will now be provided. Referring now to FIG. 5, a flowchart 500 illustrating steps according to an exemplary embodiment of the present invention is shown. For purposes of example and explanation, the steps of FIG. 5 will be described with reference to the elements of apparatus. 100 as previously described herein. The steps of FIG. 5 are merely exemplary, and are not intended to limit the present invention in any manner.

At step 510, apparatus 100 generates a plurality of filter tap values using the shared front-end means of front end filters 640. According to an exemplary embodiment, the shared front-end means of front end filter 640 represented by circuitry 641 to 650 of FIG. 3 generates a plurality of signals representing the filter tap values TERM 0 to TERM 34 at step 510.

At step 520, apparatus 100 generates a first filtered carrier signal using the filter tap values generated at step 510. According to an exemplary embodiment, P filter 660 generates the 12-bit P_FILTER signal at step 520 using the filter tap values TERM 0 to TERM 34 generated at step 510. According to this exemplary embodiment, the P_FILTER signal is a narrow bandpass filtered signal centered on the picture carrier. At step 530, apparatus 100 generates a second filtered carrier signal using the filter tap values generated at step 510. According to an exemplary embodiment, S filter 665 generates the 12-bit S_FILTER signal at step 530 using the filter tap values TERM 0 to TERM 34 generated at step 510. According to this exemplary embodiment, the S_FILTER signal is a narrow bandpass filtered signal centered on the sound carrier.

At step 540, apparatus 100 generates a composite video signal using the filter tap values generated at step 510. According to an exemplary embodiment, VSB filter 670 generates the 12-bit VSB_FILTER signal at step 540 using the filter tap values TERM 0 to TERM 34 generated at step 510. According to this exemplary embodiment, the VSB_FILTER signal is a vestigial sideband signal having a specified vestigial slope in the vicinity of the picture carrier and approximately flat passband to beyond a chroma subcarrier frequency.

Steps 520 to 540 described above are preferably performed simultaneously. In steps 520 to 540, P filter 660, S filter 665, and VSB filter 670 each utilize the same filter tap values generated by the shared front-end means of front end filter 640 at step 510, and thereby reduce gate requirements of apparatus 100. Moreover, P filter 660, S filter 665, and VSB filter 670 each employ the same statistically pipelined architecture represented in FIG. 4, but use different filter coefficient values. This statistically pipelined architecture uses adders (and subtractors), but does not use multipliers. Rather, multiplication operations are performed using adding, subtracting and bit shifting operations. Since each of the first, second, third and fourth processing paths of the statistically pipelined architecture (see FIG. 4) processes a different number of the filter tap values TERM 0 to TERM 34, similar numbers of terms are produced for each path's respective sum block (i.e., elements 403, 413, 423 and 433 of FIG. 4). This maximizes the number of adding operations that can be performed in each clock cycle, and thereby optimizes the statistical pipelining operation of the present invention. As described herein, the present invention provides an apparatus and method for filtering signals that reduces gate requirements by using a shared front-end and a statistically pipelined back-end. The present invention may be applicable to various apparatuses, either with or without an integrated display device. Accordingly, the phrase "television signal receiver" as used herein may refer to systems or apparatuses including, but not limited to, television sets, computers or monitors that include an integrated display device, and systems or apparatuses such as set-top boxes, video cassette recorders (VCRs), digital versatile disk (DVD) players, video game boxes, personal video recorders (PVRs), computers or other apparatuses that may not include an integrated display device.

While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. An apparatus (100), comprising: means (641 -650) for generating a plurality of signals representing a respective plurality of filter tap values; first filtering means (660) for generating a first filtered carrier signal using said plurality of filter tap values; and second filtering means (665) for generating a second filtered carrier signal using said plurality of filter tap values.

2. The apparatus (100) of claim 1 , wherein said first filtered carrier signal represents a picture carrier and said second filtered carrier signal represents a sound carrier.

3. The apparatus (100) of claim 1 , further comprising third filtering means (670) for generating a composite video signal using said plurality of filter tap values.

4. The apparatus (100) of claim 3, wherein each of said first, second and third filtering means (660, 665, 670) includes a plurality of adders and does not include multipliers.

5. The apparatus (100) of claim 3, wherein each of said first, second and third filtering means (660, 665, 670) includes: a plurality of adding means (403, 413, 423, 433); and each one of said adding means processes a different number of said filter tap values.

6. The apparatus (100) of claim 5, wherein, for each of said first, second and third filtering means (660, 665, 670): a first one of said adding means (433) processes a first predetermined number of said filter tap values representing centermost filter tap values; a second one of said adding means (403) processes a second, predetermined number of said filter tap values representing outermost filter tap values; and said first predetermined number is smaller than said second predetermined number.

7. A method (500) for performing signal processing, comprising: generating a plurality of signals representing a respective plurality of filter tap values (510); generating a first filtered carrier signal using said plurality of filter tap values (520); and generating a second filtered carrier signal using said plurality of filter tap values (530).

8. The method (500) of claim 7, wherein said first filtered carrier signal represents a picture carrier and said second filtered carrier signal represents a sound carrier.

9. The method (500) of claim 7, further comprised of generating a. composite video signal using said plurality of filter tap values (540).

10. The method (500) of claim 9, wherein said first filtered carrier signal, said second filtered carrier signal, and said composite video signal are generated using a plurality of adders and without using multipliers.

1 1. The method (500) of claim 9, wherein: said first filtered carrier signal is generated using a first filter; said second filtered carrier signal is generated using a second filter; said composite video signal is generated using a third filter; each of said first, second and third filters includes a plurality of adding means; and each one of said adding means processes a different number of said filter tap values.

12. The method (500) of claim 1 1 , wherein each of said first, second and third filters: uses a first one of said adding means to process a first predetermined number of said filter tap values representing centermost filter tap alues; . uses a second one of said adding means to process a second predetermined number of said filter tap values representing outermost filter tap values; and said first predetermined number is smaller than said second predetermined number.

13. A television signal receiver (100), comprising: circuitry (641 -650) operative to generate a plurality of signals representing a respective plurality of filter tap values; a first filter (660) operative to generate a first filtered carrier signal using said plurality of filter tap values; and a second filter (665) operative to generate a second filtered carrier signal using said plurality of filter tap values.

14. The television signal receiver apparatus (100) of claim 13, wherein said first filtered carrier signal represents a picture carrier and said second filtered carrier signal represents a sound carrier.

15. The television signal receiver (100) of claim 13, further comprising a third filter (670) operative to generate a composite video signal using said plurality of filter tap values.

16. The television signal receiver (100) of claim 15, wherein each of said first, second and third filters (660, 665, 670) includes a plurality of adders and does not include multipliers.

17. The television signal receiver (100) of claim 15, wherein each of said first, second and third filters (660, 665, 670) includes: a plurality of adding means (403, 413, 423, 433); and each one of said adding means processes a different number of said filter tap values.

18. The television signal receiver (100) of claim 17, wherein, for each of said first, second and third filters (660, 665, 670): a first one of said adding means (433) processes a first predetermined number of said filter tap values representing centermost filter tap values; a second one of said adding means (403) processes a second predetermined number of said filter tap values representing outermost filter tap values; and said first predetermined number is smaller than said second predetermined number.