WO2005122028A2 - Local preferred direction architecture, tools, and apparatus - Google Patents

Local preferred direction architecture, tools, and apparatus Download PDF

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Publication number
WO2005122028A2
WO2005122028A2 PCT/US2005/019361 US2005019361W WO2005122028A2 WO 2005122028 A2 WO2005122028 A2 WO 2005122028A2 US 2005019361 W US2005019361 W US 2005019361W WO 2005122028 A2 WO2005122028 A2 WO 2005122028A2
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WO
WIPO (PCT)
Prior art keywords
region
wiring
regions
layer
preferred wiring
Prior art date
Application number
PCT/US2005/019361
Other languages
French (fr)
Other versions
WO2005122028A3 (en
Inventor
Asmus Hetzel
Anish Malhotra
Akira Fujimura
Etienne Jacques
Jon Frankle
David S. Harrison
Heath Feather
Alexandre Matveev
Roger King
Original Assignee
Cadence Design Systems, Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems, Inc filed Critical Cadence Design Systems, Inc
Priority to JP2007515561A priority Critical patent/JP2008502152A/en
Priority to EP05771286A priority patent/EP1763805A4/en
Publication of WO2005122028A2 publication Critical patent/WO2005122028A2/en
Publication of WO2005122028A3 publication Critical patent/WO2005122028A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing

Definitions

  • the invention is directed towards an apparatus for routing nets using a Local Preferred
  • An integrated circuit is a semiconductor device that includes many electronic
  • circuit components e.g., gates, cells, memory units,
  • An IC also includes multiple layers of
  • metal and/or polysilicon wiring that interconnect its electronic and circuit components.
  • metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring (i.e., the wiring can be in any arbitrary direction).
  • the layer typically has one global preferred wiring direction, and the preferred direction alternates
  • wires can only make 90° turns. Occasional diagonal jogs are sometimes allowed on the
  • Interconnect lines are considered “diagonal” if they form an angle other than zero or ninety degrees with respect to the layout boundary of the IC. Typically however, diagonal
  • wiring consists of wires deposed at ⁇ 45 degrees.
  • Typical Manhattan and diagonal wiring models specify one preferred direction for
  • obstacles may cause regions on a layer to become essentially unusable for routing along the
  • FIG. 1 shows two wiring layers that each
  • One of the layers has a horizontal preferred
  • the obstacles 115 and 120 cause
  • Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring
  • each region has a local
  • At least two regions have two different polygonal shapes and no region
  • Some embodiments also provide a Graphical
  • GUI User Interface
  • Figure 1 illustrates an example of regions essentially unusable for routing due to
  • Figure 2 illustrates an example of a design layout based upon an LPD wiring model.
  • Figure 3 illustrates another example of a design layout based upon an LPD wiring
  • Figure 4A illustrates a wiring layer with pre-designed circuit blocks.
  • Figure 4B illustrate the wiring layer of Figure 4A with LPD regions.
  • FIGS 5A-5C illustrate LPD regions extended with crowns.
  • Figure 6 illustrates merging LPD regions to encompass adjacent power stripes.
  • Figure 7 illustrates defining horizontal tracks on a diagonal layer to traverse over a
  • Figure 8 illustrates vias that have different via pad shapes according to some embodiment
  • Figure 9 illustrates a visual representation of a design layout using the Graphical User
  • Figure 10 illustrates the indication of LPD regions that overlap pre-designed circuit
  • Figures 11A-11E illustrate a user creating an LPD region using an "LPDR Creation Tool" in a design window of the Graphical User Interface according to some embodiments of
  • Figures HE and 11F illustrate a user moving an LPD region within a design window
  • Figures 12A and 12B illustrate a user specifying a local preferred direction for an
  • Figures 13A and 13B illustrate a user creating an LPD region using a "select and
  • Figures 13C and 13D illustrate a user creating an LPD region using a "select and
  • Figures 13E and 13F illustrate a user creating an LPD region using a "select and
  • Figures 14A and 14B illustrate a user manipulating attributes of LPD regions in a
  • Figure 15A and 15B illustrate a user employing a "menu window" method to
  • Figures 15C and 15D illustrate a user "crowning" an LPD region in a design window of a Graphical User Interface according to some embodiments of the invention.
  • Figures 16A and 16B illustrate a user adding a vertex to an impermeable boundary
  • the invention is directed towards an apparatus for routing nets using a Local Preferred
  • Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring
  • each region has a local
  • At least two regions have two different polygonal shapes and no region
  • Some embodiments also provide a Graphical
  • GUI User Interface
  • GUI for an EDA tool that employs an LPD wiring model.
  • the LPD wiring model of some embodiments allows for the creation of routes that have edges in the Manhattan or diagonal direction.
  • a Manhattan edge is either horizontal (0°)
  • diagonal edge forms angles other than 0° or 90°.
  • a diagonal edge typically forms a 45° angle
  • the coordinate axes are often parallel
  • the LPD wiring model of the layout or IC in terms of (1) several wiring layers, (2) a global
  • each wiring layer L has a "preferred" direction as the direction that a "preferred" direction.
  • direction of a layer as the direction for at least 1000 wires on the layer.
  • a region is called an LPD region (or an LPDR) when the region
  • each LPDR is entirely within
  • all LPDRs on a given layer intersect only at their
  • some embodiments require that all LPDRs are non-
  • an LPD wiring model allows at least one wiring layer to
  • Figure 2 illustrates an example of such a wiring layer in an IC or a design layout. This wiring
  • layer has LPDRs that have several different convex shapes and local preferred directions
  • This example shows a wiring layer 200 that
  • this layer 200 has a 45° global preferred direction.
  • an octagonal LPDR 205 that has a -
  • an octagonal LPDR 210 that has a horizontal local preferred
  • Figure 3 illustrates another example of another such wiring layer in an IC or a design
  • This wiring layer has LPD regions that have several different convex shapes according
  • This example shows a wiring layer 300 that has a
  • This layer 300 has four LPDRs that have different convex
  • region 305 Adjacent to the lower-left side of region 305 is a rectangular
  • LPDR 310 with a 45° local preferred direction. Adjacent to the upper-left side of region 305
  • region 305 is a square LPDR 320 with a horizontal local preferred direction.
  • LPD wiring model in a design layout or an IC do not illustrate any macros or other obstacles to the wiring on a layer. Macros are pre-designed complex circuit blocks used
  • Such blocks include IP blocks, RAM cells, and Power Via
  • FIGS. 4A and 4B provide examples that illustrate this particular advantage of the
  • Figure 4A illustrates a wiring layer 400 that has a diagonal
  • This wiring layer includes a column of power via arrays (power
  • some embodiments define LPDRs about these
  • FIG. 4B illustrates examples of such LPDRs.
  • preferred direction is defined to encompass the power via arrays 405.
  • the horizontal direction of the LPDRs allows wiring to route between the
  • This figure also shows three LPDRs 440 that have vertical local preferred directions
  • preferred direction is defined between the right side of the IP block 410 and the right
  • the boundary edge between LPDR 450 and LPDR 460 is defined as a 45° diagonal line to
  • Boundary edges as such are
  • pins 420 and 425 can now be connected
  • Some embodiments define a boundary edge between two regions as an "impermeable
  • edge when the edge runs parallel to either one of the local preferred directions of the two
  • a “crown” is an extension of an LPDR at a boundary between two regions.
  • a crown boundary is
  • crowns thus form boundary edges that allow the intersection of
  • Figures 5A-5C illustrate a detailed example of extending boundary edges of LPDRs
  • channels 580 and 590 are essentially
  • some embodiments of the invention replace the channels 580 and 590 with LPDRs
  • FIG. 545 illustrates an example of two triangular crowns 545 and 555 created to extend LPDR 520.
  • This figure also illustrates two triangular crowns 565 and 575 created to extend LPDR 530.
  • Crowns 545 and 555 are shaped differently than crowns 565 and 575. Crowns 545 and 555
  • crowns 565 and 575 are in the shape of a right triangle. Both shapes of crowns, however, form boundary edges that intersect with the
  • the horizontal wiring is able to route into and out of
  • Crowns can be defined to have various shapes. Typically however crowns are
  • crowns shaped like an isosceles triangle forrn two
  • crowns shaped like a right triangle typically form one permeable edge.
  • edge typically allows wiring to route through an LPDR from either the left or from the right
  • This one edge however is typically longer and thus intersects more wiring when
  • the invention dynamically determine the shape of the crowns that will maximize the routing
  • Each power stripe has a set of
  • stacks 605 and 615 that may be obstacles to wiring on the layer.
  • stacks 605 and 615 may be obstacles to wiring on the layer.
  • wiring that leaves the LPDR 610 defined around one power stripe can run into a power via stack 615 of the other power stripe.
  • Figure 6 illustrates the merging of the two
  • LPDRs 610 and 620 to define a new LPDR 630.
  • the "merged" LPDR 630 is defined to
  • LPDRs are beneficial for particular multi-layer uses as well.
  • Figure 7 illustrates a multi-layer design layout or IC that utilizes LPDRs to define
  • Figure 7 shows a Layer N that has a horizontal global preferred direction and a Layer N+l
  • Layer N has a pre-designed circuit block 710 that
  • Layer N+l has an LPDR 720 that is positioned over the pre ⁇
  • This LPDR 720 has a horizontal local preferred direction in order
  • the LPD wiring model to dynamically define vias based on the particular design layout.
  • these embodiments select the shape of the via pads in the first and second
  • Figure 8 illustrates an example of using different via pad shapes between different
  • This example illustrates a perspective view of a
  • Layer N has a rectangular LPDR 835 with a diagonal local preferred
  • Layer N+l has a rectangular LPDR 805 with a horizontal local preferred direction
  • the first via is defined between the wiring area of
  • This first via has a square via pad 840 in the wiring
  • a second via is defined between
  • This second via has an octagonal via
  • a third via is
  • This third via has an
  • This tabulation provides a user with via pad options when optimizing
  • GUI incorporates an Auto-LPD Region Generator
  • An LPD design layout typically consists of pre-designed circuit blocks, LPDRs, pins,
  • Figure 9 presents a GUI of some embodiments of the invention for graphically presenting these elements in a design layout. This figure illustrates a
  • design window 900 that represents a third wiring layer that has a diagonal global preferred
  • design window 900 is a list of
  • a user can access menu options by performing a "clicking" operation while a cursor is
  • Another way for a user to access GUI menus is to perform a
  • Figure 9 also illustrates four LPDRS. Two of these LPDRs 930 and 935 have vertical
  • the other two LPDRs 940 and 945 have horizontal local preferred directions.
  • the GUI uses "directions arrows" to identify the GUI
  • the GUI also uses direction arrows
  • direction arrow 950 identifies the diagonal global preferred direction of the wiring layer in
  • GUI in some embodiments identifies any impermeable edges of the LPDRs. Impermeable
  • edges are identified by (1) placing an identifier (e.g. graphical or textual icon such as an "X") on the edge, or by (2) changing the attribute of the edge (dash, color, etc).
  • an identifier e.g. graphical or textual icon such as an "X”
  • the GUI design window 900 not only provides a visual representation of the design
  • embodiments identify design elements on other wiring layers. To distinguish these "other
  • embodiments use different coloring, shape, fill patterns, or boundary-line dashing to identify
  • Figure 10 illustrates an example of the visual representation of "other layer” design
  • Figure 10 illustrates a
  • design window 1000 representing a fourth wiring layer that has a vertical global preferred
  • This fourth wiring layer is above the third wiring layer previously illustrated in
  • third layer are represented by "dashed outlines" 1010 and 1015.
  • the outlines are “dashed” for
  • the "outlines" represent the relative location of IP block 910 and
  • LPDRs 1050 and 1060 are defined in design window 1000 to overlap the pre-designed circuit blocks on the lower layer. The benefits of defining LPDRs to
  • the GUI provides a user with precise tools to create and manipulate an LPD design
  • Figures 11A-11E illustrate the creation of LPDRs using an "LPDR
  • Figure HA illustrates a design window 1100 that has a Menu
  • the Menu Bar 1105 contains a few different menus than
  • the Tool Bar 1110 contains a few "docked"
  • menu items that are used frequently when designing layouts. These include, among other things
  • a search tool a zoom tool
  • an "insert Macro" tool a search tool, a zoom tool, and an "insert Macro" tool.
  • GUI can be configured to open the menu window via other input methods.
  • the user can open the LPDR menu window by navigating through specific
  • LPDR creation tool 1115 within the design window 1100 as illustrated in Figure 11B. This "LPDR creation tool” is particularly useful in designing LPDR octangles, which are LPDRs in
  • the LPDR creation tool can be used to create LPDRs in
  • an octangle represents a convex geometric shape in terms of eight values, x o,
  • horizontal lines are aligned with the x-axis
  • vertical lines are
  • the design layout are convex shapes, or can be decomposed into convex shapes, that have
  • Figure 11B illustrates an LPDR Creation Tool 1 115 that has eight half-planes; X L0 1110, y L0 1120, s L0 1130, t L0 1140, xm 1150, y H ⁇ 1160, s H ⁇ 1 170, and t HI 1180.
  • LPDRs that have various polygonal shapes.
  • the shape of a proposed LPDR is defined
  • Figure 11B shows a proposed LPDR 1125 shaped like a square as defined by the half-planes
  • the inner-most portions of the half-planes are the entire half-planes X O 1110, y L0 1120, X HJ
  • the half-planes are user-selectable and can be moved to define
  • Figure 11B illustrates a user selecting half plane y H1 1160
  • Figure 11D shows the proposed LPDR 1 125 in the shape of a 5-sided polygon
  • 11D also illustrates a user selecting half-planes s L0 1130, t L0 1140, and t H ⁇ 1180 with the
  • Figure HE shows the proposed LPDR 1125 in the shape of an irregular octagon, i.e.,
  • embodiments of the invention allow a user to "lock" the aspect ratio between any two or
  • locking provides a user with further flexibility in defining LPDRs.
  • the GUI in some embodiments
  • FIG. 11F illustrate a user moving the LPDR 1125 created in the previous example. Specifically,
  • Figure HE illustrates a user placing a cursor 1 135 over the surface of LPDR 1125
  • LPDR 1125 is
  • LPDR Modification Menu 1250 provides various menu options such as Duplicate LPD,
  • Some embodiments of the invention assign a "default" local preferred direction for an
  • the default local preferred direction to be assigned can be
  • the user can modify any LPDR's local preferred direction by
  • the user can move a particular LPDR up or
  • a user can also duplicate an LPDR by selecting the Duplicate LPD option in the
  • Modification Menu also provides a "Finish LPD" option. This option allows a user to
  • FIGS 13A and 13B illustrate how the GUI according to some embodiments of the
  • Figure 1 represents a wiring layer that has a diagonal global preferred direction.
  • FIG. 13A shows a user accessing an "Insert" drop down menu with a cursor 1345 and selecting an
  • the GUI can be
  • the LPDR shapes provided within the "Insert LPD" menu can be displayed along the
  • menu bar as illustrated in Figures 13C and 13D. Specifically, these figures also show a design window 1300 that has various LPDR-shapes "docked" onto the menu bar 1305. In this
  • a user places the cursor 1345 over the octagonal LPDR-shape, then "selects and
  • an octagonal-shaped LPDR 1320 is
  • Figure 13E shows a user placing a cursor 1345
  • the square LPDR-shape 1310 on the menu bar is shaded to
  • Figure 13F illustrates the expansion of an LPDR as the cursor 1345 is
  • the dashed regions represent intermediate stages of the expansion.
  • the dashed regions represent intermediate stages of the expansion.
  • One method would be to place a cursor over the vertex of two sides of a particular LPDR and perform a "select and
  • a cursor 1455 is placed over the upper-right corner vertex of LPDR 1410.
  • dashed-arrow next to cursor 1455 represents the user "clicking and dragging" the cursor 1455
  • LPDR 1410 is resized to be larger as
  • Another method to resize an LPDR is by "selecting and dragging" a boundary edge of
  • edges are "stretched” or “compacted” to conform with the movement of the particular
  • some embodiments of the invention allow a user to
  • Figures 14A and 14B illustrate a design window 1400 representing a
  • Figure 14A illustrates a cursor 1445 placed over the surface of LPDR 1405.
  • cursor 1445 small dashed-arrow next to cursor 1445 represents the user "clicking and dragging" the cursor
  • the directions of LPDRs are user-selectable and can be manipulated by various methods.
  • some embodiments of the invention provide a user with a "menu window" method
  • the “select and snap” method permits a
  • preferred directions "allowed” are in increments of 45° from a standard horizontal axis
  • a user's manipulation of a direction arrow using this "select and snap" method can be
  • some embodiments of the invention update the indication of any impermeable edges of the LPDRs within the design
  • LPDR 1415 are due to the diagonal preferred direction of the layer in design window 1400.
  • this figure shows two impermeable edge indicators 1435 added to the upper right
  • Figure 15A illustrates a user selecting a direction
  • GUI can be configured to open the menu window via other
  • the GUI in some embodiments
  • LPDRs 1540 and 1545 that have 0° local
  • This identification alerts the user to make changes to the layout to improve routabililty
  • Figure 15C illustrates a user selecting an impermeable boundary edge by
  • region 1530 The vertical arrow under the cursor represents the user
  • All impermeable boundary edges have at least two vertices that represent the end- points of the edge.
  • the user extended such a vertex of an impermeable
  • Figure 16A illustrates a user adding a vertex 1665 to impermeable
  • CD ⁇ .P0078 describes the routing tools that can route a layout with LPD's.
  • some embodiments might include a placer that computes placement
  • embodiments define a crown boundary between an LPDR with a Manhattan LPD (e.g., a

Abstract

Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools. An LPD wiring model allows at least one wiring layer (200) to have a set of regions (205, 210, 215) that each has a different preferred direction (-45°, 0°, 90°) than the particular wiring layer. In addition, each region (205, 210, 215) has a local preferred direction (-45°, 0°, 90°) that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Description

LOCAL PREFERRED DIRECTION ARCHITECTURE, TOOLS, AND APPARATUS
FIELD OF THE INVENTION
The invention is directed towards an apparatus for routing nets using a Local Preferred
Direction wiring model.
BACKGROUND OF THE INVENTION
An integrated circuit ("IC") is a semiconductor device that includes many electronic
components (e.g., transistors, resistors, diodes, etc.). These components are often
interconnected to form multiple circuit components (e.g., gates, cells, memory units,
arithmetic units, controllers, decoders, etc.) on the IC. An IC also includes multiple layers of
metal and/or polysilicon wiring that interconnect its electronic and circuit components. For
instance, many ICs are currently fabricated with five metal layers. In theory, the wiring on the
metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-
angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal
layer typically has one global preferred wiring direction, and the preferred direction alternates
between successive metal layers.
Many ICs use the Manhattan wiring model that specifies alternating layers of
horizontal and vertical preferred direction wiring. In this wiring model, the majority of the
wires can only make 90° turns. Occasional diagonal jogs are sometimes allowed on the
preferred horizontal and vertical layers. Standard routing algorithms heavily penalize these
diagonal jogs (i.e. assess proportionally high routing-costs), however, because they violate the
design rules of the Manhattan wiring model. Some have recently proposed ICs that use a
diagonal wiring model to provide design rules that do not penalize diagonal interconnect lines
(wiring). Interconnect lines are considered "diagonal" if they form an angle other than zero or ninety degrees with respect to the layout boundary of the IC. Typically however, diagonal
wiring consists of wires deposed at ±45 degrees.
Typical Manhattan and diagonal wiring models specify one preferred direction for
each wiring layer. Design difficulties arise when routing along a layer's preferred direction
because of obstacles on these wiring layers. For example, design layouts often contain circuit
components, pre-designed circuit blocks, and other obstacles to routing on a layer. Such
obstacles may cause regions on a layer to become essentially unusable for routing along the
layer's single preferred direction.
An example that shows obstacles that cause regions on a design layout to become
unusable for routing is illustrated in Figure 1. This figure shows two wiring layers that each
have two routing obstacles 115 and 120. One of the layers has a horizontal preferred
direction; the other layer has a diagonal preferred direction. The obstacles 115 and 120 cause
two regions 105 and 110 to become unusable for routing on both of these layers. Therefore,
both the Manhattan and diagonal wiring models typically waste routing resources on the
layers of a design layout.
Accordingly, a need exists for a wiring model that allows Manhattan and diagonal
wiring and recaptures the routing resources lost because of obstacles on a wiring layer.
SUMMARY OF THE INVENTION
Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring
model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring
model allows at least one wiring layer to have a set of regions that each have a different
preferred direction than the particular wiring layer. In addition, each region has a local
preferred direction that differs from the local preferred direction of at least one other region in
the set. Furthermore, at least two regions have two different polygonal shapes and no region
in the set encompasses another region in the set. Some embodiments also provide a Graphical
User Interface (GUI) that facilitates a visual presentation of an LPD design layout and
provides tools to create and manipulate LPD regions in a design layout.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features of the invention are set forth in the appended claims. For purposes
of explanation, however, several embodiments of the invention are set forth in the following
figures.
Figure 1 illustrates an example of regions essentially unusable for routing due to
obstacles on a typical Manhattan and diagonal wiring layer.
Figure 2 illustrates an example of a design layout based upon an LPD wiring model.
Figure 3 illustrates another example of a design layout based upon an LPD wiring
model.
Figure 4A illustrates a wiring layer with pre-designed circuit blocks.
Figure 4B illustrate the wiring layer of Figure 4A with LPD regions.
Figures 5A-5C illustrate LPD regions extended with crowns.
Figure 6 illustrates merging LPD regions to encompass adjacent power stripes.
Figure 7 illustrates defining horizontal tracks on a diagonal layer to traverse over a
pre-designed circuit block.
Figure 8 illustrates vias that have different via pad shapes according to some
embodiments of the invention.
Figure 9 illustrates a visual representation of a design layout using the Graphical User
Interface according to some embodiments of the invention.
Figure 10 illustrates the indication of LPD regions that overlap pre-designed circuit
blocks on a lower layer in a design window of a Graphical User Interface according to some
embodiments of the invention.
Figures 11A-11E illustrate a user creating an LPD region using an "LPDR Creation Tool" in a design window of the Graphical User Interface according to some embodiments of
the invention.
Figures HE and 11F illustrate a user moving an LPD region within a design window
of the Graphical User Interface according to some embodiments of the invention.
Figures 12A and 12B illustrate a user specifying a local preferred direction for an
LPD region in a design window of the Graphical User Interface according to some
embodiments of the invention.
Figures 13A and 13B illustrate a user creating an LPD region using a "select and
drop" method in a design window of the Graphical User Interface according to some
embodiments of the invention.
Figures 13C and 13D illustrate a user creating an LPD region using a "select and
drag" method in a design window of the Graphical User Interface according to some
embodiments of the invention.
Figures 13E and 13F illustrate a user creating an LPD region using a "select and
expand" method in a design window of the Graphical User Interface according to some
embodiments of the invention.
Figures 14A and 14B illustrate a user manipulating attributes of LPD regions in a
design window of the Graphical User Interface according to some embodiments of the
invention.
Figure 15A and 15B illustrate a user employing a "menu window" method to
manipulate the preferred direction of an LPD region in a design window of a Graphical User
Interface according to some embodiments of the invention.
Figures 15C and 15D illustrate a user "crowning" an LPD region in a design window of a Graphical User Interface according to some embodiments of the invention.
Figures 16A and 16B illustrate a user adding a vertex to an impermeable boundary
edge and "crowning" an LPD region in a design window of the Graphical User Interface
according to some embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
The invention is directed towards an apparatus for routing nets using a Local Preferred
Direction wiring model. In the following description, numerous details are set forth for
purpose of explanation. One of ordinary skill in the art will realize, however, that the
invention may be practiced without the use of these specific details. In some instances, well-
known structures and devices are shown in block diagram form to simplify the description of
the invention.
Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring
model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring
model allows at least one wiring layer to have a set of regions that each have a different
preferred direction than the particular wiring layer. In addition, each region has a local
preferred direction that differs from the local preferred direction of at least one other region in
the set. Furthermore, at least two regions have two different polygonal shapes and no region
in the set encompasses another region in the set. Some embodiments also provide a Graphical
User Interface (GUI) that facilitates a visual presentation of an LPD design layout and
provides tools to create and manipulate LPD regions in a design layout.
Several features of the LPD Architecture will be discussed below. Section II describes
some examples of the LPD Architecture and Section III describes a Graphic User Interface
(GUI) for an EDA tool that employs an LPD wiring model. Before describing the examples of
the LPD Architecture and the GUI, however, Section I describes an overview of the LPD
wiring model.
I. OVERVIEW OF LOCAL PREFERRED DIRECTION WIRING MODEL
The LPD wiring model of some embodiments allows for the creation of routes that have edges in the Manhattan or diagonal direction. A Manhattan edge is either horizontal (0°)
or vertical (90°) with respect to one of the coordinate axes of the layout or IC. Conversely, a
diagonal edge forms angles other than 0° or 90°. A diagonal edge typically forms a 45° angle
with respect to the layout's or ICs coordinate axes. The coordinate axes are often parallel
with the layout's boundary, the boundary of the layout's expected IC, or both.
Given a design layout or IC with several wiring layers, some embodiments describe
the LPD wiring model of the layout or IC in terms of (1) several wiring layers, (2) a global
preferred direction DL for each layer L, and (3) a potentially empty set of LPD regions for
each wiring layer L. Some embodiments define a "preferred" direction as the direction that a
majority of the wires are laid out in a region. Some embodiments further quantify this amount
in terms of percentages or amount of the wiring. For example, some embodiments define the
preferred direction of a layer as the direction for at least 50% of the wires (also called
interconnect lines or route segments) on the layer. Other embodiments define the preferred
direction of a layer as the direction for at least 1000 wires on the layer.
On a particular layer, a region is called an LPD region (or an LPDR) when the region
has a local preferred wiring direction that is different than the global preferred wiring direction
of the particular layer. Some embodiments impose several consistency requirements on an
LPDR description. For instance, some embodiments require each LPDR to be entirely within
the chip area. In some embodiments, all LPDRs on a given layer intersect only at their
boundary (i.e., no overlaps). In addition, some embodiments require that all LPDRs are non-
degenerate (contain at least one interior point). π. LPD ARCHITECTURE
As previously mentioned, an LPD wiring model allows at least one wiring layer to
have several different local preferred directions in several different regions of the wiring layer.
Figure 2 illustrates an example of such a wiring layer in an IC or a design layout. This wiring
layer has LPDRs that have several different convex shapes and local preferred directions
according to some embodiments of the invention. This example shows a wiring layer 200 that
has a 45° global preferred direction. On this layer 200 are an octagonal LPDR 205 that has a -
45° local preferred direction, an octagonal LPDR 210 that has a horizontal local preferred
direction, and a rectangular LPDR 215 that has a vertical local preferred direction.
Figure 3 illustrates another example of another such wiring layer in an IC or a design
layout. This wiring layer has LPD regions that have several different convex shapes according
to some embodiments of the invention. This example shows a wiring layer 300 that has a
vertical global preferred direction. This layer 300 has four LPDRs that have different convex
shapes and different local preferred directions. In the center of layer 300 is an octagonal
LPDR 305 with a
-45° local preferred direction. Adjacent to the lower-left side of region 305 is a rectangular
LPDR 310 with a 45° local preferred direction. Adjacent to the upper-left side of region 305
is a hexagonal LPDR 315 with a 60° local preferred direction. Adjacent to the right side of
region 305 is a square LPDR 320 with a horizontal local preferred direction.
The examples illustrated above in Figures 2 and 3 demonstrate that an LPD wiring
model allows a wiring layer to have several regions with different convex polygonal shapes
and different local preferred directions. These examples however present simple uses of the
LPD wiring model in a design layout or an IC. The examples do not illustrate any macros or other obstacles to the wiring on a layer. Macros are pre-designed complex circuit blocks used
in a layout or an IC. Examples of such blocks include IP blocks, RAM cells, and Power Via
Arrays. As previously mentioned, these and other obstacles to wiring may cause regions on a
wiring layer to become essentially unusable for routing. One of the advantages of the LPD
wiring model, however, is that it recovers routing resources normally lost because of macros
and other obstacles on a wiring layer.
Figures 4A and 4B provide examples that illustrate this particular advantage of the
LPD wiring model. Specifically, Figure 4A illustrates a wiring layer 400 that has a diagonal
global preferred direction. This wiring layer includes a column of power via arrays (power
stripe) 405, an IP block 410, a set of memory cells 415, and two pins 420 and 425. Also
shown on this layer is diagonal wiring represented by dotted lines. The power stripe 405, IP
block 410, and the set of memory cells 415 are all obstacles to wiring on the wiring layer.
These obstacles may present routing difficulties as shown in Figure 4A. A problem arises
when pins 420 and 425 need to be connected to each other or to other pins because the
diagonal wiring that connects to pin 420 is obstructed by the power via arrays 405.
Furthermore, the diagonal wiring that connects to pin 425 is obstructed by the IP block 410.
To solve these routing problems, some embodiments define LPDRs about these
obstacles that have local preferred directions running parallel to the edges of the obstacles.
Figure 4B illustrates examples of such LPDRs. An LPDR 430 that has a horizontal local
preferred direction is defined to encompass the power via arrays 405. As an alternative, some
embodiments define individual LPDRs between the power via arrays instead of encompassing
them. In either case, the horizontal direction of the LPDRs allows wiring to route between the
power via arrays 405. This figure also shows three LPDRs 440 that have vertical local preferred directions
defined between the RAM blocks 415. In addition, an LPDR 450 that has a vertical local
preferred direction is defined between the right side of the IP block 410 and the right
boundary of the wiring layer, and an LPDR 460 that has a horizontal local preferred direction
is defined between the topside of the IP block 410 and the top boundary of the wiring layer.
The boundary edge between LPDR 450 and LPDR 460 is defined as a 45° diagonal line to
increase the capacity of the wiring between two such regions. Boundary edges as such are
called "crowns", the advantages of which will be further described below.
The LPDRs illustrated in Figure 4B allow wiring that was previously obstructed to
now traverse around the obstacles by routing through these LPDRs along their local preferred
directions. For instance, as shown in Figure 4B, pins 420 and 425 can now be connected
through a set of interconnect lines that traverse along the global 45° direction, traverse through
the LPDR 430 in the horizontal direction, traverse again along the global 45° direction, and
then traverse through the LPDR 460 in the horizontal direction.
A. Crowns
Some embodiments define a boundary edge between two regions as an "impermeable
edge" when the edge runs parallel to either one of the local preferred directions of the two
regions sharing the respective boundary edge. These boundary edges are considered
impermeable because of geometric design constraints. For example, two sets of wires that run
parallel to each other do not typically intersect. As such, the wiring in two regions that share
an impermeable boundary edge will be impeded from intersecting at that edge.
In order to solve this potential routing problem, some embodiments of the invention
"extend" these impermeable boundary edges with "crowns." A "crown" is an extension of an LPDR at a boundary between two regions. In some embodiments, a crown boundary is
defined to not be parallel to either of the local preferred directions of the two regions sharing
the crown boundary. These crowns thus form boundary edges that allow the intersection of
wiring directed along the preferred directions of the regions sharing the boundary edge.
Figures 5A-5C illustrate a detailed example of extending boundary edges of LPDRs
with "crowns". These figures illustrate a wiring layer 500 that has a horizontal global
preferred direction. Positioned in the center of this layer are three pre-designed circuit blocks
505, 510, and 515. In addition, two channels 580 and 590 are located between the blocks 505
and 510 and blocks 510 and 515, respectively. These channels 580 and 590 are essentially
unusable for routing in the horizontal direction of layer 500 because geometric constraints
prohibit such wiring to enter or exit from the channels. In order to effectively utilize these
channels, some embodiments of the invention replace the channels 580 and 590 with LPDRs
520 and 530 that have vertical local preferred directions as illustrated in Figure 5B. Defining
the LPDRs 520 and 530 in this manner, however, would create impermeable boundary edges
at the upper and lower boundary edges of LPDRs 520 and 530 (represented by dashed lines)
in some embodiments. These boundary edges are defined as impermeable because they run
parallel to the preferred horizontal direction of the layer 500.
To avoid creating impermeable boundary edges, some embodiments of the invention
add "crowns" to the LPDRs 520 and 530 as shown in Figure 5C. Specifically, Figure 5C
illustrates an example of two triangular crowns 545 and 555 created to extend LPDR 520.
This figure also illustrates two triangular crowns 565 and 575 created to extend LPDR 530.
Crowns 545 and 555 are shaped differently than crowns 565 and 575. Crowns 545 and 555
are in the shape of an isosceles triangle; crowns 565 and 575 are in the shape of a right triangle. Both shapes of crowns, however, form boundary edges that intersect with the
horizontal wiring from layer 500. Thus, the horizontal wiring is able to route into and out of
LPDRs 520 and 530. The previously "un-routable" wiring space of the channels 580 and 590
is effectively utilized for wiring on layer 500.
Crowns can be defined to have various shapes. Typically however crowns are
triangular. The two shapes of crowns previously presented in Figure 5C differ not only in
form but function as well. For example, the crowns shaped like an isosceles triangle forrn two
boundary edges that intersect with the horizontal wiring of the layer. These edges allow
wiring directed from both the left and the right of the crown to route through the LPDR. On
the other hand, crowns shaped like a right triangle typically form one permeable edge. This
edge typically allows wiring to route through an LPDR from either the left or from the right
of the crown. This one edge however is typically longer and thus intersects more wiring when
compared to a single edge of the isosceles shaped crown. Accordingly, some embodiments of
the invention dynamically determine the shape of the crowns that will maximize the routing
through the respective region in a particular design layout.
B. Merging LPD Regions
Some embodiments of the invention merge adjacent LPDRs that have the same local
preferred direction to improve routability through the regions. Merging is particularly useful
when individual LPDRs are defined around adjacent power stripes. For example, Figure 6
illustrates two LPDRs 610 and 620 that are defined around two different power stripes. Both
of these LPDRs have a horizontal local preferred direction. Each power stripe has a set of
power via stacks 605 and 615 that may be obstacles to wiring on the layer. For example, as
shown in this figure, wiring that leaves the LPDR 610 defined around one power stripe can run into a power via stack 615 of the other power stripe.
To solve this potential routing problem, Figure 6 illustrates the merging of the two
LPDRs 610 and 620 to define a new LPDR 630. The "merged" LPDR 630 is defined to
encompass both power stripes and has the same horizontal local preferred direction as the
replaced LPDRs 610 and 620. This merging allows the wiring to traverse efficiently across the
region underneath the power stripes without the power via stack obstruction that existed
when the two LPDRs 610 and 620 were separate.
This "merging" feature is not restricted for use with power stripes. Some
embodiments of the invention merge adjacent LPDRs that have the same local preferred
wiring direction whenever doing so would improve routing efficiency. In addition, some
embodiments avoid having to merge adjacent LPDRs altogether by initially defining a single
LPDR to encompass adjacent regions that require the same local preferred direction.
C. Over-Macro Traverse
The previous examples demonstrate the beneficial use of LPDRs on a single layer of a
design layout or an IC. LPDRs are beneficial for particular multi-layer uses as well. For
example, Figure 7 illustrates a multi-layer design layout or IC that utilizes LPDRs to define
horizontal tracks over a lower-layer pre-designed circuit block (e.g. an IP block). Specifically,
Figure 7 shows a Layer N that has a horizontal global preferred direction and a Layer N+l
that has a 45° global preferred direction. Layer N has a pre-designed circuit block 710 that
prefers horizontal wiring. Layer N+l has an LPDR 720 that is positioned over the pre¬
designed circuit block 710. This LPDR 720 has a horizontal local preferred direction in order
to increase the potential locations for placing vias between the pre-designed circuit block 710
and the wiring of Layer N+l . D. Vias That Have Differently-Shaped Via Pads
Another multi-layer use of LPDRs is in the definition of vias. Some embodiments use
the LPD wiring model to dynamically define vias based on the particular design layout.
Specifically, when defining a via between a first region of a first layer and a second region of a
second layer, these embodiments select the shape of the via pads in the first and second
regions based upon the preferred direction of both regions. This dynamic selection of the via
pad shapes allows these embodiments to use vias that are optimized for connecting wire
segments along different directions.
Figure 8 illustrates an example of using different via pad shapes between different
regions of two wiring layers in a layout. This example illustrates a perspective view of a
multi-layer design layout that has a wiring layer N with a vertical global preferred direction
and a wiring layer N+l with a diagonal global preferred direction. A directional -axis indicator
is provided in Figure 8 to identify the wiring directions according to this perspective view.
In Figure 8, Layer N has a rectangular LPDR 835 with a diagonal local preferred
direction. Layer N+l has a rectangular LPDR 805 with a horizontal local preferred direction
and an octagonal LPDR 815 with a vertical local preferred direction. This example also shows
three vias between Layer N and Layer N+l . The first via is defined between the wiring area of
Layer N and LPDR 805 on Layer N+l. This first via has a square via pad 840 in the wiring
area of Layer N and a rectangular via pad 810 in LPDR 805. A second via is defined between
LPDR 835 on Layer N and LPDR 805 on Layer N+l. This second via has an octagonal via
pad 850 in LPDR region 835 and a rectangular via pad 820 in LPDR 805. A third via is
defined between LPDR 835 on Layer N and LPDR 815 on Layer N+l. This third via has an
octagonal via pad 860 in LPDR 835 and a rectangular via pad 830 in LPDR 815. The example above suggests just one of many combinations of via-pad-pairs between
Layers N and N+l. Furthermore, there are a multitude of other LPDR configurations that can
be used when designing a multi-layer IC. Accordingly, some embodiments of the invention
tabulate the possible permutations of via-pad pairs to account for these variations in design
layout configurations. This tabulation provides a user with via pad options when optimizing
vias between regions that have different local preferred directions.
m. GRAPHICAL USER INTERFACE
Some embodiments of the invention provide a GUI to allow the user to view an LPD
layout and/or create and manipulate LPDRs on a layout. The GUI of some embodiments (1)
saves/loads/deletes LPDRs, (2) displays current LPDRs with their preferred directions and
highlighted impermeable edges, (3) adds/manipulates the shapes of LPDRs and their
respective local preferred directions, (4) snaps adjacent LPD regions to remove unwanted
gaps, and (5) runs a consistency checker that highlights overlaps and degenerate regions of a
design layout. In other embodiments, the GUI incorporates an Auto-LPD Region Generator
that defines LPDRs to increase a design's routing resources, without forcing the user to create
LPR regions manually.
The GUI's visual representation of a LPD design layout according to some
embodiments of the invention is first described below. This discussion is then followed by a
discussion of the GUI's creation and manipulation of LPDRs according to some embodiments
of the invention.
A. Visual Representation of an LPD Design Layout
An LPD design layout typically consists of pre-designed circuit blocks, LPDRs, pins,
wiring, and other layout elements. Figure 9 presents a GUI of some embodiments of the invention for graphically presenting these elements in a design layout. This figure illustrates a
design window 900 that represents a third wiring layer that has a diagonal global preferred
direction. Within this design window 900 are three pre-designed circuit blocks: a power stripe
905, an IP block 910, and a set of RAMS 915. At the top of design window 900, is a list of
"drop-down menus" that provide a user with access to some of the features of the GUI
itemized above, such as loading, deleting, and creating layouts with LPDRs. In this example,
there are menus for "File", "Edit", "View", "Insert", and "Tools". Other embodiments
however provide different and/or additional menus.
A user can access menu options by performing a "clicking" operation while a cursor is
over the desired menu choice. Another way for a user to access GUI menus is to perform a
"right-clicking" operation while a cursor is within the design window. For example, Figure 9
illustrates a user accessing a "preferred direction menu" 970 by performing a "right-clicking"
operation while a cursor 960 is within design window 900.
Figure 9 also illustrates four LPDRS. Two of these LPDRs 930 and 935 have vertical
local preferred directions. The other two LPDRs 940 and 945 have horizontal local preferred
directions. As this example illustrates, the GUI uses "directions arrows" to identify the
preferred directions of any LPDRs in the design layout. The GUI also uses direction arrows
to identify the preferred direction of the wiring layer in the design window. For example,
direction arrow 950 identifies the diagonal global preferred direction of the wiring layer in
design window 900.
In addition to identifying the preferred directions of LPDRs in the design window, the
GUI in some embodiments identifies any impermeable edges of the LPDRs. Impermeable
edges are identified by (1) placing an identifier (e.g. graphical or textual icon such as an "X") on the edge, or by (2) changing the attribute of the edge (dash, color, etc). In this example, an
"X" icon 985 is superimposed on an impermeable boundary edge of LPDR 940. Identification
of impermeable edges alerts the user to make changes to the layout to improve routabililty
through the respective boundary edges (i.e., by adding "crowns").
The GUI design window 900 not only provides a visual representation of the design
elements on an "active" wiring layer (the layer currently viewed by the user), but some
embodiments identify design elements on other wiring layers. To distinguish these "other
layer" design elements from the design elements on the active layer, the GUI provides
differing visual representations of these "other layer" design elements. For instance, some
embodiments use different coloring, shape, fill patterns, or boundary-line dashing to identify
design elements that are on a layer other than the active layer.
Figure 10 illustrates an example of the visual representation of "other layer" design
elements according to some embodiments of the GUI. Specifically, Figure 10 illustrates a
design window 1000 representing a fourth wiring layer that has a vertical global preferred
direction. This fourth wiring layer is above the third wiring layer previously illustrated in
Figure 9. As shown in design window 1000, the pre-designed circuit blocks on the lower
third layer are represented by "dashed outlines" 1010 and 1015. The outlines are "dashed" for
illustrative purposes in this example only, as most embodiments of the invention typically
use different colored regions to represent other-layer pre-designed circuit blocks.
In this example, the "outlines" represent the relative location of IP block 910 and
RAMS 915 on the lower third wiring layer. The outlining of lower-level pre-defined circuit
blocks enables a user to accurately define LPDRs on an active layer to overlap the pre-defined
circuit blocks. For example, LPDRs 1050 and 1060 are defined in design window 1000 to overlap the pre-designed circuit blocks on the lower layer. The benefits of defining LPDRs to
overlap pre-defined circuit blocks on a lower level were previously discussed in Section II. C.
B. LPD Region Creation and Manipulation
The GUI's creation and manipulation of LPDRs according to some embodiments of
the invention is first described below. This discussion is then followed by a discussion of
alternate methods of creating and manipulating LPDRs according to other embodiments of the
invention.
1. LPDR creation and manipulation
The GUI provides a user with precise tools to create and manipulate an LPD design
layout. For example, Figures 11A-11E illustrate the creation of LPDRs using an "LPDR
Creation Tool". Specifically, Figure HA illustrates a design window 1100 that has a Menu
Bar 1105 and a Tool Bar 1110. The Menu Bar 1105 contains a few different menus than
previously discussed above in Section III. A.. The Tool Bar 1110 contains a few "docked"
menu items that are used frequently when designing layouts. These include, among other
things, a search tool, a zoom tool, and an "insert Macro" tool.
In order to create an LPDR, a user would first have to access an "LPR menu-
window". Typically, a user opens this LPDR menu window by performing a "right-clicking"
operation with a pointing device as previously discussed above with reference to Figure 9.
However, the GUI can be configured to open the menu window via other input methods.
Additionally, the user can open the LPDR menu window by navigating through specific
options in the menu bar. In this example, a user opens an "LPDR menu window" 1120 and
selects an "Add LPD" option with a cursor 1 135. This prompts the GUI to display an
"LPDR creation tool" 1115 within the design window 1100 as illustrated in Figure 11B. This "LPDR creation tool" is particularly useful in designing LPDR octangles, which are LPDRs in
the shape of an octagon. However, the LPDR creation tool can be used to create LPDRs in
the shape of other geometries as well.
An octangle in some embodiments is a data structure that is useful for design layouts
that have items with horizontal, vertical, and/or ±45° directions. Specifically, in these
embodiments, an octangle represents a convex geometric shape in terms of eight values, x o,
YLO> S LO> tL0, XHI, yHi, sm> and tHι. These eight values define eight half-planes in two
coordinate systems, where one coordinate system is a Manhattan coordinate system that is
formed by an x-axis and a y-axis, and the other coordinate system is a 45°-rotated coordinate
system that is formed by an s-axis and a t-axis. The s-axis is at a 45° counter-clockwise
rotation from the x-axis, while the t-axis is at a 45° clockwise rotation from the x-axis. In the
layouts of some embodiments, horizontal lines are aligned with the x-axis, vertical lines are
aligned with the y-axis, 45° diagonal lines are aligned with the s-axis, and -45° diagonal lines
are aligned with the t-axis.
Octangles are further described in U.S.. Patent Application 10/443,595, entitled
"Method and Apparatus for Representing Items in a Design Layout," which published as
U.S. Published Patent Application 2004-0225983A1. This patent application is incorporated
herein by reference. In the description below, both the wiring and non-wiring geometries of
the design layout are convex shapes, or can be decomposed into convex shapes, that have
horizontal, vertical, and ±45° sides. One of ordinary skill will realize, however, that some
embodiments might use the octangle data structure in cases where the wiring or non-wiring
geometries are more restricted.
Figure 11B illustrates an LPDR Creation Tool 1 115 that has eight half-planes; XL0 1110, yL0 1120, sL0 1130, tL0 1140, xm 1150, yHι 1160, sHι 1 170, and tHI 1180. The four s
and t half-planes initially form a square that circumscribes a square formed by the four x and
y half planes. However, all eight of these half-planes are user selectable and can be moved to
create LPDRs that have various polygonal shapes. The shape of a proposed LPDR is defined
as the closed surface formed by the inner-most portions of the half-planes. For example,
Figure 11B shows a proposed LPDR 1125 shaped like a square as defined by the half-planes
XLO 1 1 10, yL0 120, xHι 1150, and yHI 1160 of LPDR Creation Tool 1115. In this example,
the inner-most portions of the half-planes are the entire half-planes X O 1110, yL0 1120, XHJ
1150, and yH1 1160. All the portions of the remaining half planes, sLo 1130, tL0 1140, sH1
1170, and tHι 1180 are on the exterior of the default LPDR Creation Tool 1115. To aid in
distinguishing the inner and exterior portions of half-planes, some embodiments of the
invention use bolded solid-lines to represent the inner-most portions and dashed-lines to
represent the exterior portions of the half-planes.
As mentioned above, the half-planes are user-selectable and can be moved to define
the shape of a proposed LPDR. Figure 11B illustrates a user selecting half plane yH1 1160
with a cursor 1135 and moving it downward. As a result, the proposed LPDR 1125 is re¬
defined to form a rectangle as shown in Figure 11C. This figure also illustrates that the
exterior half-planes, sLo 1130, tLO 1140, sHι 1170, and tHι 1180 are redefined to maintain the
form of a square that circumscribes the proposed LPDR 1125. The exterior half-planes
maintain the form of a circumscribing square until they are moved inward. This inward
movement of an exterior half-plane is also illustrated in Figure 11C by a user selecting half
plane sHι 1170 with the cursor 1135 and moving it inward. The resulting re-definition of the
proposed LPDR 1125 is illustrated in Figure 11D. Figure 11D shows the proposed LPDR 1 125 in the shape of a 5-sided polygon
formed by the interior portions of half-planes x 0, 11 10, yL0 1120, xHι 1150, sH1 1170 and
ym 1160. The interior portion of SHI 1170 and the exterior portions of XHI 1150 and yHι 1160
are represented by the appropriate bolded solid-lines and dashed lines respectively. Figure
11D also illustrates a user selecting half-planes sL0 1130, tL0 1140, and tHι 1180 with the
cursor 1135 and moving them inward. The resulting re-definition of the proposed LPDR 1125
is illustrated in Figure HE.
Figure HE shows the proposed LPDR 1125 in the shape of an irregular octagon, i.e.,
an octagon that has sides with unequal length. This is a result of the independent and
divergent movement of the half-planes when forming the proposed LPDR 1125. This
independent half-plane movement affords a user the flexibility to create unique LPDRs that
have shapes that are precisely defined for a particular design layout. However, some
embodiments of the invention allow a user to "lock" the aspect ratio between any two or
more half-planes. As such, movement of a "locked" half-plane will also move any other
"locked" half-planes by an amount proportional to their respective aspect ratios. This
"locking" feature provides a user with further flexibility in defining LPDRs.
Once an LPDR is created in the design window, the GUI in some embodiments
presents a user with features to manipulate the attributes of an LPDR. Some of these features
include (1) resizing the LPDR, (2) moving the LPDR, (3) assigning/modifying the LPDR's
local preferred direction, (4) changing the LPDR's layer designation, and (5) duplicating the
LPDR. The resizing and moving features are typically implemented by "select and drag"
operations with a cursor. However, the remaining features are typically implemented by
selecting the particular option in an LPDR Modification Menu. These modification features of the GUI according to some embodiments of the invention will be described more
thoroughly below.
To resize an LPDR, a user would move a particular half-plane as described above with
reference to Figures HB-llD. This is performed by "selecting and dragging" a particular
half-plane to a desired location within the design window. Also, as mentioned above, the user
has the option to "lock" the aspect ratio between any two or more half plane pairs when
resizing LPDRs.
To move an LPDR, the user would place a cursor over the surface of a particular
LPDR and perform a "select and drag" operation along a desired direction. Figures HE and
11F illustrate a user moving the LPDR 1125 created in the previous example. Specifically,
Figure HE illustrates a user placing a cursor 1 135 over the surface of LPDR 1125 and
moving it diagonally up and to the left in design window 1100. As a result, LPDR 1125 is
moved to an appropriate location within design window 1100 as shown in Figure HF.
To assign/modify the LPDR's local preferred direction, change the LPDR's layer
designation, and/or duplicate the LPDR, the user would access an LPDR Modification Menu
as illustrated in Figure 12A. In this figure, a user opens an LPDR Modification Menu 1250
by placing a cursor 1235 over LPDR 1225 an performing a "right click" operation. This
LPDR Modification Menu 1250 provides various menu options such as Duplicate LPD,
Finish LPD, Layer UP Down, and LPD Direction. These menu option are "expandable" in
some embodiments of the invention, meaning that selecting a particular menu option will
expand the menu to provide further options. In this example, a user selects and expands the
LPD Direction menu option, and then selects a "Vertical" local preferred direction for LPDR
1225. As a result, some embodiments of the invention place vertical direction arrows within LPDR 1225 as illustrated in Figure 12B.
Some embodiments of the invention assign a "default" local preferred direction for an
LPDR when it is first created. The default local preferred direction to be assigned can be
previously specified by the user. Nevertheless, in cases where an LPDR was assigned a
default local preferred direction, the user can modify any LPDR's local preferred direction by
using the same method as described above for assigning the LPD.
To change the LPDR's layer designation, the user would select the particular option
from the LPDR Modification Menu. For example, the user can move a particular LPDR up or
down a layer by selecting the "Layer Up" or "Layer Down" option in the LPDR
Modification Menu 1250 previously referred to in Figure 12A. In addition, the user can also
move an LPDR to any specific layer by selecting the expandable "Layer" option provided in
the LPDR Modification Menu. As a result, the GUI in some embodiments of the invention
will change the coloring of the LPDR to indicate a specific layer designation.
A user can also duplicate an LPDR by selecting the Duplicate LPD option in the
LPDR Modification Menu. Doing so will prompt the GUI to create an LPDR in the design
window that has the same attributes as the LPDR selected for duplication (i.e. same shape,
local preferred direction, and layer designation). As previously discussed, the LPDR
Modification Menu also provides a "Finish LPD" option. This option allows a user to
finalize the creation/definition of an LPDR. As a result, some embodiments of the invention
remove the half-planes of the LPDR Creation Tool so that the particular LPDR cannot be
inadvertently resized. Other embodiments of the invention also "freeze" the LPDR in its
particular location in the design layout so that the particular LPDR cannot be inadvertently
moved. However, other embodiments of the invention still allow a user to modify the attributes of a "finalized" LPDR. An example of a 'finalized" LPDR 1225 with the LPDR
Creation Tool removed is illustrated in Figure 12B.
2. Alternate methods of LPDR creation and manipulation
The creation and manipulation of LPDR using the GUI of some embodiments of the
invention was discussed above. However, these aforementioned embodiments presented only
a few of the many ways to create and modify an LPDR using the GUI of the present
invention. Various other methods of other embodiments of the invention are described below.
In addition, another feature of the GUI called "crowning" will be introduced.
Figures 13A and 13B illustrate how the GUI according to some embodiments of the
invention enables a user to create LPDRs. These figures illustrate a design window 1300 that
represents a wiring layer that has a diagonal global preferred direction. Specifically, Figure
13A shows a user accessing an "Insert" drop down menu with a cursor 1345 and selecting an
LPDR shape. As a result, an octagonal LPDR 1310 that has a horizontal local preferred
direction is dropped into the design window 1300 as shown in Figure 13B. In this example, a
default size and a default horizontal local preferred direction was specified for LPDR 1310.
Other embodiments specify different default sizes and local preferred directions for LPDRs
that are dropped into the design window. Nevertheless, both these attributes of an LPDR can
be manipulated as will be described further below.
A user can also create LPDRs according to other embodiments of the invention by
selecting and dragging a desired LPDR shape into the design window. The GUI can be
configured to "dock" any menu options within a drop down menu onto the "menu bar". As
such, the LPDR shapes provided within the "Insert LPD" menu can be displayed along the
menu bar as illustrated in Figures 13C and 13D. Specifically, these figures also show a design window 1300 that has various LPDR-shapes "docked" onto the menu bar 1305. In this
example, a user places the cursor 1345 over the octagonal LPDR-shape, then "selects and
drags" the shape into the design window. As a result, an octagonal-shaped LPDR 1320 is
created in design window 1300.
Another method of creating an LPDR according to some embodiments of the invention
is called the "select and expand" method. In this method, after selecting a desired LPDR, a
user can specify an exact location and size of an LPDR to be created. Figures 13E and 13F
illustrate a user creating an LPDR using the select and expand method according to some
embodiments of the invention. Specifically, Figure 13E shows a user placing a cursor 1345
over a desired location to create an LPDR within the design window 1300 after previously
selecting a square LPDR shape. The square LPDR-shape 1310 on the menu bar is shaded to
indicate the user's selection. The small dashed-arrow next to cursor 1345 represents the user
"clicking and dragging" the cursor 1345 up and to the left in order to "expand" an LPDR. As a
result, an LPDR 1330 is created as shown in Figure 13F.
Specifically, Figure 13F illustrates the expansion of an LPDR as the cursor 1345 is
directed radially outward from the desired location where the user started the click and drag
operation. The dashed regions represent intermediate stages of the expansion. In this example,
the starting location of the click and drag operation specifies a corner vertex of the "expanded"
LPDR 1330. However, in other embodiments the starting location of the click and drag
operation specifies the center of an expanded LPDR.
Once an LPDR is created in the design window, the GUI presents the user with
different ways to manipulate the attributes of an LPDR. Some embodiments of the invention
allow a user to resize an LPDR region within the design window. One method would be to place a cursor over the vertex of two sides of a particular LPDR and perform a "select and
drag" operation directed radially outward/inward from the LPDR. Referring again to Figure
14A, a cursor 1455 is placed over the upper-right corner vertex of LPDR 1410. The small
dashed-arrow next to cursor 1455 represents the user "clicking and dragging" the cursor 1455
along a 45° direction (radially outward. As a result, LPDR 1410 is resized to be larger as
illustrated in Figure 14B. Typically, when resizing an LPDR by moving a vertex, the aspect
ratio of the sides of the LPDR is maintained as this example demonstrates.
Another method to resize an LPDR is by "selecting and dragging" a boundary edge of
a particular LPDR. This method is performed the same as described above except a user
selects a boundary edge of an LPDR instead of a vertex. However, these methods typically
provide different results as the aspect ratios of the sides of the LPDR are not usually
maintained when resizing an LPDR by moving a boundary edge. Instead, adjoining boundary
edges are "stretched" or "compacted" to conform with the movement of the particular
boundary edge.
In addition to re-sizing an LPDR, some embodiments of the invention allow a user to
move an LPD region within the design window. To do so, a user would place a cursor over
the surface of a particular LPDR and perform a "select and drag" operation along a desired
direction. Specifically, Figures 14A and 14B illustrate a design window 1400 representing a
wiring layer that has a diagonal global preferred direction. Within the design window 1400 are
three LPDRs 1405, 1410, and 1415 that have various convex shapes and local preferred
directions. Figure 14A illustrates a cursor 1445 placed over the surface of LPDR 1405. The
small dashed-arrow next to cursor 1445 represents the user "clicking and dragging" the cursor
1445 to the right. As a result, LPDR 1405 is moved to the right along a horizontal direction as illustrated in Figure 14B.
Another attribute of LPDRs that the GUI of some embodiments can manipulate is the
local preferred direction of LPDRs. In some embodiments, the direction arrows that represent
the directions of LPDRs are user-selectable and can be manipulated by various methods. For
example, some embodiments of the invention provide a user with a "menu window" method
to manipulate a selected direction arrow by choosing a particular direction from a menu
widow that lists typical preferred directions. Alternatively, a "select and drag" method
permits a user to select a particular direction arrow with a cursor and then "drag" the direction
arrow in a circular motion to arrive at any desired position. A variation of this "select and
drag" method is called the "select and snap" method. The "select and snap" method permits a
user to manipulate a direction arrow in the same way as the "select and drag" method except
that a selected direction arrow "snaps" progressively through allowed preferred directions
when dragged in a circular motion (i.e. from 0°, 45°, 90°, 135°, etc.). Typically, the specific
preferred directions "allowed" are in increments of 45° from a standard horizontal axis,
however some embodiments of the invention specify the "allowed" preferred directions
according to other degree increments.
A user's manipulation of a direction arrow using this "select and snap" method can be
seen by referring again to Figures 14A and 14B. These figures illustrate a cursor 1465
pointing to a direction arrow 1460 of LPDR 1415. The small dashed-arrow under the cursor
represents the user "dragging" the cursor 1445 clockwise/downward after selecting the
direction arrow 1460. As a result, the selected direction arrow 1460 is "snapped" from a
horizontal direction to a -45° direction as illustrated in Figure 14B.
As a result of a change to a region's preferred direction, some embodiments of the invention update the indication of any impermeable edges of the LPDRs within the design
window. As shown in Figure 14A, four impermeable edge indicators 1425 are superimposed
on the respective impermeable edges of LPDR 1415. Specifically, the impermeable edges
along the top and bottom of LPDR 1415 are due to the LPDR's horizontal local preferred
direction. When the local preferred direction of LPDR 1415 is changed to a -45° direction as
illustrated in Figure 14B, these two upper and lower edge indicators 1425 are removed.
However, the other two indicators 1425 remain as they represent the impermeable edges of
LPDR 1415 are due to the diagonal preferred direction of the layer in design window 1400. In
addition, this figure shows two impermeable edge indicators 1435 added to the upper right
and lower left edges of LPDR 1415 as a result of the changed -45° local preferred direction of
the LPDR 1415.
The alternate "menu window" method of manipulating the preferred direction of a
region or layer as opposed to the previously described "select and snap" method is illustrated
in Figures 15A and 15B. Specifically, Figure 15A illustrates a user selecting a direction
arrow by pointing a cursor 1560 at a direction arrow 1550 and then using a pointing device to
open a menu window. Typically, a user opens this menu window by "right-clicking" a
pointing device. However, the GUI can be configured to open the menu window via other
input methods. In this example, a "right-click" over the selected direction arrow 1550
prompts the GUI to display a "direction menu-window" 1570. This direction menu-window
presents four arrows representing the four standard preferred directions— horizontal, vertical,
45°, and -45°. Other embodiments display a "direction menu window" that present preferred
directions other than the standard four identified above. In this example, the user selects the
horizontal direction by pointing the cursor 1560 at the horizontal arrow in the direction window 1570. As a result, the selected direction arrow 1550 is changed from the 45° direction
to the horizontal direction as illustrated in Figure 15B.
As shown in Figure 15B, the direction arrow 1550 is now oriented horizontally. As a
result of this change to the global direction of the wiring layer, the GUI in some embodiments
of the invention removes any LPDRs that have local preferred directions that run parallel to
the new global preferred direction. For example, LPDRs 1540 and 1545 that have 0° local
preferred directions previously illustrated in Figure 15A are now removed from the GUI
design window as shown in Figure 15B. In addition, the GUI in some embodiments of the
invention responds to this change in global direction of the wiring layer by identifying any
impermeable edges of the remaining LPD regions. As shown in Figure 15B, "X" icons 1580
are super-imposed on the respective impermeable boundary edges of regions 1530 and 1535.
This identification alerts the user to make changes to the layout to improve routabililty
through these respective boundary edges (i.e. by adding "crowns").
In order to extend these impermeable boundary edges to form "crowns", the GUI
according to some embodiments of the invention enables a user to select impermeable
boundary edges for crowning. The "crowning" of an LPDR is illustrated in Figures 15C and
15D. Specifically, Figure 15C illustrates a user selecting an impermeable boundary edge by
pointing a cursor 1560 at a vertex 1555 of the impermeable boundary edge 1590 (represented
by a dashed line) of region 1530. The vertical arrow under the cursor represents the user
"dragging" the cursor 1560 downward after selecting the vertex 1555 of impermeable
boundary edge 1590. As a result, the selected impermeable boundary edge 1590 is extended
into the wiring layer to form a crown on region 1530 as illustrated in Figure 15D.
All impermeable boundary edges have at least two vertices that represent the end- points of the edge. In this example, the user extended such a vertex of an impermeable
boundary edge to form a triangular-shaped crown. However, a user can also create additional
vertices for an impermeable boundary edge in order to define differently shaped crowns. Some
embodiments allow a user to create and extend a vertex at any mid-point along an LPDR
boundary edge by performing a click and drag operation at a desired mid-point on the edge as
shown in Figures 16A and 16B.
Specifically, Figure 16A illustrates a user adding a vertex 1665 to impermeable
boundary edge 1690 by selecting a mid-point on the edge with cursor 1660. This example also
illustrates a user "dragging" the cursor 1660 downward after selecting the vertex 1565 of
impermeable boundary edge 1690. As a result, the selected impermeable boundary edge 1690
is extended into the wiring layer to form a crown on region 1630 as illustrated in Figure 16B.
This ability to add vertices to boundary edges provides a user with the flexibility to define
crowns of various shapes.
U.S. Patent Application entitled "Method and Apparatus for Generating Layout
Regions with Local Preferred Directions" filed concurrently with the present application,
with the Express Mail Number EV454047130US, and attorney docket number CDN.P0079,
describes an auto LPDR generator of some embodiments of the invention. Also, U.S. Patent
Application entitled "Local Preferred Direction Routing," filed concurrently with the present
application, with the Express Mail Number EN454047143US, and attorney docket number
CDΝ.P0078, describes the routing tools that can route a layout with LPD's. These
applications are incorporated herein by reference. Other EDA tools can also consider layouts
with LPD's. For instance, some embodiments might include a placer that computes placement
costs (e.g., wirelength and/or congestion costs) based on the different LPD's within which the circuit modules or the pins of these modules fall.
While the invention has been described with reference to numerous specific details,
one of ordinary skill in the art will recognize that the invention can be embodied in other
specific forms without departing from the spirit of the invention. For instance, some
embodiments define a crown boundary between an LPDR with a Manhattan LPD (e.g., a
horizontal direction) and an LPDR with a non-Manhattan LPD (e.g., a 45° diagonal direction)
in terms of an angle that is between the Manhattan and non-Manhattan directions (e.g., a
22.5° direction). Thus, one of ordinary skill in the art would understand that the invention is
not to be limited by the foregoing illustrative details, but rather is to be defined by the
appended claims.

Claims

We Claim:
1. A design layout comprising:
(a) a plurality of wiring layers; and
(b) a set of polygonally shaped regions on one of the layers, each region in the set having a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different polygonal shapes,
(c) wherein no region in the set encompasses another region in the set.
2. The layout of claim 1, wherein the plurality of regions comprise:
(a) a first region in the shape of a quadrilateral polygon; and
(b) a second region in the shape of a quadrilateral polygon.
3. The layout of claim 1, wherein the plurality of regions comprise:
(a) a first region in the shape of a non-quadrilateral polygon; and
(b) a second region in the shape of a non-quadrilateral polygon.
4. The layout of claim 1 , wherein the plurality of regions comprise:
(a) a first region in the shape of a quadrilateral polygon; and
(b) a second region in the shape of a non-quadrilateral polygon.
5. The layout of claim 4, wherein the second region is in the shape of an octagon.
6. The layout of claim 4, wherein the second region is in the shape of a hexagon.
7. The layout of claim 1, wherein the plurality of regions comprise at least two regions that have a Manhattan local preferred wiring direction.
8. The layout of claim 1, wherein the plurality of regions comprise at least two regions that have a diagonal local preferred wiring direction.
. The layout of claim 8, wherein the diagonal local preferred wiring directions are orthogonal to each other.
10. The layout of claim 8, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.
11. The layout of claim 1 , wherein the plurality of regions comprise at least one region that has a Manhattan local preferred wiring direction and at least one region that has a diagonal local preferred wiring direction.
12. A design layout comprising:
(a) a plurality of wiring layers; and
(b) a set of regions on one of the layers, each region in the set having a polygonal shape and a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different polygonal shapes, wherein each polygonal shape is a convex polygon.
13. A multi-layer design layout comprising:
(a) a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and
(b) a second wiring layer positioned directly above or below said first wiring layer, wherein said second wiring layer has at least one region above or below said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one predesigned circuit block, (c) wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.
14. The multi-layer design layout of claim 13, wherein said second wiring layer has a diagonal preferred wiring direction.
15. The multi-layer design layout of claim 14, wherein said at least one region has a Manhattan local preferred wiring direction.
16. The multi-layer design layout of claim 13, wherein a pre-designed circuit block is an IP block.
17. A multi-layer design layout comprising:
(a) a first wiring layer with first and second regions with different local preferred wiring directions;
(b) a second wiring layer with third and fourth regions with different local preferred wiring directions;
(c) a first via between the first and third regions;
(d) a second via between the second and fourth regions; wherein the shape of the first and second vias differ.
18. The multi-layer design layout of claim 17, wherein each via has two via pads, wherein the shape of the first and second vias differ since the shape of at least one of the via pads of one of the vias is different than the shape of both the via pads of the other via.
19. A design layout comprising:
(a) at least two regions having different preferred wiring directions; and
(b) at least one boundary region shared between the two regions, (c) wherein said boundary region is not parallel to either one of the preferred wiring directions of the two regions.
20. A design layout comprising:
(a) a wiring layer;
(b) a first block on said wiring layer, said first block having a local preferred wiring direction on the wiring layer that is different than another local preferred wiring direction on the wiring layer; and
(c) a region encompassing said first block, wherein said region has a local preferred wiring direction that is parallel to the local preferred wiring direction of said first block.
21. The design layout of claim 20 further comprising a second block positioned on said wiring layer, said second block having a local preferred wiring direction parallel to the preferred wiring direction of the first block, wherein said region encompasses both said first and second blocks.
22. The design layout of claim 21 , wherein the blocks are part of a power stripe.
23. The design layout of claim 22, wherein the other preferred wiring direction of the wiring layer is a diagonal preferred wiring direction.
24. The design layout 22, wherein the blocks are pre-designed circuit blocks.
25. The design layout of claim 24, wherein the circuit blocks are memory arrays.
26. The design layout 24, wherein the circuit block are IP blocks.
27. A graphical user interface comprising:
(a) a design window that illustrates a design layout with plurality of wiring layers; (b) a set of at least two regions with different local preferred wiring directions on one wiring layer in the layout;
(c) a set of graphical indicators illustrating the preferred wiring direction of each region in the set of regions.
28. The graphical user interface of claim 27, wherein, in the graphical user interface, said graphical indicators are selectable objects for selecting and moving to redefine the preferred wiring directions of the region.
29. The graphical user interface of claim 27, wherein said graphical indicators are arrows.
30. The graphical user interface of claim 27, wherein at least two regions have different polygonal shapes.
31. The graphical user interface of claim 27, wherein the set of graphical indicators is a first set of graphical indicators, wherein the graphical user interface further comprising a second set of graphical indicators that identify edges of regions that are impermeable to wiring.
32. An integrated circuit ("IC") comprising:
(a) a plurality of wiring layers; and
(b) a set of regions on one of the layers, each region in the set having a shape and a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different shapes,
(c) wherein no region in the set encompasses another region in the set.
33. The IC of claim 32, wherein the plurality of regions comprise:
(a) a first region in the shape of a quadrilateral polygon; and (b) a second region in the shape of a quadrilateral polygon.
34. The IC of claim 32, wherein the plurality of regions comprise:
(a) a first region in the shape of a non-quadrilateral polygon; and
(b) a second region in the shape of a non-quadrilateral polygon.
35. The IC of claim 32, wherein the plurality of regions comprise:
(a) a first region in the shape of a quadrilateral polygon; and
(b) a second region in the shape of a non-quadrilateral polygon.
36. The IC of claim 32, wherein the plurality of regions comprise at least two regions that have a Manhattan local preferred wiring direction.
37. The IC of claim 32, wherein the plurality of regions comprise at least two regions that have a diagonal local preferred wiring direction.
38. The IC of claim 32, wherein the diagonal local preferred wiring directions are orthogonal to each other.
39. The IC of claim 38, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.
40. The IC of claim 32, wherein the plurality of regions comprise at least one region that has a Manhattan local preferred wiring direction and at least one region that has a diagonal local preferred wiring direction.
41. A multi-layer integrated circuit comprising:
(a) a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and
(b) a second wiring layer positioned directly above or below said first wiring layer, wherein said second wiring layer has at least one region above or below said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one predesigned circuit block, (c) wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.
42. The multi-layer IC of claim 41, wherein said second wiring layer has a diagonal preferred wiring direction.
43. The multi-layer design layout of claim 42, wherein said at least one region has a Manhattan local preferred wiring direction.
44. The multi-layer design layout of claim 41, wherein a pre-designed circuit block is an IP block.
45. An integrated circuit comprising:
(a) at least two regions having different preferred wiring directions; and
(b) at least one boundary region shared between the two regions,
(c) wherein said boundary region is not parallel to either one of the preferred wiring directions of the two regions.
46. An integrated circuit ("IC") comprising:
(a) a wiring layer;
(b) a first block on said wiring layer, said first block having a local preferred wiring direction on the wiring layer that is different than another local preferred wiring direction on the wiring layer; and (c) a region encompassing said first block, wherein said region has a local preferred wiring direction that is parallel to the local preferred wiring direction of said first block.
47. The IC of claim 46 further comprising a second block positioned on said wiring layer, said second block having a local preferred wiring direction parallel to the preferred wiring direction of the first block, wherein said region encompasses both said first and second blocks.
48. The IC of claim 47, wherein the blocks are part of a power stripe.
49. The IC of claim 48, wherein the other preferred wiring direction of the wiring layer is a diagonal preferred wiring direction.
50. The IC 46, wherein the blocks are pre-designed circuit blocks.
51. The IC of claim 50, wherein the circuit blocks are memory arrays.
52. The IC of claim 50, wherein the circuit block are IP blocks.
PCT/US2005/019361 2004-06-04 2005-06-04 Local preferred direction architecture, tools, and apparatus WO2005122028A2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8166442B2 (en) 2000-12-07 2012-04-24 Cadence Design Systems, Inc. Local preferred direction architecture

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7594196B2 (en) * 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US7243328B2 (en) * 2003-05-07 2007-07-10 Cadence Design Systems, Inc. Method and apparatus for representing items in a design layout
US7412682B2 (en) * 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7340711B2 (en) * 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US20070266307A1 (en) * 2006-05-15 2007-11-15 Microsoft Corporation Microsoft Patent Group Auto-layout of shapes
US7721235B1 (en) * 2006-06-28 2010-05-18 Cadence Design Systems, Inc. Method and system for implementing edge optimization on an integrated circuit design
US8250514B1 (en) 2006-07-13 2012-08-21 Cadence Design Systems, Inc. Localized routing direction
US8086991B1 (en) * 2007-07-25 2011-12-27 AWR Corporation Automatic creation of vias in electrical circuit design
US8689139B2 (en) * 2007-12-21 2014-04-01 Adobe Systems Incorporated Expandable user interface menu
WO2010035392A1 (en) * 2008-09-29 2010-04-01 日本電気株式会社 Gui evaluation system, gui evaluation method, and gui evaluation program
US20100199251A1 (en) * 2009-01-30 2010-08-05 Henry Potts Heuristic Routing For Electronic Device Layout Designs
US8612923B2 (en) * 2009-02-06 2013-12-17 Cadence Design Systems, Inc. Methods, systems, and computer-program products for item selection and positioning suitable for high-altitude and context sensitive editing of electrical circuits
US8271909B2 (en) * 2009-02-06 2012-09-18 Cadence Design Systems, Inc. System and method for aperture based layout data analysis to achieve neighborhood awareness
US8745555B2 (en) 2010-05-12 2014-06-03 D2S, Inc. Method for integrated circuit design and manufacture using diagonal minimum-width patterns
US8239807B2 (en) 2010-06-01 2012-08-07 Freescale Semiconductor, Inc Method of making routable layout pattern using congestion table
CN102419780A (en) * 2010-09-28 2012-04-18 鸿富锦精密工业(深圳)有限公司 Image text information viewing system and image text information viewing method
US9129081B2 (en) * 2011-10-31 2015-09-08 Cadence Design Systems, Inc. Synchronized three-dimensional display of connected documents
DE102012110278A1 (en) * 2011-11-02 2013-05-02 Beijing Lenovo Software Ltd. Window display methods and apparatus and method and apparatus for touch operation of applications
US8555237B1 (en) 2012-07-05 2013-10-08 Cadence Design Systems, Inc. Method and apparatus for design rule violation reporting and visualization
US9337146B1 (en) * 2015-01-30 2016-05-10 Qualcomm Incorporated Three-dimensional integrated circuit stack
US20170061063A1 (en) * 2015-08-28 2017-03-02 Qualcomm Incorporated Integrated circuit with reduced routing congestion
US10235491B2 (en) * 2017-05-17 2019-03-19 International Business Machines Corporation Dynamic route keep-out in printed circuit board design
US11741278B2 (en) * 2022-01-03 2023-08-29 International Business Machines Corporation Context projection and wire editing in augmented media

Family Cites Families (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4500963A (en) * 1982-11-29 1985-02-19 The United States Of America As Represented By The Secretary Of The Army Automatic layout program for hybrid microcircuits (HYPAR)
US4615011A (en) * 1983-12-19 1986-09-30 Ibm Iterative method for establishing connections and resulting product
US4571451A (en) * 1984-06-04 1986-02-18 International Business Machines Corporation Method for routing electrical connections and resulting product
US4777606A (en) * 1986-06-05 1988-10-11 Northern Telecom Limited Method for deriving an interconnection route between elements in an interconnection medium
JPS63225869A (en) * 1986-10-09 1988-09-20 Nec Corp Wiring path search system
JPS63237436A (en) * 1987-03-26 1988-10-03 Toshiba Corp Wiring of semiconductor integrated circuit device
US4855253A (en) * 1988-01-29 1989-08-08 Hewlett-Packard Test method for random defects in electronic microstructures
JPH0290368A (en) * 1988-09-28 1990-03-29 Fujitsu Ltd Production for automatic lead-out wiring data on terminal of surface mount device parts
JPH03188650A (en) * 1989-12-18 1991-08-16 Hitachi Ltd Routing method, routing system and semiconductor integrated circuit
JPH04677A (en) 1990-04-18 1992-01-06 Hitachi Ltd Method and system for wiring assigned wiring length
JPH04280452A (en) * 1991-03-08 1992-10-06 Hitachi Ltd Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device
JP2759573B2 (en) * 1992-01-23 1998-05-28 株式会社日立製作所 Circuit board wiring pattern determination method
US5439636A (en) * 1992-02-18 1995-08-08 International Business Machines Corporation Large ceramic articles and method of manufacturing
JPH06196563A (en) * 1992-09-29 1994-07-15 Internatl Business Mach Corp <Ibm> Computable overclowded region wiring to vlsi wiring design
FR2702595B1 (en) * 1993-03-11 1996-05-24 Toshiba Kk Multilayer wiring structure.
JP3335250B2 (en) * 1994-05-27 2002-10-15 株式会社東芝 Semiconductor integrated circuit wiring method
JP3410829B2 (en) * 1994-09-16 2003-05-26 株式会社東芝 MOS gate type semiconductor device
US5811863A (en) * 1994-11-02 1998-09-22 Lsi Logic Corporation Transistors having dynamically adjustable characteristics
US6407434B1 (en) * 1994-11-02 2002-06-18 Lsi Logic Corporation Hexagonal architecture
US5822214A (en) 1994-11-02 1998-10-13 Lsi Logic Corporation CAD for hexagonal architecture
JPH08221451A (en) 1995-02-17 1996-08-30 Matsushita Electric Ind Co Ltd Layout design method for data path circuit
US5650653A (en) * 1995-05-10 1997-07-22 Lsi Logic Corporation Microelectronic integrated circuit including triangular CMOS "nand" gate device
US5981384A (en) * 1995-08-14 1999-11-09 Micron Technology, Inc. Method of intermetal dielectric planarization by metal features layout modification
JPH0998970A (en) * 1995-10-06 1997-04-15 Canon Inc X-ray photographing equipment
US5814847A (en) * 1996-02-02 1998-09-29 National Semiconductor Corp. General purpose assembly programmable multi-chip package substrate
JP3352583B2 (en) 1996-03-04 2002-12-03 インターナショナル・ビジネス・マシーンズ・コーポレーション Wiring path search method and apparatus, and inspection-free critical cut detection method and apparatus
US5798936A (en) * 1996-06-21 1998-08-25 Avant| Corporation Congestion-driven placement method and computer-implemented integrated-circuit design tool
JP3137178B2 (en) 1996-08-14 2001-02-19 日本電気株式会社 Integrated circuit wiring design method and apparatus
US6006024A (en) 1996-11-01 1999-12-21 Motorola, Inc. Method of routing an integrated circuit
US6209123B1 (en) 1996-11-01 2001-03-27 Motorola, Inc. Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US6330707B1 (en) 1997-09-29 2001-12-11 Matsushita Electric Industrial Co., Ltd. Automatic routing method
US6263475B1 (en) * 1997-11-17 2001-07-17 Matsushita Electric Industrial Co., Ltd. Method for optimizing component placement in designing a semiconductor device by using a cost value
US6077309A (en) 1998-01-07 2000-06-20 Mentor Graphics Corporation Method and apparatus for locating coordinated starting points for routing a differential pair of traces
US6324674B2 (en) * 1998-04-17 2001-11-27 Lsi Logic Corporation Method and apparatus for parallel simultaneous global and detail routing
US6262487B1 (en) * 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6256769B1 (en) 1999-09-30 2001-07-03 Unisys Corporation Printed circuit board routing techniques
JP2001168195A (en) * 1999-12-06 2001-06-22 Matsushita Electric Ind Co Ltd Multilayered wiring semiconductor integrated circuit
JP2001351979A (en) * 2000-06-05 2001-12-21 Fujitsu Ltd Design support device for semiconductor device
US6889372B1 (en) * 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6898773B1 (en) * 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6601222B1 (en) 2000-10-13 2003-07-29 International Business Machines Corporation Coupled noise estimation and avoidance of noise-failure using global routing information
US6691293B2 (en) 2000-11-01 2004-02-10 Fujitsu Limited Layout instrument for semiconductor integrated circuits, layout method for semiconductor integrated circuits and recording medium that stores a program for determining layout of semiconductor integrated circuits
US6665852B2 (en) 2000-12-01 2003-12-16 Sun Microsystems, Inc. Piecewise linear cost propagation for path searching
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US6826737B2 (en) 2000-12-06 2004-11-30 Cadence Design Systems, Inc. Recursive partitioning placement method and apparatus
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6915500B1 (en) * 2001-06-03 2005-07-05 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring
US7036101B2 (en) * 2001-02-26 2006-04-25 Cadence Design Systems, Inc. Method and apparatus for scalable interconnect solution
US6763512B2 (en) 2001-04-06 2004-07-13 Sun Microsystems, Inc. Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits
US6601227B1 (en) * 2001-06-27 2003-07-29 Xilinx, Inc. Method for making large-scale ASIC using pre-engineered long distance routing structure
US6441470B1 (en) * 2001-08-21 2002-08-27 Sun Microsystems, Inc. Technique to minimize crosstalk in electronic packages
US7058913B1 (en) 2001-09-06 2006-06-06 Cadence Design Systems, Inc. Analytical placement method and apparatus
JP4786836B2 (en) * 2001-09-07 2011-10-05 富士通セミコンダクター株式会社 Wiring connection design method and semiconductor device
US6651235B2 (en) * 2001-10-30 2003-11-18 Cadence Design Systems, Inc. Scalable, partitioning integrated circuit layout system
US7117468B1 (en) * 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7096449B1 (en) * 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US6973634B1 (en) * 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US6792587B2 (en) * 2002-01-28 2004-09-14 Sun Microsystems, Inc. 2.5-D graph for multi-layer routing
JP4074110B2 (en) * 2002-03-20 2008-04-09 Necエレクトロニクス株式会社 Single-chip microcomputer
US6889371B1 (en) * 2002-06-04 2005-05-03 Cadence Design Systems, Inc. Method and apparatus for propagating a function
US7197738B1 (en) * 2002-08-09 2007-03-27 Cadence Design Systems, Inc. Method and apparatus for routing
US7062743B2 (en) * 2002-09-24 2006-06-13 The Regents Of The University Of California Floorplan evaluation, global routing, and buffer insertion for integrated circuits
US7047513B2 (en) * 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7171635B2 (en) * 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7010771B2 (en) * 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7080342B2 (en) * 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US6988258B2 (en) * 2002-12-09 2006-01-17 Altera Corporation Mask-programmable logic device with building block architecture
US7013445B1 (en) * 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7086024B2 (en) * 2003-06-01 2006-08-01 Cadence Design Systems, Inc. Methods and apparatus for defining power grid structures having diagonal stripes
US7003748B1 (en) * 2003-06-01 2006-02-21 Cadence Design Systems, Inc. Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring
JP2005100239A (en) 2003-09-26 2005-04-14 Renesas Technology Corp Automatic layout apparatus, layout model generation apparatus, layout model verification apparatus, and layout model
US7058919B1 (en) 2003-10-28 2006-06-06 Xilinx, Inc. Methods of generating test designs for testing specific routing resources in programmable logic devices
JP2005141679A (en) 2003-11-10 2005-06-02 Toshiba Microelectronics Corp Semiconductor integrated circuit apparatus, layout method for semiconductor integrated circuit apparatus and layout design program for semiconductor integrated circuit apparatus
US6899371B1 (en) * 2003-11-20 2005-05-31 Dorothy L. Hammond Auxiliary sun visor
US7127696B2 (en) 2003-12-17 2006-10-24 International Business Machines Corporation Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management
US7174529B1 (en) * 2004-02-14 2007-02-06 Cadence Design Systems, Inc. Acute angle avoidance during routing
US7185307B2 (en) * 2004-02-19 2007-02-27 Faraday Technology Corp. Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units
US7707537B2 (en) * 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US7340711B2 (en) * 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
WO2005122027A2 (en) 2004-06-04 2005-12-22 Cadence Design Systems, Inc. Local preferred direction routing and layout generation
US7412682B2 (en) * 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7185304B2 (en) 2004-10-14 2007-02-27 Intel Corporation System and method for VLSI CAD design
US7299442B2 (en) 2005-01-11 2007-11-20 International Business Machines Corporation Probabilistic congestion prediction with partial blockages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP1763805A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8166442B2 (en) 2000-12-07 2012-04-24 Cadence Design Systems, Inc. Local preferred direction architecture
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8010929B2 (en) 2004-06-04 2011-08-30 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions

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US20090024977A1 (en) 2009-01-22
WO2005122028A3 (en) 2006-11-16
US7441220B2 (en) 2008-10-21
EP1763805A4 (en) 2007-12-12
US20050229134A1 (en) 2005-10-13
EP1763805A2 (en) 2007-03-21
JP2008502152A (en) 2008-01-24
JP2013077844A (en) 2013-04-25
US8166442B2 (en) 2012-04-24

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