WO2005124787A2

WO2005124787A2 - Electrical device having a programmable resistor connected in series to a punch-through diode and method of manufacturing therefor

Info

Publication number: WO2005124787A2
Application number: PCT/IB2005/051893
Authority: WO
Inventors: Pierre H. Woerlee; Franciscus P. Widdershoven; Victor M. G. Van Acht; Teunis J. Ikkink; Nicolaas Lambert; Albert W. Marsman
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-06-16
Filing date: 2005-06-09
Publication date: 2005-12-29
Also published as: EP1759392A2; JP2008503085A; KR20070049139A; WO2005124787A3; TW200614234A; CN101006517A

Abstract

The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.

Description

Electrical device and method of manufacturing therefor

An important new class of non- volatile memories is based on the use of materials having a programmable resistance. Memories based on these materials have the advantage that they can be better scaled down to smaller sizes than charged based memories such as DRAM. The most prominent technologies are MRAM, the phase change memory, the programmable metallisation cell (PMC), the RRAM and molecular storage. Generally speaking, the storage elements of the above technologies are resistors with at least two non-volatile resistance states. A particular resistance state can be programmed by application of either a voltage, a current or both. US 5,296,716 and US 6,607,974 describe a memory matrix comprising memory elements of a chalcogenide material. This type of material exhibits different electrical characteristics depending on its state. In an amorphous state it exhibits a higher resistivity than in a crystalline state. In addition, the material can be in one of a plurality of in-between states. The state can be controlled by subjecting a region, the so-called active region of the material, to a relatively strong current. By measuring the resistivity with a relatively low current the state of the material can be determined without altering it. In order to select a particular memory element from a plurality, the memory elements are connected in series with a selection device having a non- linear electrical behaviour. The type of selection device used in the known memory matrix is a pn-diode, such as a conventional diode, a zener diode or an avalanche diode, depending on whether the diode array of the memory matrix is operated in a forward biased mode or a reverse biased mode. The selection device in the known memory matrix is a two-port selection device. It has two terminals composed of semiconducting material with different doping types, i.e. a p-doped terminal and an n-doped terminal. Electrically connecting these terminals to conductors requires two different materials in order to ensure an Ohmic contact. This renders the manufacture of the known electrical device relatively complicated. It is an object of the invention to provide an electrical device which may be manufactured in a less complicated way. According to the invention this object is realized in that the selection device is a punch-through diode. A punch-through diode is a non-linear element comprising at least a first and a second region of a first conductivity type and a third region of a second conductivity type between the first and the second region. The first and the third region on the one hand, and the third and the second region on the other hand form two oppositely located rectifying junctions. At least one of these can be biased in a forward direction by means of the electric field of the other junction, which is reversely biased. The width of the third region is sufficiently small and its doping profile is such that punch- through occurs between the two junctions before one of the junctions breaks down in at least one bias direction. The punch-through diode has two terminals of the same doping type. Therefore, the number of different materials used in various steps of the production process is less than in the manufacture of the known electrical device resulting in a less complicated manufacturing process. A wide range of materials can be used for both the semiconductor and metal electrodes. An incomplete list contains: elemental semiconductors and their alloys (i.e Si, Ge, SixGel-x), III-V (i.e. GaAs, ...), II- VI (ZnS, ...), chalcopyrites, chalcogenides, metal oxides, sulfides etc can be used. As an alternative, polymers or organic molecules can be used to replace the inorganic semiconductor materials listed above. The semiconductor materials will mostly be in the polycrystalline phase since low temperature (non-epitaxial) . deposition techniques are used. However, in some cases also single crystalline semiconductor materials can be obtained. The metals may be chosen for example from Cu, Al, Ti, TiN, Ta, TaN, Ni, Co, Ag, Pt, Ru(O ), alloys. Additionally, barrier metals can be used for example. In an embodiment the punch-through diode has two n-doped terminals. This allows for a relatively easy way of obtaining ohmic contacts with conductors connected to the punch-through diode. This is in particular attractive for a silicon punch-through diode as the concentration of electrically active dopant elements is relatively large for n-doping in silicon. In again another embodiment of the integrated circuit according to the invention the punch-through diode comprises at least a first region of a semiconductor material of a first conductivity type between a second region of a semiconductor material of a second conductivity type and a third metal region. The presence of these metal layers only slightly influences the second-order behaviour. An asymmetric electrical behaviour of the punch through diode may be obtained by using asymmetric doping profiles, including low doped n or p-type regions near the electrodes. The punch-through diode may be arranged to operate alternatingly in forward direction and in backward direction. Unlike other diodes such as a pn diode or a Zener diode, a punch-through diode is particularly suited to provide similar currents in forward direction and in backward direction. Moreover, and unlike for example a Zener diode, the amplitude of the current can be well controlled over a relatively large range. This is particularly useful when the current J through the programmable resistor is relatively high, e.g. higher than 10⁴ A/cm². At relatively high currents, degradation of the electrical device may occur, e.g. due to electromigration. By using a current with alternating polarity these effects may be reduced. The punch-through diode has the advantage over other known two-port selection devices that it is able to provide currents of both polarities having similar amplitudes. Another advantage of the punch-through diode relating to its ablity to provide currents of both polarities is apparent when the programmable resistor has a first state and a second state, a transition from the first state to the second state and from the second state to the first state requiring electric signals with opposite polarities. Examples of this type of programmable resistor are a Programmble Metallisation Cell, and a Molecular Storage cell. These resistors require currents of different polarity to switch them from the first state to the second state, and back. Unlike other known two-terminal selection devices the punch-through diode has the ability to deliver these currents of alterating polarity in a controlled way. In particular, the punch-through is able to deliver relatively high current densities J higher than 10⁴ A/cm² as are required for programming resistors based on Phase Change technology (melting and recrystallisation), Programmable Metallisation Cell technology (filament formation), and molecular cell technology (oxidation/reduction of molecules). In an embodiment the punch-through diode comprises a poly-crystalline material such as poly-crystalline silicon. In such a selection device a relatively short switch- off time is obtained because it allows for a relatively fast trapping of holes. The punch-through diode and the programmable resistor may constitute a memory cell which is conveniently programmed and read using electrical currents. An electric device, such as an integrated circuit, may comprise a plurality of such memory elements. The integrated circuit may comprise additional circuitry such as processor units, clocks, power supply units etc. The memory elements may be accessible, for example by one common first conductor and a respective second conductor for each memory element. The invention is particularly advantageous for application in an electrical device which comprises an array of such memory cells, a first set of conductors and a second set of conductors, wherein the memory elements are arranged in a memory matrix and each memory element is connected between one conductor of the first set, and one conductor of the second set. It was recognized by the inventors that leakage currents can be significantly reduced in a memory wherein the programmable resistance is combined with a punch through diode as the selection device. It was found that the punch through diode has very favorable electrical characteristics in the voltage-current range required to program and read the programmable resistor. The punch through diode allows high current densities, while having a steep current-to-voltage slope. The latter contributes to a substantial reduction of leakage currents in half- select mode. It is remarked that US 4,254,427 describes a ROM having punch through diodes as selection devices. In a ROM device, however, the selection device is only used to select whether data is read from a memory element or not. In a rewritable memory the situation is significantly more complex as it is not only necessary to read a memory element, but also to write at least two different states, without influencing the state of other memory elements, and avoiding excessive leakage currents. In a memory matrix a memory element can be written, erased or read by providing the conductor of the first set and the conductor of the second set which are connected to the selected memory element with voltages which deviate in a mutually opposite sense from a reference voltage. In order to prevent that other memory elements are written or erased or that a read operation is disturbed by leakage currents via non-selected memory cells, the memory matrix can be operated in a half-select mode. In this mode the other conductors are provided with the reference voltage. This mode is preferably used in an embodiment comprising symmetrical memory elements, i.e. wherein the resistive elements can be erased with a voltage or current opposite to that used in writing and wherein the selection device has a symmetrical I-V characteristic. In an alternative embodiment, the memory elements are asymetric, i.e. the polarity of the voltage or current with which the memory element is erased is the same as that with which it is written. In an asymmetric embodiment the selection device usually has an asymetric I-V characteristic. In this alternative embodiment the memory matrix is preferably driven in full-select mode. Herein the conductor of the first set associated with the selected memory element as well as the conductors of the second set not associated with the selected memory element are driven with a first voltage and the conductor of the second set associated with the selected memory element as well as the conductors of the first set not associated with the selected memory element are driven with a second voltage. The first and the second voltage deviate from the reference voltage in a mutually opposite sense. In the full-select mode the memory matrix is arranged to be driven in an operational mode in which the conductor of the second set, which is associated with the selected memory element, is driven with a first voltage deviating from a reference voltage, and all other conductors are driven with the reference voltage. In this way an entire column can be erased. The method of manufacturing an electric device according to the invention comprises the steps of providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposed to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material. The stack comprises the layers which constitute the punch through diode. The stack may be patterned, thereby forming the punch through diode which results in a relatively compact electrical device. Alternatively, the punch through diode may be constituted by the layers as provided.The stack may be a horizontal stack, i.e. a stack the layers of which are substantially parallel to a main surface of a substrate they are provided on. Alternatively, the stack may be a vertical stack, i.e. a stack the layers of which are substantially perpendicular to a main surface of a substrate they are provided on. The layers may be provided by deposition. Alternatively, or in addition, the layers may be provided by implanting regions of a substrate which implanted regions form the layers. The layer of material having a programmable resistivity may be patterned thereby forming the programmable resistor. The steps of patterning the layer of material having a programmable resistivity and of patterning the stack may be performed in one step which allows for relatively easy processing and for a relatively compact electrical device because overlay errors may be avoided.

These and other aspects of the invention are described in more detail with reference to the drawing. Therein: Figure 1 schematically shows a resistance based memory. Figure 2A and 2B schematically show the operation of such a memory in half- select mode, Figure 3A and 3B schematically show the operation of such a memory in full- select mode, Figure 4 schematically shows a memory matrix according to the invention, Figure 5 shows an overview of memories having a programmable resistance and their properties, Figure 6 schematically shows a first embodiment of a memory element according to the invention, Figure 7 shows the electrical behaviour of a memory array of memory elements shown in Figure 6 during writing and erasure, Figure 8 shows the electrical behaviour of a memory array of memory elements shown in Figure 6 during reading, Figure 9 schematically shows a second embodiment of a memory element according to the invention, Figure 10 shows electrical behaviour of a memory array of memory elements according to Figure 9 during programming, Figure 11 shows a different aspect of the electrical behaviour of a memory array of memory elements according to Figure 9 during programming, Figure 12 shows again a different aspect of electrical behaviour of a memory . array of memory elements according to Figure 9 during reading, Figures 13A to 13G show a first way of manufacturing a memory array according to the invention, Figure 14A-14C show a second way of manufacturing a memory array according to the invention, Figure 15A-15B show a third way of manufacturing a memory array according to the invention. The figures are not drawn to scale.

Figure 1 schematically shows a memory matrix. It comprises a plurality of memory elements Mij arranged in rows and columns. For clarity only 2 columns and 3 rows thereof are shown but a typical memory matrix may comprise a significantly higher number thereof, e.g. 10,000 rows and columns. The memory cells, e.g. M13, comprise a programmable resistance PR and a selection device S connected in series between a first conductor (WL1, WL2) and a second conductor (BL1, BL2, BL3). Figures 2A and 2B schematically show how a memory element can be selected in half-select mode. For clarity the memory elements are not shown therein. Only the selected memory element is symbolically represented by a dot at the crosspoint of the conductors to which it is connected. As illustrated in Figure 2A, a memory element in a matrix, here in column 3, row 3, can be selected in a half-select mode by providing the conductors, which are connected to the selected memory element, with voltages Vp, 0 respectively, which deviate in a mutually opposite sense from a reference voltage Vp/2. This causes the selection device of the selected memory element to assume a conducting state so that the memory element is programmed into a desired state. In this way, however, also a voltage difference exists over other memory elements in the same row or column. Unfortunately, it was observed in the known devices that selection devices of the latter memory elements start conducting also, albeit at a lower rate than the selection device of the selected memory element. This results in a relatively high power consumption, and causes noise when reading the content of a selected memory cell. A comparable effect applies to the situation in Figure 2B. Here the content of the selected memory element is erased by applying voltages 0 and Ve to the conductors associated with the selected memory element and a reference voltage Ve/2 to the other conductors. The voltage drop Ve/2 over the memory elements in the same row or the same column causes a leakage current. In particularly in large matrices this can result in a substantial power consumption. Figures 3A and 3B show the full-select mode, an alternative way of selecting a memory element. Again the conductors associated with the selected memory element are provided with voltages (Vp, 0) which deviate in a mutually opposite sense from a reference voltage Vp/2. Contrary to the half-select mode the row conductors not associated with the selected memory (non-selected row conductors) are provided with a voltage (0) oppositely biased in comparison to that of the selected row conductor. Likewise the non-selected column conductors are provided with a voltage (Vp) oppositely biased in comparison to that of the selected row conductor. Now leakage currents can be substantially reduced provided that an asymmetric selection device is used. Erasure in full-select mode is illustrated in Figure 3B. Here a column of memory elements is erased at once by providing that column with an erasure voltage (Ve). In the full-select mode it is not possible to erase single memory elements. Figure 4 schematically shows an integrated circuit IC according to the invention having a plurality of memory elements M comprising a series connection of a programmable resistance and a punch-through diode (See Figures 6 and 9). The integrated circuit IC further comprises a first set of conductors CI (word lines WL1, ..., WL5) and a second set of conductors C2 (bit lines BL1, ..., BL4). The memory elements M are arranged in a memory matrix and each memory element M is connected between one conductor of the first set CI, and one conductor of the second set C2. For clarity the integrated circuit IC shown only comprises a limited number of word lines and bit lines. A practical memory matrix may comprise 1000-10000 wordlines and bit lines for example. In the embodiment shown the word lines and the bit lines are controlled by a first AD1 and a second address decoder AD2 respectively which receive a memory address ADDR. A current conducted via a particular bit line BL1,...,BL1 can be sensed by a current sence amplifier CSA so as to determine a state of a selected memory element. Various materials that have a programmable resistance are known to the skilled person. By way of example the following technologies are mentioned. MRAM (magnetoresistive random access memory) uses a magnetoresistive material which has a resistance dependent on the orientation and strength of a locally present magnetic charge. MRAM is described in more detail in R. Scheuerlein et al. ISSCC, Digest of Technical papers ppl28 2000. and S. Tekrani et al, . ISSCC, Digest of Technical papers ppl28 200T. PCRAM (phase change random access memory), as described for example in

S.Lai and T. Lowrey, Tech. Digest IEDM, paper 36.5 (2001) uses a material of which the state can be varied between amorphous and crystalline. This state determines the resistivity of the material. A PMC memory element uses an electrochemical cell between electrodes with dissolvable nano-filaments. By applying a voltage of a first polarity a metal wire is formed between the electrodes, so that the cell assumes a low resistance state. By applying a voltage of opposite polarity the metal is oxidised, and the cell assumes a high resistance state. See for example US6084796. Another example of these technologies is RRAM, as described in W.Zhuang et al, Tech. Digest IEDM, pg 143 (2002). Again another kind of programmable resistive memory is based on molecular storage, which is described in more detail in HP/UCLA group, Science 289 2000 1172 (2003). The properties of these materials are summarized in the table shown in Figure 5. Therein the way of programming the material referred to in column 1 is mentioned in the second column. For phase change materials (PCRAM) for example a minimum amount of power is required to heat the material to a sufficient extent. It is not very relevant whether this is realized with a high current and a low voltage or the other way around. In MRAM the programming current is decisive. In most other devices it is the voltage that decides which state is assumed by the material. The fourth column describes the requirements which are put on the selection device in terms of the voltage over the device and the current density. Possible embodiments of the memory elements in an integrated circuit according to the invention will now be described in more detail with reference to Figures 6 to 12. Figure 6 shows an example of a symmetric memory element in an integrated circuit according to the invention. The memory element shown therein comprises a series connection of a programmable resistance PR and a punch-through diode S. In this embodiment the programmable resistance PR is an electrochemical cell with (dissolvable) nano filaments. The programmable resistance element PR is a PMC cell, comprising a top electrode of silver PR1, a Ag _0.33 Ge ₀.₂o Se _{0. 7} solid state electrolyte PR2 and a metal bottom electrode PR3. The thickness tl of the layer PR2, i.e. the distance between layers PR1 and PR3, is typically 30 nm. The latter electrode may include a barrier metal such as TiW, TiN, Ta(N), W, WSi₂. By applying a positive potential to the silver electrode PR1 silver ions will be reduced and a silver wire will be formed at the top electrode. When the silver wire contacts the bottom electrode PR3 a low resistance path ("1") is created. For reverse bias the silver wire is oxidized and silver ions are formed, resulting in a high resistance state ("0"). A typical value for the "1" state is 50 kΩ. The off resistance is much higher. In this example a value of 10MΩ is assumed. The punch-through diode S in this embodiment is symmetrical, and comprises a first region S2 of a semiconductor material of a first conductivity type between a second region SI of a semiconductor material of a second conductivity type and a third region S3 of a semiconductor material of a second conductivity type. The punch-through diode SI -S3 may be conventionally dimensioned. By way of example it is implemented as a silicon device having n⁺ layer SI which is doped by As in a concentration of 10²⁰ cm^"3 , p layer S2 which is doped by B in a concentration of 5T0¹⁸ cm^"3 and n⁺ layer S3 which is doped by As in a concentration of 10²⁰ cm^"3. The separation between the anode and the cathode, i.e. the distance t2 between the layers SI and S3 is 30 nm. The memory element has a diameter d of 50 nm. A half-select scheme, as schematically shown in Figures 2A, 2B, is employed for reading, writing and erasing. The memory element to be programmed receives the full voltage Vp. Other memory elements can have a zero, positive half bias Vp/2 and negative half bias -Vp/2. In figure 7 the PT diode I-V characteristic Div is shown. Furthermore load lines of a low and high resistance state are shown for the full-select condition Ls and Hs respectively and for the half-select condition L_H and H_H respectively during write (+ wordline polarity) with Vp = 2.5 V. The load lines indicate the relation V = Vp-I*R, wherein I is the current through the series arrangement of the selection device S and the programmable resistance PR, and wherein R is the instantaneous value of the programmable resistance. The intersection of the relevant load line and the characteristic Div determines the current and voltage over the selection device in the operational state. Since the device is symmetric, the same considerations apply to erasure of a memory element M. First a writing operation is described. It is assumed that the start condition is the high resistance state (before writing to a block all bits are assumed to be erased). From figure 7 it is clear that the voltage V_RES over the resistor is larger than +0.3 V over the range from 10MΩ (HS) to 50 KΩ (LS). Hence, the programmable resistor will assume its low resistance state. Furthermore currents are large enough (>100nA) to program the programmable resistor PR in the (sub) μs range. Secondly it can be observed that for the half- selected devices (both polarities) the current is more than 10⁴ times smaller than that for the maximum current. In the half-selected memory elements the voltage drop over the resistor is less than lOmV. Hence, little parasitic program current flows and disturbs (i.e. unintentional writing or erasing) are negligible. For the erase action the situation is similar. Hence it is possible to program, i.e. to write or erase bits selectively in a short time. Next read-out is discussed. The voltage drop over the resistor should be smaller (to avoid further programming). In figure 8 the PT diode I-V characteristic (Div) and load lines of a low and high-R resistor are shown both for full and half-select Ls, Hs; L_H, H_H condition during reading (+ wordline polarity). The read voltage is 2.1 V. The read current of a selected low- resistance cell is 1.7 μA which is sufficient for read out. The voltage drop over the resistor is less than 0.1V which is low enough to reduce unwanted programming actions. Read current for the high resistance is 50 times lower, hence there is sufficient margin for read out. Finally, parasitic currents through half-selected devices are four to five orders of magnitude lower than the read current. This shows that read out in megabit arrays is possible. From the results described above it is clear that the symmetric PT select device is well suited for electrochemical cells. An example of application of an asymmetric punch-through device in a programmable resistance memory is discussed below with reference to Figure 9. The punch through device S subsequently has an n⁺ layer SI which is doped by As in a concentration of 10²⁰ cm^"3, a p⁺ layer S2 which is doped by B in a concentration of 5-10¹⁸ cm^"3, a p layer S3 which is doped by B in a concentration which is substantially smaller than the concentration in the p+layer S2 e.g. 5-10¹⁷ cm^"3, and an n⁺ layer S4 which is doped by As in a concentration of 10²⁰ cm^"3, wherein the separation between anode and cathode, i.e. the distance tl between layers SI and S4 is 62 nm in total, 20 nm of which is due to the thickness t2 of the p⁺ doped region S2. The programmable resistance PR is a PCRAM with chalcogenide Ge₂Sb₂Te₅ alloy (thickness t3 of 10 - 20 nm) PR2 which is sandwiched between electrode layers PR1, PR3, of a W-based material, TiW, W, WSi₂, or other suitable materials, such as TiN, Ta, TaN. The area of one of the electrodes PR3 may be equal to that of electrode PR1 or alternatively it may be smaller than that of PR1, such as e.g. smaller than (50 nm)² to reduce the program currents which may be typically 50 μA. The low and high-resistance state is set at 10 kΩ and 250 kΩ respectively. Since the program current is high, the punch through diode has a relatively large diameter d of 100 nm. The PCRAM is written and erased with pulses having the same polarity. Hence an asymmetric punch-through diode is desirable. In figure 10 the I-V characteristic of the PT diode Div and the load lines of the high and low-resistance Hs, Ls are shown. Programming, erasure and read-out are all done in the forward direction. The program voltage is 2.5 V. For the low-resistance case the voltage drop over the resistor is 0.75V. For the high-resistance case it is 0.87 V. Current capability is sufficient for reset for a down scaled electrode (ID limit). The non-selected device has a very low current (0.1 pA), so there is hardly any voltage drop over the resistor (see Figure 11 for reverse characteristic). Hence undesired programming is negligible for the asymmetric PT device. The cells can be erased by a rapid heating of the material, followed by a rapid cooling. A reduced current is required for read-out of the device. In figure 12 the I-V characteristics and load lines for a read-out voltage of 1.8 V are shown. The voltage drops over the low and high resistor are 0.13 and 0.23 V respectively. The read current is 12.6 μA. The dissipated power is low enough to ensure read out without disturbances. The read current is also sufficiently high for a sufficiently high read out speed (> MHz). The leakage current in the reverse direction is 5-6 orders of magnitude smaller than the read current. Hence the asymmetric PT device is well suited for use in uni-polar arrays. With reference to Figures 13 A to 13G and Figure 14A-14C two possible ways of manufacturing a memory according to the invention are elucidated. The first one allows for a relatively high temperature back-end processing, e.g. in a Tungsten based interconnect technology. The second one is in line with a low temperature Copper back end technology. Figures 13A-13G show a first way of manufacturing, based on a Tungsten metallization technology. The Tungsten metallization allows for a relatively high temperature budget to be used. The embodiment will deal with an asymmetric device fabricated using established CMOS compatible technologies and materials for the 2T device. A PMC cell is assumed as the programmable resistance, but other suitable materials could be applied as an alternative. The electrical device may comprise a substrate such as e.g. a Silicon or GaAs wafer which is not shown in the Figures and in which other electrical elements such as e.g. transistors or resistors may be formed. The substrate may be provided with a dielectric layer in which conductive layers are arranged, e.g. to mutually connect the other electrical elements if present. The conductive layers may comprise interconnect layers and plugs connecting adjacent interconnect layers. These elements are well known in the art of semiconductor manufacturing. In Fig. 13A a single interconnect layer 10 and corresponding plug of Tungsten 11 is shown but the invention is not limited to just one interconnect layer and/or one plug. After Tungsten plug formation a combined barrier layer/contact resistance layer 12, e.g. a stack of Ti/TiN/Ti is deposited by sputtering as shown in Figure 13 A. On top of this layer an amorphous silicon layer 20 having a total thickness of approximately 200 nm is deposited in a single deposition step with an LPCVD type process. The bottom part 21 of amorphous silicon layer has a thickness of 30 nm and is highly doped in-situ with Arsenic or Phosphorus with a doping concentration in the range of 10²⁰-10²¹ cm^"3. The doping concentration may be up to solid solubility of the dopant. The top part 22 of the amorphous silicon layer (i) is not doped intentionally. In a subsequent step, the result of which is shown in Figure 13B, the top part

22 of the amorphous Silicon layer is provided with a p-type implantation, e.g. by body doping with B or BF₂ using an implant energy between 10 - 20 keV and a dose of approximately ~10¹³ cm^"2, and with an n-type implantation of e.g. As having an implant energy below lOkeV and a dose of approximately 3xl0¹⁵ cm^"2. In this way the asymmetric p- type body doping and the emitter doping is formed. Subsequently, a thin plasma nitride layer 14 may be deposited as a cap layer, which may serve as a hard mask during a subsequent etch step, and as CMP stop layer. Then the stack thus formed is etched to form the 2T selection device as shown in Figure 13C This step is followed by a low temperature (~ 400 C) inter-metal dielectric deposition and an oxide CMP step in which the nitride layer 14 serves as a CMP stop layer (see fig 13D). Thereafter, the amorphous layer 20 is recrystallized at low temperature (around 500-700 °C). The heating could be done with a pulsed excimer laser. An RTP anneal, RTO step (activate and to passivate the sidewall by growing a thin oxide) or even a furnace anneal (T< 750° C) are other options. As a result, the amorphous layer 20 is recrystallized and a polycrystalline morphology results. During recrystallisation the dopants are electrically activated to a high degree (similar to solid phase epitaxy) by the transition from the amorphous to the crystalline phase. After nitride removal a thin metal/ barrier 17 (for example Ni, Co, Ti, .../TiN) layer is deposited followed by a salicide formation step, the result of which is shown in Figure 13E. Furthermore by suicide formation at the n+-silicon salicide interface a low contact resistance is obtained. Hence by careful optimization of the thermal budget electrical activation can be high and dopant diffusion can be negligible. An optional hydrogen (furnace or plasma) anneal could be applied to improve activation and reduce leakage current. As illustrated in Figure 13F, a stack 30 comprising a metal electrode 31, an amorphous solid state electrolyte 32 with a specific number of metal ions and a second metal electrode 33 is deposited, in this order, by sputtering. A plasma nitride cap layer 18 is deposited hereafter. After patterning of the memory element an intermetal dielectric 16' is deposited (could be HDP-CVD oxide or a stack of nitride/oxide). CMP is applied to planarize the topography, the silicon nitride layer 18 may serve as a CMP stop layer (see fig. 13G). Thereafter a second inter-metal dielectric is deposited, a groove 15 is etched, filled with a barrier 13 and a W- interconnect 19 is formed with CVD deposited Tungsten followed by a tungsten CMP step. This ends the memory element processing. The resulting memory element comprising the programmable resistor 30 and the punch-through diode 20 is shown in Figure 13H. A low-temperature process compatible with a Copper Damascene technology is described with reference to Figures 14A-14C. After Copper metallisation layer 40 and corresponding plug 41 have been finished, a first stack 50 is formed by deposition of a barrier layer 51 (e.g. Ta), a contact layer 52 (could be AuGeNi), a semiconductor 53 (could be n- type GaAs ) in situ doped with Silicon (> 5 10¹⁷ cm^"3)and again a contact layer 54 and barrier layer 55. The barrier layers 51, 55 and contact layers 52, 54 are sputtered, the GaAs layer 53 is deposited by MOCVD. The GaAs layer 53 is polycrystalline. In this way a punch-through diode is formed. Thereafter, a second stack 60 consisting of a barrier layer 61, an electrode layer 62, PMC material 63, a contact layer 64 and a barrier layer 65 is deposited by sputtering. Barrier layers 55 and 61 may be combined. On top of the second stack 60 a thin plasma nitride layer 42 is deposited. The stacks 50, 60 are patterned (See Figure 14B), thereafter an intermetal dielectric layer is deposited. After dielectric CMP (stop on nitride layer 42) the nitride layer 42 is removed selectively. Thereafter, a third LMD layer 43 is deposited, a groove 44 is etched, the groove is filled with a barrier layer 45 and Copper followed by Copper CMP. In this way the second Copper interconnect layer 46 is formed. This procedure can be repeated several times. This allows for manufacturing an electrical device which has multiple layers of individually accessible memory elements, i.e. for a three-dimensional array of memory elements. In this embodiment the semiconductor 53, sandwiched between the two metal contact layers 52, 54, constitutes the selection element 50. The interfaces between the semiconductor layer 53 and the respective metal layers 52, 54 form two diodes arranged back-to back which effectively resemble a punch through diode. The semiconductor layer may be n-doped by e.g. Si with a concentration of > 5-10¹⁷ cm^"3. The semiconducting layer 53 may have a thickness of < 100 nm. In another embodiment the punch through diode is integrated in a semiconducting substrate such as e.g. a silicon wafer or a GaAs wafer. As an example an embodiment in an advanced SOI CMOS technology is described below with reference to Figures 15A, 15B. In this embodiment the select device is a lateral punch through diode, which may be fabricated easily without major process alterations using standard IC process technology such as e.g. 90 nm CMOS technology. After formation of a silicon island with a thickness of 60 nm e.g. by standard SOI STI isolation 71 on a substrate 70 of buried oxide, a modified p well body 81, an anode 82 and a cathode 83 are formed by ion implantation and rapid thermal annealing. The p well 81 may be implanted with B at an implant energy of 10 keV and at a dose of 10¹³ cm^"2. The cathode 83 and the anode 82 may be implanted with As at an implant energy of 10 keV at a dose of 3T0¹⁵ cm^"2. The implants may be followed by an annealing at 1000°C for 1 sec. The anode-cathode separation is less than 70 nm. A suicide protection layer 84 shown in Figure 15A is deposited and patterned to ensure that the cathode 83 and anode 82 are not shorted by a salicide layer. Alternatively, the gate of a transistor may be used to block suicide formation. Thereafter, a standard contact technology including a first tungsten plug 72 is formed exposing the anode 82, followed by the deposition of a layer of memory material 92 such as chalcogenide phase change material, which may be Ge2Sb2Te5 and which may be sandwiched between two electrodes 91, 93 of e.g. TiW. After patterning of the programmable resistor 90 formed by the layers 91, 92, 93, a second contact 73 is made to the top electrode 93 of the programmable resistor 90. A third contact 74 is made to expose the cathode 83 of the selection element 80. The forming of contacts 73 and 74 may take place in the same step. In this way one mask can be avoided. The process is finished with a standard Copper metallisation process to connect the contacts 73 and 74 to a word line 75 and a bit- line 76 respectively. The device comprising a programmable resistor 90 in series connected to a punch-through diode 80 thus obtained is shown in cross section in Figure 15B. It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. The punch-through diode in the electrical device according to the invention may have any functional implementation conceivable to the skilled person on the basis of his common general knowledge in this field. Likewise the programmable resistor may have any functional implementation conceivable to the skilled person in the field of programmable resistor memories. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)^! preceding an element does not exclude a plurality of these elements. The invention resides in each new feature or combination of features.

Claims

CLAIMS:

1. An electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S).

2. An electrical device (Fig. 6) as claimed in claim 1, wherein the punch-through diode (S) has two n-doped terminals.

3. An electrical device (Fig. 6) as claimed in claim 1, wherein the punch-through diode (S) is arranged to operate altematingly in forward direction and in backward direction.

4. An electrical device (Fig. 6) as claimed in claim 3, wherein the programmable resistor (PR) has a first state and a second state, a transition from the first state to the second state and from the second state to the first state requiring electric signals with opposite polarities.

5. An electrical device as claimed in claim 1, wherein the punch-through diode

(20) comprises a poly-crystalline material.

6. An electrical device (Fig. 6) as claimed in claim 1, wherein the punch-through diode (S) and the programmable resistor (PR) constitute a memory cell.

7. An electrical device (IC) as claimed in claim 6, comprising an array of memory cells (M), a first set of conductors (Cl) and a second set of conductors (C2), wherein the memory elements (M) are arranged in a memory matrix and each memory element is connected between one conductor of the first set (Cl), and one conductor of the second set (C2).

8. A method of manufacturing an electrical device as claimed in claim 1, the method comprising the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layers of the semiconductor material.

9. A method as claimed in claim 8, wherein the stack is patterned thereby forming the punch through diode.

10. A method as claimed in claim 8, wherein the layer of material having a programmable resistivity is patterned thereby forming the programmable resistor.

11. A method as claimed in claims 9 and 10, wherein the steps of patterning the layer of material having a programmable resistivity and of patterning the stack are performed in one step.

12. A method as claimed in claim 8, wherein the stack is provided laterally on a main surface of a substrate.