WO2006002069A3 - Redundant processing architecture for single fault tolerance - Google Patents

Redundant processing architecture for single fault tolerance Download PDF

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Publication number
WO2006002069A3
WO2006002069A3 PCT/US2005/021063 US2005021063W WO2006002069A3 WO 2006002069 A3 WO2006002069 A3 WO 2006002069A3 US 2005021063 W US2005021063 W US 2005021063W WO 2006002069 A3 WO2006002069 A3 WO 2006002069A3
Authority
WO
WIPO (PCT)
Prior art keywords
fault tolerance
processing architecture
redundant processing
single fault
comparator
Prior art date
Application number
PCT/US2005/021063
Other languages
French (fr)
Other versions
WO2006002069A2 (en
Inventor
Jeffrey M Wolfe
Jeremy Ramos
Jason Copenhaver
Original Assignee
Honeywell Int Inc
Jeffrey M Wolfe
Jeremy Ramos
Jason Copenhaver
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Int Inc, Jeffrey M Wolfe, Jeremy Ramos, Jason Copenhaver filed Critical Honeywell Int Inc
Priority to EP05759169A priority Critical patent/EP1759293A2/en
Priority to JP2007516665A priority patent/JP2008503002A/en
Publication of WO2006002069A2 publication Critical patent/WO2006002069A2/en
Publication of WO2006002069A3 publication Critical patent/WO2006002069A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G06F11/185—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality and the voting is itself performed redundantly

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one prcessor and a second comparator. Each of the at least two processors are coupled to each of first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.
PCT/US2005/021063 2004-06-15 2005-06-15 Redundant processing architecture for single fault tolerance WO2006002069A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05759169A EP1759293A2 (en) 2004-06-15 2005-06-15 Redundant processing architecture for single fault tolerance
JP2007516665A JP2008503002A (en) 2004-06-15 2005-06-15 Redundant processing architecture for single fault tolerance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/867,894 2004-06-15
US10/867,894 US7392426B2 (en) 2004-06-15 2004-06-15 Redundant processing architecture for single fault tolerance

Publications (2)

Publication Number Publication Date
WO2006002069A2 WO2006002069A2 (en) 2006-01-05
WO2006002069A3 true WO2006002069A3 (en) 2006-04-27

Family

ID=35414771

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/021063 WO2006002069A2 (en) 2004-06-15 2005-06-15 Redundant processing architecture for single fault tolerance

Country Status (4)

Country Link
US (1) US7392426B2 (en)
EP (1) EP1759293A2 (en)
JP (1) JP2008503002A (en)
WO (1) WO2006002069A2 (en)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050273653A1 (en) * 2004-05-19 2005-12-08 Honeywell International Inc. Single fault tolerance in an architecture with redundant systems
US7328371B1 (en) * 2004-10-15 2008-02-05 Advanced Micro Devices, Inc. Core redundancy in a chip multiprocessor for highly reliable systems
JP2006228121A (en) * 2005-02-21 2006-08-31 Toshiba Corp Arithmetic processing unit
US9769354B2 (en) 2005-03-24 2017-09-19 Kofax, Inc. Systems and methods of processing scanned data
US9137417B2 (en) 2005-03-24 2015-09-15 Kofax, Inc. Systems and methods for processing video data
DE102005037233A1 (en) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Method and device for data processing
US7577870B2 (en) * 2005-12-21 2009-08-18 The Boeing Company Method and system for controlling command execution
US20070220367A1 (en) * 2006-02-06 2007-09-20 Honeywell International Inc. Fault tolerant computing system
US20070186126A1 (en) * 2006-02-06 2007-08-09 Honeywell International Inc. Fault tolerance in a distributed processing network
US20070260939A1 (en) * 2006-04-21 2007-11-08 Honeywell International Inc. Error filtering in fault tolerant computing systems
US7685464B2 (en) * 2006-11-20 2010-03-23 Honeywell International Inc. Alternating fault tolerant reconfigurable computing architecture
EP2153328B1 (en) * 2007-05-25 2011-08-10 Freescale Semiconductor, Inc. Data processing system, data processing method, and apparatus
US7850127B2 (en) * 2008-03-11 2010-12-14 Ansaldo Sts Usa, Inc. Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays
US8200947B1 (en) * 2008-03-24 2012-06-12 Nvidia Corporation Systems and methods for voting among parallel threads
KR101476187B1 (en) * 2008-04-04 2014-12-24 엘지전자 주식회사 Method for instructing and performing a network entry
US7877627B1 (en) 2008-12-18 2011-01-25 Supercon, L.L.C. Multiple redundant computer system combining fault diagnostics and majority voting with dissimilar redundancy technology
US8958605B2 (en) 2009-02-10 2015-02-17 Kofax, Inc. Systems, methods and computer program products for determining document validity
US8774516B2 (en) 2009-02-10 2014-07-08 Kofax, Inc. Systems, methods and computer program products for determining document validity
US9349046B2 (en) 2009-02-10 2016-05-24 Kofax, Inc. Smart optical input/output (I/O) extension for context-dependent workflows
US9767354B2 (en) 2009-02-10 2017-09-19 Kofax, Inc. Global geographic information retrieval, validation, and normalization
US9576272B2 (en) 2009-02-10 2017-02-21 Kofax, Inc. Systems, methods and computer program products for determining document validity
US7969229B2 (en) * 2009-02-19 2011-06-28 Hitachi, Ltd. On-chip redundancy high-reliable system and method of controlling the same
US8564616B1 (en) 2009-07-17 2013-10-22 Nvidia Corporation Cull before vertex attribute fetch and vertex lighting
US8542247B1 (en) 2009-07-17 2013-09-24 Nvidia Corporation Cull before vertex attribute fetch and vertex lighting
US20110099421A1 (en) * 2009-09-30 2011-04-28 Alessandro Geist Radiation-hardened hybrid processor
US20110078498A1 (en) * 2009-09-30 2011-03-31 United States Of America As Represented By The Administrator Of The National Aeronautics And Spac Radiation-hardened hybrid processor
US8384736B1 (en) 2009-10-14 2013-02-26 Nvidia Corporation Generating clip state for a batch of vertices
US8976195B1 (en) 2009-10-14 2015-03-10 Nvidia Corporation Generating clip state for a batch of vertices
US8499193B2 (en) * 2010-07-30 2013-07-30 Honeywell International Inc. Integrated dissimilar high integrity processing
US9625894B2 (en) 2011-09-22 2017-04-18 Hamilton Sundstrand Corporation Multi-channel control switchover logic
US8949663B2 (en) * 2011-12-13 2015-02-03 Toyota Jidosha Kabushiki Kaisha Multi-core processor including a monitored processor core whose process result is to be monitored by a number of processors based on processing load
US9483794B2 (en) 2012-01-12 2016-11-01 Kofax, Inc. Systems and methods for identification document processing and business workflow integration
US10146795B2 (en) 2012-01-12 2018-12-04 Kofax, Inc. Systems and methods for mobile image capture and processing
US8989515B2 (en) 2012-01-12 2015-03-24 Kofax, Inc. Systems and methods for mobile image capture and processing
US9058515B1 (en) 2012-01-12 2015-06-16 Kofax, Inc. Systems and methods for identification document processing and business workflow integration
US9058580B1 (en) 2012-01-12 2015-06-16 Kofax, Inc. Systems and methods for identification document processing and business workflow integration
DE102013202253A1 (en) * 2013-02-12 2014-08-14 Paravan Gmbh Circuit for controlling an acceleration, braking and steering system of a vehicle
WO2014160426A1 (en) 2013-03-13 2014-10-02 Kofax, Inc. Classifying objects in digital images captured using mobile devices
US9355312B2 (en) 2013-03-13 2016-05-31 Kofax, Inc. Systems and methods for classifying objects in digital images captured using mobile devices
US9208536B2 (en) 2013-09-27 2015-12-08 Kofax, Inc. Systems and methods for three dimensional geometric reconstruction of captured image data
US20140316841A1 (en) 2013-04-23 2014-10-23 Kofax, Inc. Location-based workflows and services
DE202014011407U1 (en) 2013-05-03 2020-04-20 Kofax, Inc. Systems for recognizing and classifying objects in videos captured by mobile devices
JP2016538783A (en) 2013-11-15 2016-12-08 コファックス， インコーポレイテッド System and method for generating a composite image of a long document using mobile video data
JP2015222467A (en) * 2014-05-22 2015-12-10 ルネサスエレクトロニクス株式会社 Microcontroller and electronic control device using the same
US9912733B2 (en) * 2014-07-31 2018-03-06 General Electric Company System and method for maintaining the health of a control system
US9760788B2 (en) 2014-10-30 2017-09-12 Kofax, Inc. Mobile document detection and orientation based on reference object characteristics
US10242285B2 (en) 2015-07-20 2019-03-26 Kofax, Inc. Iterative recognition-guided thresholding and data extraction
US9779296B1 (en) 2016-04-01 2017-10-03 Kofax, Inc. Content-based detection and three dimensional geometric reconstruction of objects in image and video data
US10331532B2 (en) 2017-01-19 2019-06-25 Qualcomm Incorporated Periodic non-intrusive diagnosis of lockstep systems
US10803350B2 (en) 2017-11-30 2020-10-13 Kofax, Inc. Object detection and image cropping using a multi-detector approach
US11641395B2 (en) * 2019-07-31 2023-05-02 Stratus Technologies Ireland Ltd. Fault tolerant systems and methods incorporating a minimum checkpoint interval

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274554A (en) * 1991-02-01 1993-12-28 The Boeing Company Multiple-voting fault detection system for flight critical actuation control systems
EP1014237A1 (en) * 1998-12-17 2000-06-28 Honeywell Inc. Modular computer architecture

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
JPS6170637A (en) * 1984-09-11 1986-04-11 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Correction of error detection due to decision by majority
US4817094A (en) * 1986-12-31 1989-03-28 International Business Machines Corporation Fault tolerant switch with selectable operating modes
US4959836A (en) * 1987-12-09 1990-09-25 Siemens Transmission Systems, Inc. Register robustness improvement circuit and method
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5339404A (en) * 1991-05-28 1994-08-16 International Business Machines Corporation Asynchronous TMR processing system
US5550736A (en) * 1993-04-27 1996-08-27 Honeywell Inc. Fail-operational fault tolerant flight critical computer architecture and monitoring method
US5812757A (en) * 1993-10-08 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Processing board, a computer, and a fault recovery method for the computer
US6112140A (en) * 1996-05-14 2000-08-29 The Boeing Company Flight management system providing for automatic control display unit backup utilizing structured data routing
US5903717A (en) * 1997-04-02 1999-05-11 General Dynamics Information Systems, Inc. Fault tolerant computer system
US5923830A (en) * 1997-05-07 1999-07-13 General Dynamics Information Systems, Inc. Non-interrupting power control for fault tolerant computer systems
FR2774359B1 (en) * 1998-01-30 2000-04-07 Aerospatiale ENGINE CONTROL SYSTEM FOR AIRCRAFT
US6085350A (en) * 1998-03-04 2000-07-04 Motorola, Inc. Single event upset tolerant system and method
FR2803057B1 (en) * 1999-12-22 2002-11-29 Centre Nat Etd Spatiales COMPUTER SYSTEM TOLERANT TO TRANSIENT ERRORS AND MANAGEMENT METHOD IN SUCH A SYSTEM
US6532550B1 (en) * 2000-02-10 2003-03-11 Westinghouse Electric Company Llc Process protection system
US6732300B1 (en) * 2000-02-18 2004-05-04 Lev Freydel Hybrid triple redundant computer system
US6550018B1 (en) * 2000-02-18 2003-04-15 The University Of Akron Hybrid multiple redundant computer system
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6704887B2 (en) * 2001-03-08 2004-03-09 The United States Of America As Represented By The Secretary Of The Air Force Method and apparatus for improved security in distributed-environment voting
US7065672B2 (en) * 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
US6971043B2 (en) * 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6862693B2 (en) * 2001-04-13 2005-03-01 Sun Microsystems, Inc. Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step
US6839866B2 (en) * 2001-05-31 2005-01-04 Sycamore Networks, Inc. System and method for the use of reset logic in high availability systems
US6938183B2 (en) * 2001-09-21 2005-08-30 The Boeing Company Fault tolerant processing architecture
US6667520B1 (en) * 2002-11-21 2003-12-23 Honeywell International Inc. SEU hard majority voter for triple redundancy
US7260742B2 (en) * 2003-01-28 2007-08-21 Czajkowski David R SEU and SEFI fault tolerant computer
US7047440B1 (en) * 2004-07-27 2006-05-16 Freydel Lev R Dual/triple redundant computer system
US20060200278A1 (en) * 2005-03-02 2006-09-07 Honeywell International Inc. Generic software fault mitigation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274554A (en) * 1991-02-01 1993-12-28 The Boeing Company Multiple-voting fault detection system for flight critical actuation control systems
EP1014237A1 (en) * 1998-12-17 2000-06-28 Honeywell Inc. Modular computer architecture

Also Published As

Publication number Publication date
EP1759293A2 (en) 2007-03-07
WO2006002069A2 (en) 2006-01-05
JP2008503002A (en) 2008-01-31
US20050278567A1 (en) 2005-12-15
US7392426B2 (en) 2008-06-24

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