WO2006004826A3 - Apparatus and method for fine-grained multithreading in a multipipelined processor core - Google Patents

Apparatus and method for fine-grained multithreading in a multipipelined processor core Download PDF

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Publication number
WO2006004826A3
WO2006004826A3 PCT/US2005/023077 US2005023077W WO2006004826A3 WO 2006004826 A3 WO2006004826 A3 WO 2006004826A3 US 2005023077 W US2005023077 W US 2005023077W WO 2006004826 A3 WO2006004826 A3 WO 2006004826A3
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WO
WIPO (PCT)
Prior art keywords
multipipelined
fine
processor core
threads
processor
Prior art date
Application number
PCT/US2005/023077
Other languages
French (fr)
Other versions
WO2006004826A2 (en
Inventor
Ricky C Hetherington
Gregory F Grohoski
Robert T Golla
Original Assignee
Sun Microsystems Inc
Ricky C Hetherington
Gregory F Grohoski
Robert T Golla
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc, Ricky C Hetherington, Gregory F Grohoski, Robert T Golla filed Critical Sun Microsystems Inc
Priority to EP05763865A priority Critical patent/EP1782194A2/en
Publication of WO2006004826A2 publication Critical patent/WO2006004826A2/en
Publication of WO2006004826A3 publication Critical patent/WO2006004826A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Abstract

An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.
PCT/US2005/023077 2004-06-30 2005-06-30 Apparatus and method for fine-grained multithreading in a multipipelined processor core WO2006004826A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05763865A EP1782194A2 (en) 2004-06-30 2005-06-30 Apparatus and method for fine-grained multithreading in a multipipelined processor core

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/880,488 US7401206B2 (en) 2004-06-30 2004-06-30 Apparatus and method for fine-grained multithreading in a multipipelined processor core
US10/880,488 2004-06-30

Publications (2)

Publication Number Publication Date
WO2006004826A2 WO2006004826A2 (en) 2006-01-12
WO2006004826A3 true WO2006004826A3 (en) 2006-03-23

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Country Status (3)

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US (1) US7401206B2 (en)
EP (1) EP1782194A2 (en)
WO (1) WO2006004826A2 (en)

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US7401206B2 (en) 2008-07-15
US20060004995A1 (en) 2006-01-05
EP1782194A2 (en) 2007-05-09
WO2006004826A2 (en) 2006-01-12

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