WO2006006119A1 - Integrated doherty type amplifier arrangement with integrated feedback - Google Patents

Integrated doherty type amplifier arrangement with integrated feedback Download PDF

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Publication number
WO2006006119A1
WO2006006119A1 PCT/IB2005/052218 IB2005052218W WO2006006119A1 WO 2006006119 A1 WO2006006119 A1 WO 2006006119A1 IB 2005052218 W IB2005052218 W IB 2005052218W WO 2006006119 A1 WO2006006119 A1 WO 2006006119A1
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Prior art keywords
signal
amplifier
output
input
peak
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PCT/IB2005/052218
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French (fr)
Inventor
Igor Blednov
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Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006006119A1 publication Critical patent/WO2006006119A1/en

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    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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Definitions

  • the present invention relates to an integrated Doherty type amplifier arrangement and a method of amplifying an input signal of such a Doherty type amplifier arrangement.
  • the Doherty amplifier schema achieves high linear efficiency by having a first amplifier (main amplifier or carrier amplifier) operated at a point where the output begins to saturate and where the highest linear efficiency is obtained. Additionally, a second amplifier (peak amplifier or auxiliary amplifier) is used to affect the first so that overall linearity can be maintained as it is driven beyond this saturation point.
  • the Doherty amplifier's operation can thus be divided into two main regions. In the first region, the input power is less than the peak amplifier's threshold and only the carrier amplifier supplies the output power to the load with the efficiency determined by its mode of operation, i.e. AB-class, B-class, F-class or E- class, which defines the location of the bias working point of the amplifier.
  • the peak amplifier starts to operate and this mark is the beginning of the second region.
  • the power supplied by the peak amplifier effectively reduces the output load impedance seen by the carrier amplifier. This impedance reduction enables the carrier amplifier to deliver more power to the load while its voltage remains saturated. In this way, the maximum efficiency of the carrier amplifier and hence the overall Doherty amplifier is maintained throughout the region until the peak amplifier reaches its saturation.
  • variable input impedances of the power devices especially when used in C-class operating mode (with bias providing conducting angle less that 180 degrees), which is often the case for the peak amplifier, lead to amplitude and phase distortions depending on the power level, which its extremely detrimental for code multiplex system, such as Wideband Code Division Multiple Access (WCDMA) communication systems.
  • WCDMA Wideband Code Division Multiple Access
  • the Doherty technique requires use of similar devices in the carrier (or main) and peak amplifiers to provide best linearity, but, on the other hand, both power devices are operating in different modes, e.g. the main amplifier in AB-class and the peak amplifier in C-class, which cause large differences in power gain. Moreover, in C-class mode, a variable input impedance can be observed in dependence on the input power level. These bottlenecks lead to the drawbacks that the Doherty amplifier's characteristic shows a poor "turn-on" property, low AM-AM stability and less power efficiency. In addition, the power-dependent gain introduces increased output amplitude modulations based on input amplitude modulations (i.e.
  • AM-AM distortions in the active range of the main and peak amplifiers, due to the fact that the peak amplifier operating in C-class has a lower gain and also because the load impedance at the main amplifier output drops in the power region when Peak Amplifier becomes active due to the Doherty principal.
  • Additional power-dependent distortions such as output phase modulations based on input amplitude modulations (i.e. AM-PM distortions), arise from the variable input impedance and resulting power-dependent input reflection coefficient.
  • Doherty amplifier arrangement by means of which a compact design with improved stability of AM-AM and AM-PM characteristics and turn-on speed can be obtained.
  • the integrated feedback from the output side of the Doherty type amplifier arrangement to the input side provides an internal bias control loop which is fed from the own output of the Doherty type amplifier arrangement.
  • a larger control signal is used which incorporates information about the performance of the main amplifier.
  • the internal feedback provides better conditions for fast regulation, reduced turn-on delay, compact design and lower costs.
  • the proposed internal bias control functions as a feedback loop and thus provides better performance of the Doherty amplifier.
  • the main and peak amplifier stages may comprise at least one of bipolar devices (BJT), metal oxide semiconductors (MOS), LDMOST , field effect transistors, and HBT. Using these elements a compact design of the amplifier arrangement can be ensured. Furthermore, an outside or integrated lumped element hybrid power divider means may be provided for deriving the first and second signals from the input signal, wherein the power divider means may be built with bond wires or deposited inductances and capacitances. The use of bond wires provides the advantage that power loss is avoided in the lumped elements. On the other hand, the use of deposited capacitances provides the advantage that parasitic capacitances can be considered or integrated as a part of the lumped elements. In general, both solutions serve to shrink the circuit size for integration.
  • the integrated feedback means may comprise at least one first bond wire provided in an output compensation circuit, wherein the at least one first bond wire may be arranged to provide a predetermined coupling to at least one second bond wire provided in an input matching circuit.
  • the integrated feedback means may be arranged to generate a bias signal in response to the first output signal, and to supply the bias signal to a control terminal of the peak amplifier stage.
  • This internal feedback solution also serves to improve performance of the Doherty type amplifier arrangement with respect to gain, linearity, AM-PM distortions and input impedance.
  • the generation function of the bias signal provides an additional opportunity to control these characteristics to some extent.
  • the integrated feedback means may comprise power detecting means coupled to an output of the main amplifier stage.
  • these power detecting means may be coupled to at least one third bond wire provided in an output artificial line structure connected to an output of the main amplifier stage. This structure ensures a compact size of the proposed amplifier arrangement with integrated feedback.
  • the power detecting means may for example be coupled to at least one capacitor provided in an output artificial line structure connected to an output of the main amplifier stage.
  • the power detecting means may have a frequency response adapted to the bandwidth of a modulation signal or an RF signal envelope of the first output signal or may have a special response to serve for required optimal performance of the Doherty amplifier. Thereby, the frequency response can be made equal to that of the modulation bandwidth, so as to ensure proper feedback operation.
  • the power detecting means may comprise a circuitry which provides an envelope signal processing in a way to improve at least one or optimize both of linearity and power efficiency of said amplifier arrangement.
  • Fig. 1 shows a schematic block diagram of a Doherty type amplifier arrangement in which the preferred embodiments can be implemented
  • Fig. 2 shows a schematic circuit diagram of an integrated Doherty type amplifier arrangement with integrated feedback according to the first preferred embodiment
  • Fig. 3 shows a sectional view of an implementation example of a Doherty type amplifier circuit according to the first preferred embodiment
  • Figs. 4A to 4C show diagrams indicating the effect of integrated feedback on input impedance and AM-PM characteristic at different coupling coefficients
  • Fig. 5 shows a diagram indicating turn-on characteristics with and without internal feedback
  • Fig. 6 shows an implementation example of the first preferred embodiment
  • Fig. 7 shows a schematic circuit diagram of an integrated Doherty type amplifier arrangement with integrated feedback according to the second preferred embodiment
  • Fig. 8 shows an implementation example of the second preferred embodiment.
  • MMIC Monitoring Microwave Integrated Circuit
  • RF radio frequency
  • power amplifiers are used in transmitter stages, where the modulated RF signal is amplified before being supplied to the antenna for wireless transmission. These power amplifiers are the most power consuming part of these RF transceivers. Using a Doherty type amplifier arrangement, a highly efficient power amplifier can be provided.
  • a Doherty structure is used, where circuit size is reduced for integration by using lumped elements to replace distributed circuit like power splitters and transmission lines. Furthermore, inductive coupling is used to increase inductance values and output parasitic capacitances are used as a part of lumped element artificial lines. Moreover, to avoid power losses in lumped elements and provide stable characteristic impedance in a wide frequency band including 2fo...nfo harmonics of fundamental signal, bond wires are suggested to be used at least partly as inductances. Bond wires provide very high parasitic parallel resonance frequency, e.g. above 15 GHz , as lumped inductance suitable for building a wideband lumped element equivalent of an RF transmission line. Fig.
  • FIG. 1 shows a schematic circuit diagram of an integrated Doherty type amplifier in MMIC technology, where an input signal received at an input terminal 5 is supplied to a lumped element hybrid power divider 12 provided for splitting the input signal to a carrier or main amplifier 20 and at least one peak amplifier 30.
  • two peak amplifiers 30 are used to support the operation of the main amplifier 20.
  • the output signals of the main amplifier 20 and the two peak amplifiers 30 are supplied to an output network which comprises a lumped element artificial line Zl.
  • the output network serves to combine the output signals of the main and peak amplifiers 20, 30 so as to generate a single amplified output signal supplied to an output terminal 15.
  • non-equal power splitting can be performed in the hybrid power divider 12.
  • the hybrid power divider 12 provides enhanced isolation between the input ports or gates of the main and peak amplifiers 20, 30.
  • the linearity versus efficiency characteristic of the Doherty type amplifier arrangement can be optimized by using a phase control at the input of the main and peak amplifiers 20, 30 and by using dynamic bias voltages to control the peak amplifiers 30.
  • the required power distribution can be provided by establishing the non-equal power division at the hybrids of the input network 10.
  • the lumped element hybrid coupler 12 has two input and two output ports.
  • the lower input port is grounded via a predetermined load resistor which may correspond to the characteristic impedance of the MMIC line system, e.g. a strip line or micro strip system.
  • the input signal at the input port 5 its supplied to the upper input port of the hybrid coupler 12 which upper output port is connected at a 0° phase shift to the main amplifier 20, while its lower output port is connected at a 90° phase shift to the input ports of the peak amplifiers 30.
  • the hybrid coupler 12 can provide an arbitrary power division between the main amplifier 20 and the peak amplifiers 30, which allows flexibility in optimization of the Doherty performance.
  • the output signal of the main amplifier 20 is matched in phase by a ⁇ /4 transmission line Zl, after which the respective output signals of the peak amplifiers 30 are combined with the suitably delayed output signal of the main amplifier 20 to generate the combined output signal available at the output terminal 15.
  • the main amplifier 20 and the two peak amplifiers 30 each may comprise a power device in bipolar technology, MOS (Metal Oxide Semiconductor) technology,
  • LDMOST Longeral Defused Metal Oxide Semiconductor Transistor
  • FET Field Effect Transistor
  • HBT Heterojunction Bipolar Transistor
  • Fig. 2 shows a simplified schematic block diagram of an integrated Doherty transistor package with a main amplifier 20 and a peak amplifier 30 with internal feedback functionality 38 according to the first preferred embodiment.
  • the Doherty structure is arranged as a discrete power transistor package having one or more input leads 22, 32 for the respective dies of the main amplifier 20 and the peak amplifier 30.
  • a one- step or one-stage pre-matching circuit 24 is provided at the input of the main amplifier 20 and arranged as an integrated structure of bond wires and capacitors.
  • a lumped equivalent circuit of a ⁇ /4 or 90° transmission line is provided at the output of the main amplifier 20 .
  • a first and second step or stage 34, 36 of another pre-matching circuit is provided at the input of the peak amplifier 30 and may also be arranged as an integrated structure of bond wires and capacitors.
  • post-matching circuits (not shown) may be provided, which can also be implemented as an integrated structure of bond wires and capacitors.
  • the pre- and post- matching circuits are used to provide an impedance matching at the inputs and outputs of the main and peak amplifiers 20, 30.
  • the lumped equivalent circuit of the 90° transmission line may have a ⁇ -type structure with two parallel capacitors and one serial inductor.
  • the parallel capacitors may correspond to the output capacitances of the main amplifier 20 and the peak amplifier 30, respectively, to thereby obtain a compact arrangement which may consist solely of a bond wire corresponding to the serial inductor.
  • an output lead 28 is provide to supply the output signal to the output terminal 15 shown in Fig. 1.
  • the feedback functionality 38 is obtained by providing a predetermined coupling between at least one bond wire of the second stage 36 of the pre-matching circuit at the input of the peak amplifier 30 and at least one bond wire of the post-matching circuit at the output of the peak amplifier circuit 30.
  • Fig. 3 shows a cross section of an MMIC implementation example of the
  • Doherty type transistor package of Fig. 2 along a line passing through the peak amplifier 30 and its input lead 32.
  • the input signal is supplied to the input lead 32 on the left side of Fig. 3, wherein the first and second plate-like structures from the left of Fig. 3 correspond to respective capacitors Cg2, and CgI and Ci of the respective pre- and post-matching circuits, and the bold lines correspond to respective bond inductors Lg3, Lg2, LgI, Li, and Ld.
  • the second plate-like structure combines the two capacitors Cgland Cgi. At the bottom of Fig.
  • a corresponding equivalent circuit diagram is shown, where the bond inductor Lg3 and the capacitor Cg2 form the first stage 34 of the pre-matching circuit, and the bond inductor Lg2 and the capacitor CgI form the second stage 36 of the pre-matching circuit.
  • the third plate-like structure from the left of Fig. 3 corresponds to the die of the peak amplifier 30, and the forth plat-like structure corresponds to an additional common capacitor and power combining bar which is not shown in the equivalent circuit diagram.
  • the bond inductors Li, Ld and the capacitor Ci form the post-matching circuit which is connected to the output lead 28. A compact circuit design can thus be achieved. As can be gathered from Fig.
  • the bond wire of the bond inductor LgI of the second stage 36 of the pre-matching circuit and the bond wire of the bond inductor Li of the post-matching circuit are arranged or routed in close proximity to provide a coupling area 72 by which a mutual coupling effect with a predetermined coupling factor or coefficient K between the output signal of the peak amplifier 30 and the input or gate of the peak amplifier 30 can be achieved.
  • the coupling strength can be controlled or modified by changing the distance and direction of the bond wires in the coupling area 72.
  • other suitable measures of decreasing or increasing the coupling coefficient K can be used to control the amount of feedback.
  • the relative angle between the bond wire can be changed to control mutual coupling.
  • the adaptive feedback function obtained by the mutual coupling effect leads to an improved Doherty characteristic with improved gain and AM-PM characteristic, increased input impedance and improved RP turn-on characteristic of the peak amplifier 30. Figs.
  • 4A to 4C show diagrams indicating effects of the proposed feedback or coupling functionality 38 between the bond inductors Li and LgI on the power-dependent characteristic of the input impedance (left-hand diagrams) and the power-dependent characteristic of the AM-PM distortions (right-hand diagrams) of the Doherty transistor package with the main amplifier 20 in AB-class mode.
  • the upper curve indicates the real portion of the complex input impedance
  • the lower curve indicates the imaginary portion of the complex input impedance.
  • the real part and thus ohmic component of the input impedance can be increased by increasing the coupling coefficient K.
  • the negative coupling coefficient corresponds to a decrease in coupling and thus leads to a reduction of the input impedance.
  • the right-hand diagrams of the AM-PM distortion characteristic indicate that AM-PM distortions are reduced with increased coupling coefficient K and increased with reduced (or increased negative) coupling coefficient K.
  • Fig. 5 shows a diagram indicating the turn-on characteristic of a C-class transistor of the peak amplifier 30. In particular, Fig 5 shows the dependency of the power gain Gp from the input power level Pin supplied to the input terminal 5.
  • the lower curve Kl corresponds to a conventional C-class transistor performance without integrated feedback functionality
  • the upper curve K2 corresponds to the proposed C-class transistor performance with introduced integrated feedback functionality of the peak amplifier 30.
  • the upper curve K2 indicates a higher power gain Gp with steep slope and thus steep or fast turn- on characteristic.
  • Fig. 6 shows a plain view on the implementation example of the Doherty type transistor package according to Fig. 2.
  • the other input lead 22 the die of the main amplifier 20, the on-stage pre-matching circuit 24 (which is arranged as an L-C-L configuration consisting of two serial bond inductors and a parallel capacitor), and the lumped equivalent circuit Zl of the 90° transmission line, which is formed by bond wires and arranged as an artificial C-L-C ⁇ -type circuit.
  • the common capacitor and power combining bar 27 mentioned in connection with Fig. 3 is also shown.
  • the encircled portion in the right-hand portion of the circuit diagram indicates the plate-like structure which is used as a combined capacitor consisting of the capacitor Ci of the post-matching circuit and the capacitor CgI of the second stage 36 of the pre-matching circuit of the peak amplifier 30.
  • the relative connection positions of the bond wires of the bond inductors LgI and Li can be shifted to obtain a predetermined coupling coefficient K which defines the amount of feedback at the peak amplifier 30.
  • a plurality of parallel bond wires are provided in the present example of the first preferred embodiment to form the respective bond inductors and lumped equivalent circuit of the 90° transmission line.
  • the number and size of these bond wires depends on the desired characteristic of the Doherty transistor.
  • a compact feedback functionality can be provided by arranging input and output bond wires close together to provide a predetermined coupling coefficient K and thus a predetermined amount of feedback.
  • the coupling coefficient K can be varied by changing the mutual spatial arrangement of the bond wires at the coupling area.
  • Figs. 7 and 8 wherein an integrated envelope signal feedback functionality 74 is arranged between the output of main amplifier 20 and the input of the peak amplifier 30, to thereby provide a dynamic bias control for the peak amplifier 30.
  • Fig. 7 shows a simplified schematic block diagram of an integrated Doherty transistor package similar to Fig. 2.
  • an inductive or magnetic coupling element Tl is provided, which may be achieved e.g. by arranging two bond wires or two inductors in close proximity.
  • the coupling element Tl serves to extract at least a portion of the output signal of the main amplifier 20 and to supply this extracted portion to a rectifying or detection circuit consisting in the most simple case at least of a diode Dl and a capacitor Cl connected to a reference potential, e.g.
  • an envelope feedback control circuit 74 with a power detection functionality, which generates based on the power of the received envelope signal a predetermined bias signal to be supplied to the gate or input of the peak amplifier 30.
  • the feedback control circuit 74 may be arranged to provide a frequency response modified or identical to that of the modulation signal bandwidth or bandwidth of the RF signal envelope of the input signal supplied to the Doherty transistor package.
  • the feedback control circuit 74 may include a processing circuit which provides an envelope signal processing, e.g. amplitude or phase processing, in a way to improve at least one of linearity and power efficiency of the Doherty transistor package.
  • the coupling coefficient K can be controlled by the feedback control circuit 74 to improve the performance of the integrated Doherty transistor package.
  • the RF envelope signal detection at the output of the main amplifier 20 is used for dynamic bias control at the input of the peak amplifier 30. This provides the advantage that a C-class operation mode with such an envelope feedback provides abrupt increase of the slope in the turn-on characteristic at a specific level of the input power, and higher maximal gain in the diagram of Fig. 5.
  • Fig. 9 shows a plain view on the MMIC implementation example of the Doherty type transistor package according to the second preferred embodiment. Only the differences with respect to the arrangement of Fig. 6 shall be described here for reasons of brevity.
  • the feedback functionality is connected between a bond wire of the lumped equivalent circuit Zl of the 90° transmission line and the die of combined capacitor plate of the capacitors Ci and CgI.
  • the integrated feedback bias control according to the second preferred embodiment is combined with the coupled bond wire feedback at the bond inductors Li and LgI of the peak amplifier 30. According to Fig.
  • the coupling element Tl is obtained by arranging a bond wire of the envelope feedback control circuit 74 in close proximity to a bond wire of the lumped equivalent circuit Zl of the 90° transmission line.
  • the extracted signal component is rectified by a corresponding integrated diode element and capacitor plate(s), and the envelope signal is supplied to via the feedback control circuit 74 to the combined capacitor plate at the input of the peak amplifier 30.
  • the feedback control circuit 74 may be a simple semiconductor or resistor element or circuit for generating a bias signal of a predetermined amplitude and/or phase.
  • the feedback control circuit 74 may be an integrated circuit arrangement which provides predetermined processing functions, as explained above.
  • the described integrated feedback functionalities of the first and second preferred embodiments alone or in combination provide the advantages of improved gain, linearity, input impedance and reduced AM-PM or AM-AM distortions. Moreover, a control functionality for controlling these characteristics is provided. At positive feedback of the bond wire coupling according to the first preferred embodiment, increased gain and improved turn-on characteristic of the C-class transistor can be achieved, which in case of AB-class mode of operation would have led to a stable oscillation.
  • an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement wherein a first signal, derived from an input signal, is amplified in a main amplifying path to generate a first output signal, and an operation of a peak amplifying path for amplifying a second signal, derived from the input signal, to generate a second output signal, is started when the level of the second signal has reached a predetermined threshold. A predetermined portion of at least one of the first and second output signals is supplied to an input of the peak amplifying path.
  • This integrated feedback provides the advantage that gain, linearity and input impedance can be controlled to improve performance of the integrated Doherty type amplifier arrangement.
  • the present invention is not restricted to the above preferred embodiments, but can be used in any kind of single-stage or multiple-stage Doherty type amplifier arrangement.
  • any other type of coupling functionality can be used in the first and second preferred embodiments to achieve the desired integrated feedback.
  • the preferred embodiment may be used as a building block device for high power Doherty amplifiers when connected in parallel within a high power RF transistor package, for power levels above 10OW, for example.

Abstract

The present invention relates to an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement, wherein a first signal, derived from an input signal, is amplified in a main amplifying path (20) to generate a first output signal, and an operation of a peak amplifying path (30) for amplifying a second signal, derived from the input signal, to generate a second output signal, is started when the level of the second signal has reached a predetermined threshold. A predetermined portion of at least one of the first and second output signals is supplied to an input of the peak amplifying path (70). This integrated feedback (38) provides the advantage that gain, linearity and input impedance can be controlled to improve performance of the integrated Doherty type amplifier arrangement.

Description

Integrated Doherty type amplifier arrangement with integrated feedback
The present invention relates to an integrated Doherty type amplifier arrangement and a method of amplifying an input signal of such a Doherty type amplifier arrangement.
In recent years, there has been a strong demand to improve the efficiency of power amplifiers for wireless communications. The use of the Doherty technique allows to maintain the efficiency of the power amplifier across a wide range of input power variation. The Doherty amplifier was first suggested by W.H. Doherty in 1936 and is discussed in a technical paper and titled "A New High Efficiency Power Amplifier For Modulated Waves", W.H. Doherty, Proceedings of the Institute of Radio Engineers, Vol. 24, No. 9, Sept. 1936. Originally intended for use in low to medium frequency amplitude modulated broadcasting transmitters, the suggested scheme can be modified and updated to increase efficiency of high frequency power amplifiers.
In a conventional amplifier there is a direct relationship between efficiency and input drive level. Therefore, high efficiency is not attained until the high frequency input power becomes sufficiently high to drive the amplifier into saturation. Since in multi-carrier communications systems an amplifier must remain as linear as possible in order to avoid intermodulation distortion, this region of high efficiency cannot be used.
The Doherty amplifier schema achieves high linear efficiency by having a first amplifier (main amplifier or carrier amplifier) operated at a point where the output begins to saturate and where the highest linear efficiency is obtained. Additionally, a second amplifier (peak amplifier or auxiliary amplifier) is used to affect the first so that overall linearity can be maintained as it is driven beyond this saturation point. The Doherty amplifier's operation can thus be divided into two main regions. In the first region, the input power is less than the peak amplifier's threshold and only the carrier amplifier supplies the output power to the load with the efficiency determined by its mode of operation, i.e. AB-class, B-class, F-class or E- class, which defines the location of the bias working point of the amplifier. As the input drive voltage or power increases further to a level just before the carrier amplifier becomes saturated, i.e. the point where the peak efficiency is obtained, the peak amplifier starts to operate and this mark is the beginning of the second region. Through the connection of a quarter-wave transformer, the power supplied by the peak amplifier effectively reduces the output load impedance seen by the carrier amplifier. This impedance reduction enables the carrier amplifier to deliver more power to the load while its voltage remains saturated. In this way, the maximum efficiency of the carrier amplifier and hence the overall Doherty amplifier is maintained throughout the region until the peak amplifier reaches its saturation. However, variable input impedances of the power devices especially when used in C-class operating mode (with bias providing conducting angle less that 180 degrees), which is often the case for the peak amplifier, lead to amplitude and phase distortions depending on the power level, which its extremely detrimental for code multiplex system, such as Wideband Code Division Multiple Access (WCDMA) communication systems. Furthermore, the variable input impedances lead to power reflections from the input of the power devices operating in the peak and main amplifiers and this results in an undesirable mutual influence or coupling effect.
On one hand, the Doherty technique requires use of similar devices in the carrier (or main) and peak amplifiers to provide best linearity, but, on the other hand, both power devices are operating in different modes, e.g. the main amplifier in AB-class and the peak amplifier in C-class, which cause large differences in power gain. Moreover, in C-class mode, a variable input impedance can be observed in dependence on the input power level. These bottlenecks lead to the drawbacks that the Doherty amplifier's characteristic shows a poor "turn-on" property, low AM-AM stability and less power efficiency. In addition, the power-dependent gain introduces increased output amplitude modulations based on input amplitude modulations (i.e. AM-AM distortions) in the active range of the main and peak amplifiers, due to the fact that the peak amplifier operating in C-class has a lower gain and also because the load impedance at the main amplifier output drops in the power region when Peak Amplifier becomes active due to the Doherty principal. Additional power-dependent distortions, such as output phase modulations based on input amplitude modulations (i.e. AM-PM distortions), arise from the variable input impedance and resulting power-dependent input reflection coefficient.
In the article "An Adaptive Bias Controlled Power Amplifier with a Load- Modulated Combining Scheme for High Efficiency and Linearity" by Jeonghyeon Cha et al, IEEE MTT-S Digest, pp 81-84, 2003, a Doherty type amplifier arrangement with external non-integrated adaptive bias control circuit is described. The bias control circuit serves to improve efficiency by controlling the gate biases of the main and peak amplifiers according to the envelope of the input signal of the Doherty type amplifier arrangement. Due to the adaptively controlled biases, efficiency and linearity of the Doherty technique can be improved.
However, the additional external bias control circuit increases complexity and costs of the circuit and requires an undesirable amount of additional space which leads to a bulky circuit design. Furthermore, the above prior art document does not address the problems of poor "turn-on" property and AM- AM/ AM-PM characteristics distortions faced by the above bottlenecks.
It is therefore an object of the present invention to provide an improved
Doherty amplifier arrangement, by means of which a compact design with improved stability of AM-AM and AM-PM characteristics and turn-on speed can be obtained.
This object its achieved by an integrated Doherty type amplifier arrangement as claimed in claim 1 and by a method of amplifying an input signal, as claimed in claim 11. Accordingly, the integrated feedback from the output side of the Doherty type amplifier arrangement to the input side provides an internal bias control loop which is fed from the own output of the Doherty type amplifier arrangement. Thereby, a larger control signal is used which incorporates information about the performance of the main amplifier. Additionally, the internal feedback provides better conditions for fast regulation, reduced turn-on delay, compact design and lower costs. Furthermore, the proposed internal bias control functions as a feedback loop and thus provides better performance of the Doherty amplifier.
The main and peak amplifier stages may comprise at least one of bipolar devices (BJT), metal oxide semiconductors (MOS), LDMOST , field effect transistors, and HBT. Using these elements a compact design of the amplifier arrangement can be ensured. Furthermore, an outside or integrated lumped element hybrid power divider means may be provided for deriving the first and second signals from the input signal, wherein the power divider means may be built with bond wires or deposited inductances and capacitances. The use of bond wires provides the advantage that power loss is avoided in the lumped elements. On the other hand, the use of deposited capacitances provides the advantage that parasitic capacitances can be considered or integrated as a part of the lumped elements. In general, both solutions serve to shrink the circuit size for integration.
According to a first aspect, the integrated feedback means may comprise at least one first bond wire provided in an output compensation circuit, wherein the at least one first bond wire may be arranged to provide a predetermined coupling to at least one second bond wire provided in an input matching circuit. This approach ensures a very compact circuit design due to the fact that feedback coupling is provided simply by arranging bond wires in a manner to provide a predetermined coupling. Moreover, the bond- wire feedback improves the AM-PM characteristic and leads to an increased input impedance with improved turn-on characteristic of the peak amplifier.
According to a second aspect, the integrated feedback means may be arranged to generate a bias signal in response to the first output signal, and to supply the bias signal to a control terminal of the peak amplifier stage. This internal feedback solution also serves to improve performance of the Doherty type amplifier arrangement with respect to gain, linearity, AM-PM distortions and input impedance. The generation function of the bias signal provides an additional opportunity to control these characteristics to some extent. In particular, the integrated feedback means may comprise power detecting means coupled to an output of the main amplifier stage. As an example, these power detecting means may be coupled to at least one third bond wire provided in an output artificial line structure connected to an output of the main amplifier stage. This structure ensures a compact size of the proposed amplifier arrangement with integrated feedback. The power detecting means may for example be coupled to at least one capacitor provided in an output artificial line structure connected to an output of the main amplifier stage. This implementation example of the second aspect provides the advantage that the feedback circuit can be realized at minimum additional space requirements, since the extraction of the portion of the first output signal is obtained simply by bond- wire coupling or by use of the main amplifier cell.
The power detecting means may have a frequency response adapted to the bandwidth of a modulation signal or an RF signal envelope of the first output signal or may have a special response to serve for required optimal performance of the Doherty amplifier. Thereby, the frequency response can be made equal to that of the modulation bandwidth, so as to ensure proper feedback operation.
As a further optional feature, the power detecting means may comprise a circuitry which provides an envelope signal processing in a way to improve at least one or optimize both of linearity and power efficiency of said amplifier arrangement.
The present invention will now be described based on preferred embodiments with reference to the accompanying drawings, in which: Fig. 1 shows a schematic block diagram of a Doherty type amplifier arrangement in which the preferred embodiments can be implemented;
Fig. 2 shows a schematic circuit diagram of an integrated Doherty type amplifier arrangement with integrated feedback according to the first preferred embodiment; Fig. 3 shows a sectional view of an implementation example of a Doherty type amplifier circuit according to the first preferred embodiment;
Figs. 4A to 4C show diagrams indicating the effect of integrated feedback on input impedance and AM-PM characteristic at different coupling coefficients;
Fig. 5 shows a diagram indicating turn-on characteristics with and without internal feedback;
Fig. 6 shows an implementation example of the first preferred embodiment; Fig. 7 shows a schematic circuit diagram of an integrated Doherty type amplifier arrangement with integrated feedback according to the second preferred embodiment; and Fig. 8 shows an implementation example of the second preferred embodiment.
The preferred embodiments will now be described in connection with an MMIC (Monolithic Microwave Integrated Circuit) Technology, which may be used in a transceiver design of a wireless system or any other radio frequency (RF) system. The application of MMIC technology has enabled miniaturization of microwave and millimeter- wave systems, combined with increasing performance.
In mobile RF transceivers of emerging wireless systems such as WCDMA, CDMA2000 or Wireless Local Area Network (WLAN) systems according to the IEEE 802.11 (a)/(g) standard, power amplifiers are used in transmitter stages, where the modulated RF signal is amplified before being supplied to the antenna for wireless transmission. These power amplifiers are the most power consuming part of these RF transceivers. Using a Doherty type amplifier arrangement, a highly efficient power amplifier can be provided.
In the power amplifier arrangement according to the preferred embodiment a Doherty structure is used, where circuit size is reduced for integration by using lumped elements to replace distributed circuit like power splitters and transmission lines. Furthermore, inductive coupling is used to increase inductance values and output parasitic capacitances are used as a part of lumped element artificial lines. Moreover, to avoid power losses in lumped elements and provide stable characteristic impedance in a wide frequency band including 2fo...nfo harmonics of fundamental signal, bond wires are suggested to be used at least partly as inductances. Bond wires provide very high parasitic parallel resonance frequency, e.g. above 15 GHz , as lumped inductance suitable for building a wideband lumped element equivalent of an RF transmission line. Fig. 1 shows a schematic circuit diagram of an integrated Doherty type amplifier in MMIC technology, where an input signal received at an input terminal 5 is supplied to a lumped element hybrid power divider 12 provided for splitting the input signal to a carrier or main amplifier 20 and at least one peak amplifier 30. In the present example of Fig. 1, two peak amplifiers 30 are used to support the operation of the main amplifier 20. The output signals of the main amplifier 20 and the two peak amplifiers 30 are supplied to an output network which comprises a lumped element artificial line Zl. The output network serves to combine the output signals of the main and peak amplifiers 20, 30 so as to generate a single amplified output signal supplied to an output terminal 15. To compensate for the low gain of the peak amplifiers 30 which may operate in C-class mode, i.e. at a negative input bias, non-equal power splitting can be performed in the hybrid power divider 12.
Furthermore, to diminish the effect of variable input impedance of the peak amplifiers 30, the hybrid power divider 12 provides enhanced isolation between the input ports or gates of the main and peak amplifiers 20, 30.
The linearity versus efficiency characteristic of the Doherty type amplifier arrangement can be optimized by using a phase control at the input of the main and peak amplifiers 20, 30 and by using dynamic bias voltages to control the peak amplifiers 30. The required power distribution can be provided by establishing the non-equal power division at the hybrids of the input network 10.
The lumped element hybrid coupler 12 has two input and two output ports. The lower input port is grounded via a predetermined load resistor which may correspond to the characteristic impedance of the MMIC line system, e.g. a strip line or micro strip system. The input signal at the input port 5 its supplied to the upper input port of the hybrid coupler 12 which upper output port is connected at a 0° phase shift to the main amplifier 20, while its lower output port is connected at a 90° phase shift to the input ports of the peak amplifiers 30. The hybrid coupler 12 can provide an arbitrary power division between the main amplifier 20 and the peak amplifiers 30, which allows flexibility in optimization of the Doherty performance.
Before combining the output signals of the main amplifier 20 and the peak amplifiers 30 again, the output signal of the main amplifier 20 is matched in phase by a λ/4 transmission line Zl, after which the respective output signals of the peak amplifiers 30 are combined with the suitably delayed output signal of the main amplifier 20 to generate the combined output signal available at the output terminal 15.
The main amplifier 20 and the two peak amplifiers 30 each may comprise a power device in bipolar technology, MOS (Metal Oxide Semiconductor) technology,
LDMOST (Lateral Defused Metal Oxide Semiconductor Transistor) technology, FET (Field Effect Transistor) technology, or HBT (Heterojunction Bipolar Transistor) technology. The LDMOST technology provides high gain and good linearity compared to the other semiconductor technologies. However, complex modulation schemes, like WCDMA, make further device improvements for linearity still very desirable. Therefore, the suggested
Doherty type amplifier arrangement enhances the performance of the LDMOST technology or other RF power devices technologies mentioned above. For example, HBT MMIC power devices may be used, where the heterojunction increases breakdown voltage and minimizes leakage current between junctions. Fig. 2 shows a simplified schematic block diagram of an integrated Doherty transistor package with a main amplifier 20 and a peak amplifier 30 with internal feedback functionality 38 according to the first preferred embodiment. In the present example, the Doherty structure is arranged as a discrete power transistor package having one or more input leads 22, 32 for the respective dies of the main amplifier 20 and the peak amplifier 30. A one- step or one-stage pre-matching circuit 24 is provided at the input of the main amplifier 20 and arranged as an integrated structure of bond wires and capacitors. At the output of the main amplifier 20 a lumped equivalent circuit of a λ/4 or 90° transmission line is provided. Furthermore, a first and second step or stage 34, 36 of another pre-matching circuit is provided at the input of the peak amplifier 30 and may also be arranged as an integrated structure of bond wires and capacitors. At the respective outputs of the main and peak amplifiers 20, 30, post-matching circuits (not shown) may be provided, which can also be implemented as an integrated structure of bond wires and capacitors. The pre- and post- matching circuits are used to provide an impedance matching at the inputs and outputs of the main and peak amplifiers 20, 30. The lumped equivalent circuit of the 90° transmission line may have a π-type structure with two parallel capacitors and one serial inductor. The parallel capacitors may correspond to the output capacitances of the main amplifier 20 and the peak amplifier 30, respectively, to thereby obtain a compact arrangement which may consist solely of a bond wire corresponding to the serial inductor. At the output of the transistor package, an output lead 28 is provide to supply the output signal to the output terminal 15 shown in Fig. 1. In the present first preferred embodiment, the feedback functionality 38 is obtained by providing a predetermined coupling between at least one bond wire of the second stage 36 of the pre-matching circuit at the input of the peak amplifier 30 and at least one bond wire of the post-matching circuit at the output of the peak amplifier circuit 30. Fig. 3 shows a cross section of an MMIC implementation example of the
Doherty type transistor package of Fig. 2 along a line passing through the peak amplifier 30 and its input lead 32. The input signal is supplied to the input lead 32 on the left side of Fig. 3, wherein the first and second plate-like structures from the left of Fig. 3 correspond to respective capacitors Cg2, and CgI and Ci of the respective pre- and post-matching circuits, and the bold lines correspond to respective bond inductors Lg3, Lg2, LgI, Li, and Ld. It is noted that the second plate-like structure combines the two capacitors Cgland Cgi. At the bottom of Fig. 3, a corresponding equivalent circuit diagram is shown, where the bond inductor Lg3 and the capacitor Cg2 form the first stage 34 of the pre-matching circuit, and the bond inductor Lg2 and the capacitor CgI form the second stage 36 of the pre-matching circuit. The third plate-like structure from the left of Fig. 3 corresponds to the die of the peak amplifier 30, and the forth plat-like structure corresponds to an additional common capacitor and power combining bar which is not shown in the equivalent circuit diagram. The bond inductors Li, Ld and the capacitor Ci form the post-matching circuit which is connected to the output lead 28. A compact circuit design can thus be achieved. As can be gathered from Fig. 3, the bond wire of the bond inductor LgI of the second stage 36 of the pre-matching circuit and the bond wire of the bond inductor Li of the post-matching circuit are arranged or routed in close proximity to provide a coupling area 72 by which a mutual coupling effect with a predetermined coupling factor or coefficient K between the output signal of the peak amplifier 30 and the input or gate of the peak amplifier 30 can be achieved. The coupling strength can be controlled or modified by changing the distance and direction of the bond wires in the coupling area 72. A zero coupling coefficient K=O can be obtained for example if the bond wire of the bond inductor LgI is not directly connected to the bond wire of the bond inductor Lg2 but separated and connected at or near the right edge of the plate-like structure of the capacitors CgI and Ci to thereby obtain a large distance between the bond wires of the bond inductors Li and LgI. Of course, other suitable measures of decreasing or increasing the coupling coefficient K can be used to control the amount of feedback. For example, the relative angle between the bond wire can be changed to control mutual coupling. The adaptive feedback function obtained by the mutual coupling effect leads to an improved Doherty characteristic with improved gain and AM-PM characteristic, increased input impedance and improved RP turn-on characteristic of the peak amplifier 30. Figs. 4A to 4C show diagrams indicating effects of the proposed feedback or coupling functionality 38 between the bond inductors Li and LgI on the power-dependent characteristic of the input impedance (left-hand diagrams) and the power-dependent characteristic of the AM-PM distortions (right-hand diagrams) of the Doherty transistor package with the main amplifier 20 in AB-class mode. In the impedance characteristics, the upper curve indicates the real portion of the complex input impedance, while the lower curve indicates the imaginary portion of the complex input impedance. The negative coupling coefficient K=-0.5 indicates a 180° phase shift between the output signal and the signal component coupled via the coupling area 72 to the input of the peak amplifier 30. As can be gathered from the left-hand impedance diagrams, the real part and thus ohmic component of the input impedance can be increased by increasing the coupling coefficient K. The negative coupling coefficient corresponds to a decrease in coupling and thus leads to a reduction of the input impedance. On the other hand, the right-hand diagrams of the AM-PM distortion characteristic indicate that AM-PM distortions are reduced with increased coupling coefficient K and increased with reduced (or increased negative) coupling coefficient K. Fig. 5 shows a diagram indicating the turn-on characteristic of a C-class transistor of the peak amplifier 30. In particular, Fig 5 shows the dependency of the power gain Gp from the input power level Pin supplied to the input terminal 5. The lower curve Kl corresponds to a conventional C-class transistor performance without integrated feedback functionality, while the upper curve K2 corresponds to the proposed C-class transistor performance with introduced integrated feedback functionality of the peak amplifier 30. The upper curve K2 indicates a higher power gain Gp with steep slope and thus steep or fast turn- on characteristic.
Fig. 6 shows a plain view on the implementation example of the Doherty type transistor package according to Fig. 2. In addition to Fig. 2, the other input lead 22, the die of the main amplifier 20, the on-stage pre-matching circuit 24 (which is arranged as an L-C-L configuration consisting of two serial bond inductors and a parallel capacitor), and the lumped equivalent circuit Zl of the 90° transmission line, which is formed by bond wires and arranged as an artificial C-L-C π-type circuit. Furthermore, the common capacitor and power combining bar 27 mentioned in connection with Fig. 3 is also shown. The encircled portion in the right-hand portion of the circuit diagram indicates the plate-like structure which is used as a combined capacitor consisting of the capacitor Ci of the post-matching circuit and the capacitor CgI of the second stage 36 of the pre-matching circuit of the peak amplifier 30. As already mentioned, the relative connection positions of the bond wires of the bond inductors LgI and Li can be shifted to obtain a predetermined coupling coefficient K which defines the amount of feedback at the peak amplifier 30.
As can be gathered from Fig. 6, a plurality of parallel bond wires are provided in the present example of the first preferred embodiment to form the respective bond inductors and lumped equivalent circuit of the 90° transmission line. The number and size of these bond wires depends on the desired characteristic of the Doherty transistor. Thus, according to the first preferred embodiment, a compact feedback functionality can be provided by arranging input and output bond wires close together to provide a predetermined coupling coefficient K and thus a predetermined amount of feedback. The coupling coefficient K can be varied by changing the mutual spatial arrangement of the bond wires at the coupling area. In the following, a second preferred embodiment is described with reference to
Figs. 7 and 8, wherein an integrated envelope signal feedback functionality 74 is arranged between the output of main amplifier 20 and the input of the peak amplifier 30, to thereby provide a dynamic bias control for the peak amplifier 30.
Fig. 7 shows a simplified schematic block diagram of an integrated Doherty transistor package similar to Fig. 2. At the lumped equivalent circuit of the λ/4 or 90° transmission line, an inductive or magnetic coupling element Tl is provided, which may be achieved e.g. by arranging two bond wires or two inductors in close proximity. The coupling element Tl serves to extract at least a portion of the output signal of the main amplifier 20 and to supply this extracted portion to a rectifying or detection circuit consisting in the most simple case at least of a diode Dl and a capacitor Cl connected to a reference potential, e.g. ground potential, which generates a signal corresponding to the envelope of the extracted feedback signal VFB- AS an alternative, a capacitive coupling element or other extracting element may be used to obtain an extracted feedback signal VFB- The obtained envelope signal is supplied to an envelope feedback control circuit 74 with a power detection functionality, which generates based on the power of the received envelope signal a predetermined bias signal to be supplied to the gate or input of the peak amplifier 30. The feedback control circuit 74 may be arranged to provide a frequency response modified or identical to that of the modulation signal bandwidth or bandwidth of the RF signal envelope of the input signal supplied to the Doherty transistor package. Furthermore, the feedback control circuit 74 may include a processing circuit which provides an envelope signal processing, e.g. amplitude or phase processing, in a way to improve at least one of linearity and power efficiency of the Doherty transistor package.
Similar to the first preferred embodiment, the coupling coefficient K can be controlled by the feedback control circuit 74 to improve the performance of the integrated Doherty transistor package. The RF envelope signal detection at the output of the main amplifier 20 is used for dynamic bias control at the input of the peak amplifier 30. This provides the advantage that a C-class operation mode with such an envelope feedback provides abrupt increase of the slope in the turn-on characteristic at a specific level of the input power, and higher maximal gain in the diagram of Fig. 5.
Fig. 9 shows a plain view on the MMIC implementation example of the Doherty type transistor package according to the second preferred embodiment. Only the differences with respect to the arrangement of Fig. 6 shall be described here for reasons of brevity. The feedback functionality is connected between a bond wire of the lumped equivalent circuit Zl of the 90° transmission line and the die of combined capacitor plate of the capacitors Ci and CgI. Furthermore, in the implementation example shown in Fig. 8, the integrated feedback bias control according to the second preferred embodiment is combined with the coupled bond wire feedback at the bond inductors Li and LgI of the peak amplifier 30. According to Fig. 8, the coupling element Tl is obtained by arranging a bond wire of the envelope feedback control circuit 74 in close proximity to a bond wire of the lumped equivalent circuit Zl of the 90° transmission line. The extracted signal component is rectified by a corresponding integrated diode element and capacitor plate(s), and the envelope signal is supplied to via the feedback control circuit 74 to the combined capacitor plate at the input of the peak amplifier 30. It is noted that the feedback control circuit 74 may be a simple semiconductor or resistor element or circuit for generating a bias signal of a predetermined amplitude and/or phase. Alternatively, the feedback control circuit 74 may be an integrated circuit arrangement which provides predetermined processing functions, as explained above. Accordingly, the described integrated feedback functionalities of the first and second preferred embodiments alone or in combination provide the advantages of improved gain, linearity, input impedance and reduced AM-PM or AM-AM distortions. Moreover, a control functionality for controlling these characteristics is provided. At positive feedback of the bond wire coupling according to the first preferred embodiment, increased gain and improved turn-on characteristic of the C-class transistor can be achieved, which in case of AB-class mode of operation would have led to a stable oscillation.
In summary, an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement is described, wherein a first signal, derived from an input signal, is amplified in a main amplifying path to generate a first output signal, and an operation of a peak amplifying path for amplifying a second signal, derived from the input signal, to generate a second output signal, is started when the level of the second signal has reached a predetermined threshold. A predetermined portion of at least one of the first and second output signals is supplied to an input of the peak amplifying path. This integrated feedback provides the advantage that gain, linearity and input impedance can be controlled to improve performance of the integrated Doherty type amplifier arrangement.
It is to be noted that the present invention is not restricted to the above preferred embodiments, but can be used in any kind of single-stage or multiple-stage Doherty type amplifier arrangement. Furthermore, any other type of coupling functionality can be used in the first and second preferred embodiments to achieve the desired integrated feedback. The preferred embodiment may be used as a building block device for high power Doherty amplifiers when connected in parallel within a high power RF transistor package, for power levels above 10OW, for example.
It is further noted that the present invention is not limited to the above preferred embodiments and can be varied within the scope of the attached claims. In particular, the described drawing figures are only schematic and are not limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term 'comprising' is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g. 'a' or 'an', 'the', this includes a plural of that noun unless something else is specifically stated. The terms first, second, third and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. Moreover, although preferred embodiments, specific constructions and configurations have been discussed herein, various changes or modifications in form and detail may be made without departing from the scope of the attached claims.

Claims

CLAIMS:
1. An integrated Doherty type amplifier arrangement, comprising: a) a main amplifier stage (20) for receiving a first signal derived from an input signal and for amplifying the first signal to generate a first output signal; b) a peak amplifier stage (30) for receiving a second signal derived from said input signal, said peak amplifier stage (30) being arranged to start operating when the level of said second signal has reached a predetermined threshold, to generate a second output signal; and c) integrated feedback means (38; 74) for supplying a predetermined portion of at least one of said first and second output signals to an input of said peak amplifier stage (30).
2. An amplifier arrangement according to claim 1, wherein said main and peak amplifier stages (20, 30) comprise at least one of bipolar elements, metal oxide semiconductors, LDMOST elements, field effect transistors, and HBT elements.
3. An amplifier arrangement according to claim 1 or 2, further comprising an integrated lumped element hybrid power divider means (12) for deriving said first and second signals from said input signal, said power divider means being built with bond wires or deposited inductances and capacitances.
4. An amplifier arrangement according to any one of the preceding claims, wherein said integrated feedback means (38) comprise at least one first bond wire (Li) provided in an output compensation circuit, said at least one first bond wire (Li) being arranged to provide a predetermined coupling to at least one second bond wire (LgI) provided in an input matching circuit (36).
5. An amplifier arrangement according to claim any one of the preceding claims, wherein said integrated feedback means (74) is arranged to generate a bias signal in response to said first output signal, and to supply said bias signal to a control terminal of said peak amplifier stage (30).
6. An amplifier arrangement according to claim 5, wherein said integrated feedback means (74) comprise power detecting means (Tl, Dl, Cl) coupled to an output of said main amplifier stage (20).
7. An amplifier arrangement according to claim 6, wherein said power detecting means is coupled to at least one third bond wire provided in an output artificial line structure (Zl) connected to an output of said main amplifier stage (20).
8. An amplifier arrangement according to claim 6 or 7, wherein said power detecting means is coupled to at least one capacitor provided in an output artificial line structure (Zl) connected to an output of said main amplifier stage (20).
9. An amplifier arrangement according to any one of claims 6 to 8, wherein said power detecting means has a frequency response adapted to the bandwidth of a modulation signal or an RF signal envelope of said first output signal.
10. An amplifier arrangement according to any one of claims 6 to 9, wherein said power detecting means comprises a circuitry which provides an envelope signal processing in a way to improve at least one of linearity and power efficiency of said amplifier arrangement.
11. A method of amplifying an input signal in a Doherty type amplifier arrangement, said method comprising the steps of: a) amplifying a first signal, derived from said input signal, in a main amplifying path to generate a first output signal; b) starting operation of a peak amplifying path for amplifying a second signal, derived from said input signal, to generate a second output signal, when the level of said second signal has reached a predetermined threshold; and c) supplying a predetermined portion of at least one of said first and second output signals to an input of said peak amplifying path.
PCT/IB2005/052218 2004-07-08 2005-07-04 Integrated doherty type amplifier arrangement with integrated feedback WO2006006119A1 (en)

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006097893A2 (en) * 2005-03-18 2006-09-21 Nxp B.V. Method and system for output matching of rf transistors
WO2008062371A2 (en) * 2006-11-23 2008-05-29 Nxp B.V. Integrated doherty type amplifier arrangement with high power efficiency
WO2009027916A2 (en) * 2007-08-29 2009-03-05 Nxp B.V. Integrated doherty amplifier
WO2007122586A3 (en) * 2006-04-26 2009-09-11 Nxp B.V. A high power integrated rf amplifier
WO2010037212A1 (en) * 2008-09-30 2010-04-08 Nortel Networks Limited Enhanced doherty amplifier with bias supply modulation
EP2665181A1 (en) * 2012-05-17 2013-11-20 Nxp B.V. Amplifier circuit
EP2869463A1 (en) * 2013-10-31 2015-05-06 Nxp B.V. Doherty amplifier structure
EP3043470A1 (en) * 2015-01-09 2016-07-13 Kabushiki Kaisha Toshiba High frequency signal amplifying circuitry
EP3179628A3 (en) * 2015-12-11 2017-08-23 NXP USA, Inc. Amplifier devices with in-package transmission line combiner
US9831837B2 (en) 2014-11-05 2017-11-28 Qualcomm Incorporated Dynamic power divider circuits and methods
CN111404490A (en) * 2020-03-25 2020-07-10 上海洺太电子科技有限公司 Mixed continuous Doherty power amplifier
WO2020256554A1 (en) * 2019-06-19 2020-12-24 Ampleon Netherlands B.V. Amplifier having improved stability

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444418A (en) * 1994-07-29 1995-08-22 Motorola, Inc. Method and apparatus for feedforward power amplifying
US5880633A (en) * 1997-05-08 1999-03-09 Motorola, Inc. High efficiency power amplifier
US6356149B1 (en) * 2000-04-10 2002-03-12 Motorola, Inc. Tunable inductor circuit, phase tuning circuit and applications thereof
US6374092B1 (en) * 1999-12-04 2002-04-16 Motorola, Inc. Efficient multimode power amplifier
US20040082354A1 (en) * 2002-10-28 2004-04-29 Allen Cohen System and method for boosting signals in a cellular phone base station

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444418A (en) * 1994-07-29 1995-08-22 Motorola, Inc. Method and apparatus for feedforward power amplifying
US5880633A (en) * 1997-05-08 1999-03-09 Motorola, Inc. High efficiency power amplifier
US6374092B1 (en) * 1999-12-04 2002-04-16 Motorola, Inc. Efficient multimode power amplifier
US6356149B1 (en) * 2000-04-10 2002-03-12 Motorola, Inc. Tunable inductor circuit, phase tuning circuit and applications thereof
US20040082354A1 (en) * 2002-10-28 2004-04-29 Allen Cohen System and method for boosting signals in a cellular phone base station

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006097893A2 (en) * 2005-03-18 2006-09-21 Nxp B.V. Method and system for output matching of rf transistors
WO2006097893A3 (en) * 2005-03-18 2007-03-29 Koninkl Philips Electronics Nv Method and system for output matching of rf transistors
WO2007122586A3 (en) * 2006-04-26 2009-09-11 Nxp B.V. A high power integrated rf amplifier
US7898338B2 (en) 2006-04-26 2011-03-01 Nxp B.V. High power integrated RF amplifier
WO2008062371A2 (en) * 2006-11-23 2008-05-29 Nxp B.V. Integrated doherty type amplifier arrangement with high power efficiency
WO2008062371A3 (en) * 2006-11-23 2008-12-18 Nxp Bv Integrated doherty type amplifier arrangement with high power efficiency
WO2009027916A2 (en) * 2007-08-29 2009-03-05 Nxp B.V. Integrated doherty amplifier
WO2009027916A3 (en) * 2007-08-29 2009-04-30 Nxp Bv Integrated doherty amplifier
US8228123B2 (en) 2007-08-29 2012-07-24 Nxp B.V. Integrated Doherty amplifier
WO2010037212A1 (en) * 2008-09-30 2010-04-08 Nortel Networks Limited Enhanced doherty amplifier with bias supply modulation
US9071198B2 (en) 2012-05-17 2015-06-30 Nxp, B.V. Amplifier circuit
EP2665181A1 (en) * 2012-05-17 2013-11-20 Nxp B.V. Amplifier circuit
US9543914B2 (en) 2013-10-31 2017-01-10 Ampleon Netherlands B.V. Doherty amplifier structure
EP2869463A1 (en) * 2013-10-31 2015-05-06 Nxp B.V. Doherty amplifier structure
US9831837B2 (en) 2014-11-05 2017-11-28 Qualcomm Incorporated Dynamic power divider circuits and methods
US9748904B2 (en) 2015-01-09 2017-08-29 Kabushiki Kaisha Toshiba High frequency signal amplifying circuitry
EP3043470A1 (en) * 2015-01-09 2016-07-13 Kabushiki Kaisha Toshiba High frequency signal amplifying circuitry
EP3179628A3 (en) * 2015-12-11 2017-08-23 NXP USA, Inc. Amplifier devices with in-package transmission line combiner
WO2020256554A1 (en) * 2019-06-19 2020-12-24 Ampleon Netherlands B.V. Amplifier having improved stability
NL2023348B1 (en) * 2019-06-19 2021-01-27 Ampleon Netherlands Bv Amplifier having improved stability
CN113994589A (en) * 2019-06-19 2022-01-28 安普林荷兰有限公司 Amplifier with improved stability
US11482501B2 (en) 2019-06-19 2022-10-25 Ampleon Netherlands B.V. Amplifier having improved stability
CN113994589B (en) * 2019-06-19 2022-11-22 安普林荷兰有限公司 Amplifier with improved stability
CN111404490A (en) * 2020-03-25 2020-07-10 上海洺太电子科技有限公司 Mixed continuous Doherty power amplifier

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