WO2006017135A3 - Simulating multiported memories using memories with lower port count - Google Patents

Simulating multiported memories using memories with lower port count Download PDF

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Publication number
WO2006017135A3
WO2006017135A3 PCT/US2005/024164 US2005024164W WO2006017135A3 WO 2006017135 A3 WO2006017135 A3 WO 2006017135A3 US 2005024164 W US2005024164 W US 2005024164W WO 2006017135 A3 WO2006017135 A3 WO 2006017135A3
Authority
WO
WIPO (PCT)
Prior art keywords
memories
simulating
source operands
multiported
lower port
Prior art date
Application number
PCT/US2005/024164
Other languages
French (fr)
Other versions
WO2006017135A2 (en
Inventor
John Erik Lindholm
Ming Y Siu
Simon S Moy
Samuel Liu
John R Nickolls
Original Assignee
Nvidia Corp
John Erik Lindholm
Ming Y Siu
Simon S Moy
Samuel Liu
John R Nickolls
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp, John Erik Lindholm, Ming Y Siu, Simon S Moy, Samuel Liu, John R Nickolls filed Critical Nvidia Corp
Priority to JP2007521508A priority Critical patent/JP2008507034A/en
Priority to CN2005800298490A priority patent/CN101014933B/en
Publication of WO2006017135A2 publication Critical patent/WO2006017135A2/en
Publication of WO2006017135A3 publication Critical patent/WO2006017135A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.
PCT/US2005/024164 2004-07-13 2005-07-07 Simulating multiported memories using memories with lower port count WO2006017135A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007521508A JP2008507034A (en) 2004-07-13 2005-07-07 Multi-port memory simulation using lower port count memory
CN2005800298490A CN101014933B (en) 2004-07-13 2005-07-07 Simulating multiported memories using lower port count memories

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/889,730 2004-07-13
US10/889,730 US7339592B2 (en) 2004-07-13 2004-07-13 Simulating multiported memories using lower port count memories

Publications (2)

Publication Number Publication Date
WO2006017135A2 WO2006017135A2 (en) 2006-02-16
WO2006017135A3 true WO2006017135A3 (en) 2006-10-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/024164 WO2006017135A2 (en) 2004-07-13 2005-07-07 Simulating multiported memories using memories with lower port count

Country Status (6)

Country Link
US (2) US7339592B2 (en)
JP (2) JP2008507034A (en)
KR (1) KR100862124B1 (en)
CN (1) CN101014933B (en)
TW (1) TWI441021B (en)
WO (1) WO2006017135A2 (en)

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Also Published As

Publication number Publication date
KR100862124B1 (en) 2008-10-09
US7834881B2 (en) 2010-11-16
US20060012603A1 (en) 2006-01-19
CN101014933A (en) 2007-08-08
US20080109611A1 (en) 2008-05-08
JP2008507034A (en) 2008-03-06
WO2006017135A2 (en) 2006-02-16
JP2011238271A (en) 2011-11-24
JP5422614B2 (en) 2014-02-19
US7339592B2 (en) 2008-03-04
TW200613980A (en) 2006-05-01
TWI441021B (en) 2014-06-11
KR20070030327A (en) 2007-03-15
CN101014933B (en) 2011-07-27

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