WO2006017296A1 - Dual panel pixel readout in an imager - Google Patents
Dual panel pixel readout in an imager Download PDFInfo
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- WO2006017296A1 WO2006017296A1 PCT/US2005/024711 US2005024711W WO2006017296A1 WO 2006017296 A1 WO2006017296 A1 WO 2006017296A1 US 2005024711 W US2005024711 W US 2005024711W WO 2006017296 A1 WO2006017296 A1 WO 2006017296A1
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- pixels
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/41—Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Definitions
- the invention relates generally to imaging devices and more particularly to dual panel pixel readout in an imaging device.
- a CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate.
- Each pixel cell has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor.
- the charge storage region may be constructed as a floating diffusion region.
- Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
- the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge.
- Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region.
- the charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
- CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Patent no. 6,140,630, U.S. Patent no. 6,376,868, U.S. Patent no. 6,310,366, U.S. Patent no. 6,326,652, U.S. Patent no. 6,204,524 and U.S. Patent no. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
- FIG. 1 illustrates a portion of a conventional CMOS imager 10.
- the illustrated imager 10 includes an array of pixels 20 connected to a column sample and hold circuit 42 by pixel output lines 32.
- the imager 10 also includes a row decoder and driver 40, column decoder 44, readout programmable gain amplifier (PGA) 50, an analog-to-digital converter (ADC) 55, an image processor 60 and a control circuit 70.
- PGA programmable gain amplifier
- ADC analog-to-digital converter
- row lines RL connected to a row of pixels 20 are selectively activated by the row decoder and driver 40.
- Each pixel 20 in the activated row outputs sequentially a reset V rs j- and pixel signal V s jg, not necessarily in that order, on a corresponding pixel output line 32.
- the column sample and hold circuit 42 samples, holds and then outputs the reset V rs t and pixel signals V sl ⁇ to the amplifier 50 as selected by the column decoder 44.
- a differential signal (V rs t-V s ig) is produced by the amplifier 50.
- the differential signal is digitized by the analog-to-digital converter 55.
- the analog-to-digital converter 55 supplies the digitized pixel signals to the image processor 60, which forms a digital image output.
- every pixel 20 in a row is readout and input into the column sample and hold circuit 42, and then each column is serially (or sequentially) readout from the sample and hold circuit 42 for further processing.
- An exemplary timing diagram of the pixel readout and serial column readout is illustrated in FIG. 2.
- row processing time t r is equal to tp+ t cr , where tp is the time to readout the reset V rs j- and pixel signals V s jg from the pixel 20 and t cr is the column readout time (i.e., total time to readout each column in a serial manner).
- An imager's frame rate (the inverse of the time required to readout an entire array) is dependent upon the row processing time t r . It is desirable to improve an imager's frame rate. If tp is 6 ⁇ secs and t ⁇ is 42.67 ⁇ secs (e.g., 2048 columns @ 48Mhz), row processing time t r is 48.67 ⁇ secs.
- the invention provides an imager with decreased row processing time and improved frame rate.
- Various exemplary embodiments of the invention provide an imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders.
- the dual panel architecture allows pipelining of pixel readout and column readout operations to improve the imager's frame rate.
- the dual panel architecture may use a standard pixel configuration, a shared column and/or a shared row and column configuration.
- FIG. 1 is a diagram of a CMOS imager
- FIG. 2 is a timing diagram of the operation of the FIG. 1 imager
- FIG. 3 is a diagram of another CMOS imager
- FIG. 4 is a timing diagram of the operation of the FIG.3 imager
- FIG. 5 is a diagram of a CMOS imager constructed in accordance with an exemplary embodiment of the invention.
- FIG. 6 is an exemplary timing diagram of the operation of the FIG. 5 imager
- FIG. 7 is a diagram of a CMOS imager constructed in accordance with another exemplary embodiment of the invention.
- FIG. 8 is a diagram of a CMOS imager constructed in accordance with yet another exemplary embodiment of the invention.
- FIG. 9 shows a processor system incorporating at least one imaging device constructed in accordance with an embodiment of the invention.
- FIG. 3 shows an imager 110 having a shared pixel architecture. That is, two neighboring pixels 120a, 120b in the same row share readout circuitry such that their reset and pixel signals can be output to the same column's pixel output line 132. This is done to improve fill factor of the pixels 120a, 120b, but as is discussed below with respect to FIG. 4, it does not improve row processing time.
- the illustrated imager 110 includes a column sample and hold circuit 142 connected to the pixel output lines 132 by multiplexers 134. Multiplexers 134 are required to ensure that the signals from each pixel 120a, 120b are sampled and held by appropriate circuitry within the column sample and hold circuitry 142.
- the imager 110 also includes a row decoder and driver 140, column decoder 144, readout programmable gain amplifier (PGA) 150, an analog-to-digital converter (ADC) 155, an image processor 160 and a control circuit 170.
- PGA readout programmable gain amplifier
- ADC analog-to-digital converter
- row lines RL connected to a row of pixels 120a, 120b are selectively and sequentially activated by the row decoder and driver 140.
- Each pair of pixels 120a, 120b in the activated row outputs its reset V rs t and pixel signals V s ig onto a corresponding pixel output line 132 (at appropriate separate reset and pixel readout stages).
- the multiplexer 134 ensures that the column sample and hold circuitry 142 inputs the reset and pixel signals V rs t, V s jg from the pixels 120a, 120b in the correct order.
- the column sample and hold circuit 142 samples, holds and then outputs the reset V rs t and pixel signals V s ig to the amplifier 150 as selected by the decoder 144.
- a differential signal (V rs t-V s ig) is produced by the amplifier 150.
- the differential signal is digitized by the analog-to- digital converter 155.
- the analog-to-digital converter 155 supplies the digitized pixel signals to the image processor 160, which forms a digital image output.
- every pair of pixels 120a, 120b in a row is readout and input into the column sample and hold circuit 142, and then each column is serially (or sequentially) readout from the sample and hold circuit 142 for further processing.
- An exemplary timing diagram of the pixel readout and serial column readout of the imager 110 is illustrated in FIG. 4. As can be seen from FIG. 4,
- row processing time t r is equal to t a + tt ⁇ + t cr , where t a is the time to readout the reset V rs t and pixel signals V s jg from the first pixel 120a, tfc, is the time to readout the reset V rS ⁇ - and pixel signals V s jg from the second pixel 120b, and t cr is the column readout time (i.e., total time to readout each column in a serial manner).
- t a is 6 ⁇ secs
- ty is 6 ⁇ secs
- t cr is 42.67 ⁇ secs (e.g., 2048 columns @ 48Mhz)
- row processing time t r is 54.67 ⁇ secs.
- These architectures also contain column parallel gain circuits, which have storage capacitors at the amplifier output. In operation, after the signal is amplified, a subsequent analog-to-digital conversion step is performed. During the conversion, the sample and hold circuits prior to the gain circuits are available for reading out the next row of pixels. Thus, pipelined pixel readout with analog- to-digital conversion is possible. Unfortunately, with serial column readout and analog-to-digital conversion, the next row of pixels to be readout cannot be processed until the current sampled row is readout completely. As such, the existing pipelining architecture is not desirable.
- FIG. 5 illustrates a CMOS imager 210 constructed in accordance with an exemplary embodiment of the invention.
- the illustrated imager 210 uses a unique configuration and pipelining to improve row processing time and frame rate without increasing column circuitry complexity and area used.
- the illustrated imager 210 uses a dual panel pixel array 212, consisting of a first panel 212a and a second panel 212b, and separate dedicated row decoders and drivers 240a, 240b to operate the panels in a manner that allows pixel readout and column readout to be pipelined (described below in more detail with respect to FIG. 6).
- the illustrated imager 210 has a shared pixel architecture. That is, two neighboring pixels 220a, 220b in the same row share readout circuitry such that their reset and pixel signals can be output to the same column's pixel output line 232. This is done to improve fill factor of the pixels 220a, 220b.
- the imager 210 also includes a column sample and hold circuit 242 connected to the pixel output lines 232 by multiplexers 234. Multiplexers 234 ensure that the V rs t, V s ig signals from each pixel 220a, 220b are sampled and held by appropriate circuitry within the column sample and hold circuitry 242.
- the imager 210 also includes a column decoder 244, readout programmable gain amplifier (PGA) 250, an analog- to-digital converter (ADC) 255, an image processor 260 and a control circuit 270.
- the column decoder 244 generates column addresses to address the columns associated with the first panel 212a and the second panel 212b.
- the column sample and hold circuitry 242 also has separate controls for the first and second panels 212a, 212b.
- row lines RLa connected to a row of pixels 220a, 220b in the first panel 212a are selectively activated by the first row decoder and driver 240a.
- Each pair of pixels 220a, 220b in the activated row outputs its reset V rs t and pixel signals V s ig onto a corresponding pixel output line 232 (at appropriate separate reset and pixel readout stages).
- the multiplexer 234 ensures that the column sample and hold circuitry 242 inputs the reset signal V rsj - from the first pixel 220a, followed by the pixel signal V s jg from the first pixel 220a of the pair.
- the multiplexer 234 then ensures that the column sample and hold circuitry 242 inputs the reset signal V rs t from the second pixel 220b, followed by the pixel signal V s ig from the second pixel 220b of the pair.
- row lines RLb connected to a row of pixels 220a, 220b in the second panel 212b are selectively activated by the second row decoder and driver 240b.
- Each pair of pixels 220a, 220b in the activated row outputs its reset and pixel signals V rs t, V s jg onto a corresponding pixel output line 232 (at appropriate separate reset and pixel readout stages).
- the multiplexer 234 ensures that the column sample and hold circuitry 242 initially inputs the reset signal V rs t from the first pixel 220a, followed by the pixel signal V s ig from the first pixel 220a of the pair.
- the multiplexer 234 then ensures that the column sample and hold circuitry 242 inputs the reset signal V rs t from the second pixel 220b, followed by the pixel signal V s jg from the second pixel 220b of the pair.
- the column sample and hold circuit 242 samples, holds and outputs, to title amplifier 250, the reset V rs t and pixel signals V s ig from the first panel 212a and the second panel 212b (described below with respect to FIG. 6).
- a differential signal (V rS fV s ig) is produced by the amplifier 250.
- the differential signal is digitized by the analog-to-digital converter 255.
- the analog-to-digital converter 255 supplies the digitized pixel signals to the image processor 260, which forms a digital image output.
- row processing time t r has been reduced to the column readout time t cr , which is a vast improvement over other imagers row processing times. If t cr is 42.67 ⁇ secs (e.g., 2048 columns @ 48Mhz), row processing time t r is 42.67 ⁇ secs. This reduced row processing time t r yields an improved frame rate for the imager 210 of the invention.
- FIG. 7 is a diagram of a CMOS imager 310 constructed in accordance with another exemplary embodiment of the invention.
- the illustrated imager 310 uses the unique dual panel array 312 configuration and pipelining to improve row processing time and frame rate without increasing column circuitry complexity and area used.
- the illustrated imager 310 uses a dual panel array 312, consisting of a first panel 312a and a second panel 312b, and separate dedicated row decoders and drivers 340a, 340b to operate the panels in a manner that allows pixel readout and column readout to be pipelined.
- the imager 310 includes panels 312a, 312b using the conventional non-shared pixel configuration illustrated in FIG. 1. It should be noted that because the imager 310 uses the dual panel array 312, respective row decoders and drivers 340a, 340b and pipelining, the imager 310 will have improved row processing time and frame rate as illustrated in FIG. 6.
- the illustrated imager 310 also includes a column sample and hold circuit 342 connected to each column of pixels 320 by pixel output lines 332. Multiplexers are not required because each column of pixels has its own output circuitry and pixel output line 332.
- the imager 310 also includes a column decoder 344, readout programmable gain amplifier (PGA) 350, an analog-to-digital converter (ADC) 355, an image processor 360 and a control circuit 370.
- PGA readout programmable gain amplifier
- ADC analog-to-digital converter
- the column decoder 344 generates column addresses to address the columns associated with the first panel 312a and the columns associated with the second panel 312b.
- the column sample and hold circuitry 342 also has separate controls for the first and second panels 312a, 312b.
- row lines RLa connected to a row of pixels 320 in the first panel 312a are selectively activated by the first row decoder and driver 340a.
- Each pixel 320 in the activated row outputs its reset V rs t and pixel signals V s jg onto a corresponding pixel output line 332 (at appropriate separate reset and pixel readout stages).
- row lines RLb connected to a row of pixels 320 in the second panel 312b are selectively activated by the second row decoder and driver 340b.
- Each pixel 320 in the activated row outputs its reset V rs t and pixel signals V s j ⁇ onto a corresponding pixel output line 332 (at appropriate separate reset and pixel readout stages).
- the column sample and hold circuit 342 samples, holds and outputs, to the amplifier 350, the reset V rs t and pixel signals V s jg from the first panel 312a and the second panel 312b as described above with respect to FIG. 6.
- a differential signal (V rS fV s ig) is produced by the amplifier 350.
- the differential signal is digitized by the analog-to-digital converter 355.
- the analog-to-digital converter 355 supplies the digitized pixel signals to the image processor 360, which forms a digital image output.
- FIG. 8 is a diagram of a CMOS imager 410 constructed in accordance with yet another exemplary embodiment of the invention.
- the illustrated imager 410 uses a unique configuration and pipelining to improve row processing time and frame rate without increasing column circuitry complexity and area used.
- the illustrated imager 410 uses a dual panel array 412, consisting of a first panel 412a and a second panel 412b, and separate dedicated row decoders and drivers 440a, 440b to operate the panels in a manner that allows pixel readout and column readout to be pipelined.
- the illustrated imager 410 has a combined shared-row/column pixel readout architecture such as one of the architectures disclosed in application nos. 10/721,190 and 10/721,191, also assigned to Micron Technology, Inc., the disclosures of which are hereby incorporated by reference in their entirety. That is, two neighboring pixels 420a, 420b in a row and two neighboring pixels 420c, 42Od in the adjacent row share readout circuitry such that their reset and pixel signals can be output to the same column's pixel output line 432. This is done to improve fill factor of the pixels 420a, 420b, 420c, 42Od.
- the imager 410 also includes a column sample and hold circuit 442 connected to the pixel output lines 432 by multiplexers 434. Multiplexers 434 are required to ensure that the signals from each pixel 420a, 420b, 420c, 42Od are sampled and held by appropriate circuitry within the column sample and hold circuitry 442.
- the imager 410 also includes a column decoder 444, readout programmable gain amplifier (PGA) 450, an analog-to-digital converter (ADC) 455, an image processor 460 and a control circuit 470.
- PGA readout programmable gain amplifier
- ADC analog-to-digital converter
- the column decoder 444 generates column addresses to address the columns associated with the first panel 412a and the columns associated with the second panel 412b. Similar to the other embodiments of the invention, the column sample and hold circuitry 442 also has separate controls for the first and second panels 412a, 412b.
- row lines RLa connected to a row of pixels 420a, 420b in the first panel 412a are selectively activated by the first row decoder and driver 440a.
- Each pair of pixels 420a, 420b in the activated row outputs its reset V rs t and pixel signals V s jg onto a corresponding pixel output line 432 (at appropriate separate reset and pixel readout stages).
- Row lines RLa connected to the adjacent row of pixels 420c, 42Od in the first panel 412a are selectively activated by the first row decoder and driver 440a.
- Each pair of pixels 420c, 420d, in the activated adjacent row also outputs its reset V rs t and pixel signals V s jg onto a corresponding pixel output line 432 (at appropriate separate reset and pixel readout stages).
- row lines RLb connected to a row of pixels 420a, 420b in the second panel 412b are selectively activated by the second row decoder and driver 440b.
- Each pair of pixels 420a, 420b in the activated row outputs its reset V rS (- and pixel signals V 8 ⁇ g onto a corresponding pixel output line 432 (at appropriate separate reset and pixel readout stages).
- Row lines RLb connected to the adjacent row of pixels 420c, 42Od in the second panel 412b are selectively activated by the second row decoder and driver 440b.
- Each pair of pixels 420c, 42Od, in the activated adjacent row also outputs its reset V rs t and pixel signals V s ig onto a corresponding pixel output line 432 (at appropriate separate reset and pixel readout stages).
- the column sample and hold circuit 442 samples, holds and outputs, to the amplifier 450, the reset V rs t and pixel signals V s ig from the first panel 412a and the second panel 412b in the pipelined manner described above with respect to FIG. 6.
- a differential signal (V rs t-V s ig) is produced by the amplifier 450.
- the differential signal is digitized by the analog- to-digital converter 455.
- the analog-to-digital converter 455 supplies the digitized pixel signals to the image processor 460, which forms a digital image output.
- the present invention has the additional benefit of reducing the loading on the row decoder/driver circuits. Reduced loading leads to faster pixel readout times. Timing to the separate row decoders and drivers can be made the same in the case that pipelined pixel readout id not desired or required.
- the invention can utilize many panel configurations and is not to be limited to a dual panel construction. That is, the panels used in the invention can comprise 2, 3, 4, or more panels as deemed appropriate for the application. All that is required is that each panel be driven by its own row decoder and that the column S/H circuitry and control circuitry be configured to operate the panels as described above.
- FIG. 9 shows system 900, a typical processor system modified to include an imaging device 908 constructed in accordance with an embodiment of the invention (i.e., imagers 210, 310, 410 described above).
- the processor-based system 900 is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and data compression system.
- System 900 for example a camera system, generally comprises a central processing unit (CPU) 902, such as a microprocessor, that communicates with an input/output (I/O) device 906 over a bus 904.
- Imaging device 908 also communicates with the CPU 902 over the bus 904.
- the processor-based system 900 also includes random access memory (RAM) 910, and can include removable memory 915, such as flash memory, which also communicate with the CPU 902 over the bus 904.
- the imaging device 908 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.
- a method of integrating an imaging device comprises fabricating an array of pixels in at least two panels and fabricating a readout circuit coupled to the panel, the readout circuit enabling pipelined readout of the panels.
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Priority Applications (2)
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JP2007521574A JP2008506341A (en) | 2004-07-12 | 2005-07-11 | Dual panel pixel readout device in imaging device |
EP05769594A EP1779651B1 (en) | 2004-07-12 | 2005-07-11 | Dual panel pixel readout in an imager |
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US10/887,880 | 2004-07-12 | ||
US10/887,880 US7652703B2 (en) | 2004-07-12 | 2004-07-12 | Dual panel pixel readout in an imager |
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US (2) | US7652703B2 (en) |
EP (1) | EP1779651B1 (en) |
JP (1) | JP2008506341A (en) |
KR (2) | KR100914582B1 (en) |
CN (1) | CN101019413A (en) |
TW (1) | TWI278230B (en) |
WO (1) | WO2006017296A1 (en) |
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KR100914582B1 (en) | 2009-08-31 |
US7924337B2 (en) | 2011-04-12 |
US7652703B2 (en) | 2010-01-26 |
TW200618621A (en) | 2006-06-01 |
US20060007337A1 (en) | 2006-01-12 |
TWI278230B (en) | 2007-04-01 |
KR20090003366A (en) | 2009-01-09 |
KR20070042175A (en) | 2007-04-20 |
EP1779651B1 (en) | 2012-12-19 |
EP1779651A1 (en) | 2007-05-02 |
JP2008506341A (en) | 2008-02-28 |
CN101019413A (en) | 2007-08-15 |
US20100091164A1 (en) | 2010-04-15 |
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