WO2006020468A1

WO2006020468A1 - Display device with current driving

Info

Publication number: WO2006020468A1
Application number: PCT/US2005/027512
Authority: WO
Inventors: Kazuyoshi Kawabe
Original assignee: Eastman Kodak Company
Priority date: 2004-08-11
Filing date: 2005-08-01
Publication date: 2006-02-23
Also published as: EP1776690A1; JP2006053347A

Abstract

A current is sufficiently written into a pixel in an organic EL display device. An auxiliary circuit (110) for supplying part of current data is connected, in addition to a pixel circuit, to a data line (107) for supplying the current data to the pixel. As a result, a desired small tone current can be written into the pixel even when a sufficiently large current is supplied to the data line (107).

Description

DISPLAY DEVICE WITH CURRENT DRIVING

FIELD OF THE INVENTION

The present invention relates to a display device of an active matrix type including pixel circuits arranged in a matrix, each pixel circuit having a current driven diode type emissive element and a plurality of thin film transistors controlling the diode type emissive element.

BACKGROUND OF THE INVENTION Accompanying recent advances in computerization has been an increasing demand for personal digital assistants having processing capabilities comparable to that of earlier personal computers. As a result, high-resolution and high-quality video display devices fulfilling the requirements of reduced thickness and weight, a wider viewing angle, and smaller power consumption are desired.

In order to meet desired requirements, display devices (or displays) in which thin film active elements (thin film transistors or simply referred to as TFTs) are formed in a matrix on a glass substrate, and electrooptic elements are formed thereon controlled by the TFT to be driven are actively developed.

The substrate for forming the thin film active elements is usually formed by providing and patterning a semiconductor film made of, for example, amorphous silicon or polysilicon, and making connections using metal wiring lines. Due to differences in electric properties between the thin film active elements, a driving integrated circuit (IC) must be separately provided when amorphous silicon is used while a driving circuit can be formed on the substrate when polysilicon is used. In liquid crystal displays (hereafter simply referred to as LCDs) currently in widespread use, amorphous silicon is most commonly used in larger size displays, while polysilicon type has become the standard material used for medium and small sizes because it is suited for providing higher resolution. Regarding organic electroluminescence (organic EL) type displays having characteristics of self-emissiveness, reduced thickness and weight, and a wider viewing angle, only the polysilicon type displays are mass produced.

Generally, an organic EL element is combined with a TFT to utilize a voltage current controlling function thereof for controlling a current. The voltage current controlling function is the function to control a current between a source and a drain by applying a voltage to a gate terminal of a TFT. By setting a voltage of the gate terminal of the TFT supplying a driving current to the organic EL element to a voltage in accordance with luminance data (tone data), the driving current in accordance with luminance data can be supplied to the organic EL element to adjust intensity of emitted light, and therefore to display an image in a desired tone.

However, when such a configuration is employed, the intensity of light emitted from the organic EL element is easily sensitive to the properties of the TFTs. Polysilicon TFTs, particularly so-called "low-temperature polysilicon TFTs", i.e. TFTs formed through a low temperature process, tend to exhibit relatively significant variation in electric properties even between adjoining pixels, which is one of the main factors for deterioration in display quality, particularly in display uniformity on the screen, of the organic EL displays. One conventional technique for addressing this problem is disclosed in Patent Document 1 (JP-A-2002-514320). Referring to FIG 12, this document discloses a technique in which a TFT 260 for driving an organic EL element 290 by a current controls supply of a tone current to be provided to a data line 220. More specifically, a tone current is supplied to the data line 220 from a current source 230. A select line 210 is connected to a gate of a P channel TFT 250, which has a source connected to the data line 220, and a drain connected to a source of a P channel driving TFT 260. The source and gate of the driving TFT 260 are connected by a storage capacitor 280. A drain of the driving TFT 260 is connected to an anode of the organic EL element 290, whose cathode is connected to the ground. The source of the driving TFT 260 is connected to a source of an N channel TFT 270 having a gate connected to the select line 210, and a drain connected to a power supply. The gate of the driving transistor TFT 260 is connected to a source of a P channel TFT 240 having a drain connected to the drain of the driving TFT 260, and a gate connected to the select line 210. In this circuit of the conventional art illustrated in FIG 12, when the select line 210 is rendered "High", the TFT 270 is turned on, and a power supply voltage is applied at one end of the storage capacitor 280. Subsequently, when the select line 210 is rendered "Low", the TFT 270 is turned off, and the TFTs 250 and 240 are turned on. As a result, a short circuit is made between the drain and gate of the driving TFT 260, whereby the tone current flowing through the data line 220 is supplied to the driving TFT 260, and a voltage at which the driving TFT 260 supplies the tone current flowing through the data line 220 is set at the storage capacitor 280. In other words, the voltage in accordance with the tone current is written in the storage capacitor 280. Consequently, the driving TFT 260 keeps supplying the tone current to the organic EL element 290 until it is next accessed, thereby achieving desired tone. The gate voltage obtained when the tone current is supplied is thus set, the driving current to be supplied to the organic EL element 290 can be made similar to the tone current even when the properties, such as a threshold, of the driving TFT 260 are varied. In this conventional example, on the data line 220, intersection capacitors are generated at intersections with wiring lines, such as the select line 210 and other electrodes. The capacitance of such an intersection capacitor is generally at least in the range of several pF to tens of pF depending on the size and resolution of the display.

The time ΔT required for changing the potential of the data line having the intersection capacitance C with a data current "i" by an amount ΔV can be expressed as: ΔT = C*ΔV/i. When the intersection capacitance C is lOpF, the data current "i" is 0.1 μA, and ΔV is 3 V, the time ΔT is equal to 300 μs. Taking into consideration that the one horizontal period for the resolution of QVGA (320 X 240) is about 60 μs, writing operation cannot be performed within the horizontal period with the current as small as about 0.1 μA, and therefore unevenness is observed on the display due to insufficient writing.

Further, such effects are especially conspicuous in high-resolution panels, i.e. the panel in which the horizontal period no longer than 60 μs can be secured.

SUMMARY OFTHE INVENTION The present invention provides a display device comprising an active matrix display array including pixel circuits arranged in a matrix, each having a diode emissive element driven by a current, and a plurality of thin film transistors for controlling the diode emissive element, a data line provided corresponding to each column of the matrix for supplying a data current to the pixel circuit in the corresponding column, a data driver for controlling supply of the data current to the data line, a select line provided corresponding to each row of the matrix for supplying a select signal to the pixel circuit in the corresponding row, a gate driver for supplying the select signal to the select line, and an auxiliary circuit connected to the data line. The auxiliary circuit is capable of supplying part of the data current supplied from the data driver to the data line.

The auxiliary circuit may also preferably have a current supplying capability larger than the pixel circuit. Further, the auxiliary circuit may be preferably formed of a plurality of auxiliary circuits having different current supplying capabilities for one data line.

Preferably, the auxiliary circuit may be connectable to the data line through a switch, and be connected to the data line at least once in a horizontal period.

Preferably, the data driver is capable of supplying a plurality of data currents to the data line for the same data voltage, and the plurality of data currents are switched within one horizontal period. The plurality of data currents are preferably supplied to the data line as a current larger than a data current written to a pixel in a first half of one horizontal period.

Preferably, the gate driver simultaneously selects a plurality of select lines. Further, the present invention provides a display device comprising an active matrix display array including pixel circuits arranged in a matrix, each having a diode emissive element driven by a current, and a plurality of thin film transistors for controlling the diode emissive element, a data line provided corresponding to each column of the matrix for supplying a data current to the pixel circuit in the corresponding column, a data driver for controlling supply of the data current to the data line, a select line provided corresponding to each row of the matrix for supplying a select signal to the pixel circuit in the corresponding row, and a gate driver for supplying the select signal to the select line. The gate driver simultaneously selects a plurality of select lines to simultaneously supply to a plurality of pixel circuits the data current supplied from the data driver to the data line. Because current data is written by selecting a plurality of lines or the auxiliary circuit, the current data supplied to the data line can be supplied to other elements than the pixel selected for writing. Therefore, it is possible to control a small current to be written to the selected pixel even when a large current is supplied to the data line. As a result, a wiring capacitor can rapidly be driven to write a small current to the pixel within a horizontal period.

Further, a ratio of the current supplied to the selected pixel can be varied by changing the transistor size of the auxiliary circuit or the number of selected lines, thereby making it possible to easily cope with large, high-resolution panels.

BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 shows the overall configuration of an organic EL display. FIG 2 shows a TFT pixel circuit.

FIG 3 shows internal configurations of a data driver, a precharge circuit, and an auxiliary circuit.

FIG 4 shows an internal configuration of a gate driver. FIGS. 5A and 5B show internal configurations of a voltage-current conversion circuit according to a first embodiment.

FIGS. 6A and 6B show an example of a configuration wherein a plurality of auxiliary circuits are provided.

FIG 7 is a timing chart for driving a panel according to the first embodiment.

FIGS. 8 A and 8B show internal configurations of the auxiliary circuit. FIGS. 9A and 9B show internal configurations of a voltage-current conversion circuit according to a second embodiment. FIG 10 is a timing chart for driving a panel according to the second embodiment.

FIG 11 is a timing chart for driving a gate driver according to a third embodiment. FIG 12 is a diagram used for describing a conventional example.

DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. (1) First Embodiment Overall Configuration

FIG 1 shows the overall configuration of an organic EL display according to the present embodiment. An organic EL display 1 includes an active matrix display array 101 having an organic EL element and a TFT arranged for a pixel, a data driver 102, a gate driver 103, a precharge circuit 104, a control circuit 106 for supplying a video signal and a control signal to the data driver 102 through a data control bus 112, and a control signal to the gate driver 103 through a gate control bus 113, a data line 107 for supplying a tone data current from the data driver 102 or a precharge voltage from the precharge circuit 104 to a pixel, a first select line 108 for supplying a first selection potential from the gate driver 103, a second select line 109 for supplying a second selection potential from the gate driver 103, an auxiliary circuit 110 for supplying part of the tone current on the data line 107 from the data driver 102, and an input bus 111 for receiving RGB video data, a clock, and the like.

Under the control of the control circuit 106, the gate driver 103 controls driving of the first and second select lines 108 and 109, and supply of a tone current from the data driver 102 to the data line 107. The control circuit 106 also controls supply of the precharge voltage to the data line 107 from the precharge circuit 104, and connection of the auxiliary circuit 110 to the data line 107.

A display device 105 is constituted by the display array 101, the data driver 102, the gate driver 103, the precharge circuit 104, and the auxiliary circuit 110. When the low-temperature polysilicon process is employed, these circuits can be formed on a glass substrate. Pixel Circuit Configuration

A configuration of pixel circuits arranged in a matrix in the active matrix display array 101 for use in the present embodiment will be described with reference to FIG. 2.

The pixel circuit includes an organic EL element 201, a driving TFT 202 for driving the organic EL element 201 with a current, a diode switch TFT 203 for connecting a gate terminal and a drain terminal of the driving TFT 202, a light control TFT 204 for controlling whether or not to light up (supply a current to) the organic EL element 201, a gate TFT 205 for supplying the tone current from the data line 107 into a pixel in a controlled manner, a storage capacitor 206, a current supply line 211 for supplying a current to the organic EL element 201, and a fixed potential line 212 for fixing a potential of one terminal of the storage capacitor 206 at a predetermined value. The fixed potential line 212 may be connected to the current supply line 211.

The driving TFT 202 has a source terminal connected to the current supply line 211, a drain terminal connected to a source terminal of the light control TFT 204 and a source terminal of the diode switch TFT 203, and a gate terminal connected to the other terminal of the storage capacitor 206 that is not connected to the fixed potential line 212, a drain terminal of the gate TFT 205, and a drain terminal of the diode switch TFT 203. The light control TFT 204 has a gate terminal connected to the first select line 108, and a drain terminal connected to an anode of the organic EL element 201.

The gate TFT 205 has a gate terminal connected to the first select line 108, and a source terminal connected to the data line 107.

The gate terminal of the diode switch TFT 203 is connected to the second select line 109.

The current supply line 211 , the fixed potential line 212, and a cathode electrode of the organic EL element are shared by all the pixels. The driving TFT 202, the diode switch TFT 203, and the light control TFT 204 are P channel TFTs, while the gate TFT 205 is an N channel TFT. The method of controlling the pixel circuit of FIG 2 using the data driver 102, the gate driver 103, the precharge circuit 104, and the auxiliary circuit 110 will be described later, and a method of driving the organic EL element using the pixel of FIG 2 will next be described. Pixel Circuit Driving Method A. Precharge

When the second select line 109 is deactivated and the first select line 108 is activated, the diode switch TFT 203 is turned off, the gate TFT 205 is turned on, and the light control TFT 204 is turned off. Under such conditions, when a precharge potential is supplied to the data line 107, it is written in the storage capacitor 206 to be set in the initial state. The precharge potential is arranged at the level where the organic EL element 201 is not illuminated, i.e. no current is supplied. The pixel circuit of FIG. 2 is controlled to always attain this initial state immediately before the tone current is written. More specifically, the gate potential of the driving TFT 202 and the potential of the data line 107 are set at the precharge potential. B. Current Data Writing

Next, when the second select line 109 is rendered active, the diode switch TFT 203 is turned on to connect the gate and drain terminals of the driving TFT 202, acting as an MOS diode. In this state, when the tone current is supplied to the data line 107, the current flows from the current supply line 211 through the source and drain terminals of the driving TFT 202, the source and drain terminals of the diode switch TFT 203, and the gate TFT 205 to the data line 107.

As a result, a gate potential supplied by the driving TFT 202 and equal to the tone current supplied to the data line 107 is generated at the gate terminal of the driving TFT 202. When the second select line 109 is deactivated after this potential is stabilized, the diode switch TFT 203 is turned off, cutting off the tone current path. Subsequently when the first select line 108 is deactivated, the gate TFT 205 is turned off, the gate potential is stored in the storage capacitor 206, so that the driving TFT 202 keeps supplying to the organic EL element 201 the current determined by the gate potential, i.e. the tone current supplied to the data line 107, until it is next accessed.

When the gate TFT 205 is of the N type and the diode switch TFT 203 is of the P type as in the pixel circuit of FIG 2, the gate TFT 205 and the diode switch TFT 203 are active when they are in a "High" state and "Low" state, respectively. As a result, these TFTs are controlled in opposite polarities to each other in this configuration, such that fluctuation in the potential stored in the storage capacitor 206 is as a result of the selection potential of the select lines 108 and 109 is reduced. More specifically, the first select line 108 is "High" and the second select line 109 is "Low" while the tone current is written, whereby the effects on the storage capacitor are canceled with each other. When the lines are deselected, the first and second select lines 108 and 109 are "Low" and "High", respectively, and the effects are similarly canceled with each other.

By thus configuring the pixel circuit so that a plurality of select lines are controlled with opposite polarities to each other, variation in potential stored in the storage capacitor 206 can be suppressed.

Internal configurations of the data driver 102, the precharge circuit 104, and the auxiliary circuit 110 used for driving the display array 101 including the pixel circuits of FIG 2 arranged in a matrix in the above-described manner will next be described with reference to FIG. 3. Data Driver

The data driver 102 includes a shift register 301, a pulse enable circuit 302, a video switch 303, a voltage-current conversion circuit 304, a data switch 305, an RGB video signal line 311, a driver select line 312 (EA, EB), and an output enable line 313 (OA, OB).

The shift register 301 sequentially shifts an input pulse from a shift register 1 to a shift register "n" in synchronism with a clock. A pulse obtained by shifting the input pulse is output from an output terminal Hi (i = 1 to n), and input to the associated pulse enable circuit 302.

The pulse enable circuit 302 enables the shift register output by the driver select lines EA and EB.

The video switch 303, the voltage-current conversion circuit 304, and the data switch 305 are each provided with two systems, system A and system B, for R, G, and B. The shift pulse of the shift register enabled through the pulse enable circuit 302 by the driver select signal lines EA and EB turns on the video switch 303 of either the system A or the system B, and the video signal line 311 is connected to the voltage-current conversion circuit 304 of the system A or B.

For example, when the output Hl of the shift register is "High", and the lines EA and EB are "High" and "Low", respectively, the pulse enable circuit 302 for the shift register 1 transmits the shift pulse of the shift register to the video switch 303 of the system A, which in turn connects inputs of the voltage-current conversion circuits RAl, GAl, and BAl in the system A to the video signal lines R, G, and B to take the video data into the associated voltage-current conversion circuits.

When the shift pulse is transmitted to the last shift register "n" and horizontal line data is sampled by the voltage-conversion circuit 304 of the system A or the system B, the output enable line OA or OB for the sampled system is activated, thereby connecting the data line 107 and the output of the voltage-current conversion circuit 304 of the activated system to drive the data line 107.

According to the above-described example in which the line EA is "High", the data line 107 is driven by the voltage-current conversion circuit 304 of the system A by activating the line OA after the shift pulse is transmitted to the shift register "n".

By deactivating the select line EA of the system A, activating the select signal EB of the system B, and transmitting the shift register pulse to the system B while the voltage-current conversion circuit 304 of the system A drives the data line 107, data on the video signal line 311 is now taken into the voltage-current conversion circuit 304 of the system B to supply the tone current to the data line 107. Thus, the tone current data corresponding to each line data can smoothly be supplied to the data line 107 by alternately switching the systems. In such a data driver 102, the video signal line 311 is connected to the voltage-current conversion circuit 304 through the video switch 303. Consequently, the wiring load of the video signal line 311 is equal to an input impedance of the voltage-current conversion circuit 304 connected by the video switch 303, and is very small. This indicates that a signal on the video signal line 311 can be more rapidly transferred to the voltage-current conversion circuit 304, suited for driving a panel with a higher resolution. Voltage-Current Conversion Circuit

The voltage-current conversion circuit 304 is preferably formed by an N channel TFT illustrated in FIGS. 5 A and 5B by way of example when the driving TFT 202 is formed by a P channel TFT as in FIG 2.

An example of the simplest circuit is shown in FIG 5 A. The circuit includes an N channel voltage-current conversion TFT 501, and a storage capacitor 502. The voltage-current conversion TFT 501 is controlled by a shift pulse of the shift register 301 , and the driver select lines EA and EB. The video switch 303 samples video data (a tone voltage) on the video signal line (data bus) 311, and the sampled voltage level is stored in the storage capacitor 502. The voltage stored in the storage capacitor 502 is set as the gate voltage of the voltage-current conversion TFT 501 , and therefore the current value is determined in accordance with the sampled voltage level (tone voltage).

As described above, either the system A or the system B in the voltage-current conversion circuit 304 is selected by the driver select lines EA and EB, and the tone voltage for a line is sequentially sampled by the voltage-current conversion circuit 304 of the system A or the system B for the corresponding line. After sampling the voltage for one line, the data switch 305 controlled by the output enable lines OA and OB connects the voltage-current conversion circuit 304 of the system A or the system B that does not sample the tone voltage to the data line 107. As a result, the voltage-current conversion TFT 501 drives the data line 107 at the tone current corresponding to the tone voltage sampled in the storage capacitor 502. Because uniform voltage-current conversion properties are hard to achieve when the voltage-current conversion TFT 501 is formed through, for example, the low-temperature polysilicon TFT process, reset TFTs 503 and 504 and a reset capacitor 505 are additionally provided as illustrated in FIG 5B to correct a voltage Vth of the voltage-current conversion TFT 501, so that the voltage-current conversion properties can be more uniform.

The reset TFT 503 has a gate connected to a control line, and a source and a drain connected between a gate and a drain of the voltage-current conversion TFT 501. The reset TFT 504 has a gate connected to the control line, and a source and a drain connected to opposing ends of the storage capacitor 502. The storage capacitor 502 is connected to the gate of the voltage-current conversion TFT 501 through the reset capacitor 505. Correction of Threshold Voltage Vth

The process for correcting the voltage Vth of the voltage-current conversion TFT 501 using the reset TFTs 503 and 504 and the reset capacitor 505 will be described.

By turning on the reset TFTs 503 and 504 before providing the input pulse to the shift register, i.e. turning off the video switch 303 and the data switch 305, and rendering the control line "High", the current flowing through the TFT 501 approaches to zero over time. In other words, the voltage Vth of the voltage-current conversion TFT 501 is written in the reset capacitor 505.

Next, the reset TFTs 503 and 504 are turned off, the input pulse is provided to the shift register, and the tone voltage data on the video signal line (data bus) 311 is sequentially taken into the storage capacitor 502, whereby a gate potential Vgs of the voltage-current conversion TFT 501 can be set to the potential expressed as: Vgs = Vth + Vd, where Vd is the tone voltage.

Thus, according to the circuit of FIG 5B, the gate voltage (the gate-source voltage) of the voltage-current conversion TFT 501 can be set equal to the sum of Vth and Vd, thereby reducing variation in voltage-current conversion. The voltage-current conversion TFT 501 is preferably designed larger than the reset TFTs 503 and 504 in order to improve uniformity of conversion properties. The data driver 102 may be replaced with a data driver IC having the above-described or equivalent functions. Precharge Circuit

Referring again to FIG 3, the precharge circuit 104 includes a precharge switch 306, a precharge enable line 314 (PRE), and a precharge potential supply line 315. By activating the precharge enable line PRE, the precharge switch 306 is turned on, and a precharge voltage VPRE on the precharge potential supply line 315 is supplied to the data line 107, thereby precharging the data line 107 at the precharge potential VPRE. Auxiliary Circuit

The auxiliary circuit 110 includes an individual auxiliary circuit 307 controlled by each data line 107 to be connected or disconnected, and an auxiliary circuit enable line 316 for controlling whether or not to activate the auxiliary circuit 307 by turning the switch on or off to connect or disconnect the circuit to the data line 107.

Referring to FIGS. 8A and 8B, the individual auxiliary circuit 307 is similar to the pixel circuit of FIG 2, but does not include the organic EL element 201 and the light control TFT 204 of the pixel circuit of FIG 2, and formed either as the circuit illustrated in FIG 8 A in which the gate terminal of the diode switch TFT 203 is fixed to the level where the diode switch TFT 203 is turned on and which is enabled by the first auxiliary circuit select line 316, or as the circuit illustrated in FIG. 8B in which the gate terminal of the diode switch TFT 203 is connected to a second auxiliary circuit select line 317. The storage capacitor 206 may not be provided in the auxiliary circuit 307 because the current needs to be supplied only when data is written into the pixel circuit.

In the circuit of FIG 8 A, the diode switch TFT 203 is always in the ON state when the auxiliary circuit 307 is connected to the data line 107, and therefore the driving TFT 202 is diode-connected. Consequently, by causing the auxiliary circuit enable line 316 to attain the "High" state, the gate TFT 205 is turned on to supply the current from the power supply line 211 to the data line 107. Thus, the auxiliary circuit 307 can be controlled whether or not to connect to the data line 107 by controlling the auxiliary circuit enable line 316.

It should be noted that the driving TFT 202 in the auxiliary circuit has a different current value (different current supplying capability) from the pixel circuit for the same gate voltage. This can easily be achieved by changing the transistor size.

For example, assuming that the current supplying capability of the driving TFT in the auxiliary circuit is (x-1) times (where x is a real number no smaller than 1) the driving power of the driving TFT in the pixel circuit, and that the circuit of FIG 8B is used as the auxiliary circuit, in supplying the tone current to a pixel in a given line, the gate terminal of the driving TFT in the pixel and the gate terminal of the driving TFT in the auxiliary circuit are connected through the data line 107 by activating the first and second select lines 108 and 109, and simultaneously the first and second auxiliary circuit enable lines 316 and 317. Assuming that a current "i" is supplied to the driving TFT 202 in the pixel circuit during this operation, the current in accordance with the current supplying capability, i.e. (x-l)*i, is supplied to the driving TFT 202 in the auxiliary circuit, and therefore the sum x*i is supplied to the data line 107. Assuming that the current "i" is 0.1 μA, and that the current supplying capability of the driving TFT 202 in the auxiliary circuit is nine times that of the pixel circuit, the current of 10*i, i.e. 1 μA, is supplied to the data line 107. When the data line 107 has the wiring capacitance C of 10 pF and the voltage change ΔV is 3 V, the time ΔT required for the change is equal to 30 μ s from the equation ΔT = C*ΔV /i. The time is shortened enough for writing within one horizontal period of 60 μ s for the panel of QVGA resolution, and a small current of 0.1 μ A can be supplied into the pixel during this period. As a result, when the auxiliary circuit 110 is provided, the data driver 102 needs only to supply the data current 10 times the current supplied in the configuration where the auxiliary circuit is not provided. This can easily be achieved by appropriately setting the ability of the voltage-current conversion TFT 501 in the data driver 102.

The multiplying ratio of the current supplying capability of the driving TFT 202 in the auxiliary circuit 307 with respect to that of the pixel circuit can be determined as desired, so that the optimum ratio can be set in accordance with the resolution and the wiring capacitance of the data line. More specifically, when the wiring line has a considerable capacitance in a high resolution panel of a larger size, a higher multiplying ratio is set in order to write a small current into the pixel within the horizontal period. This indicates that a current writing operation can be finished within the horizontal period without exception even for a large-sized panel having an amorphous silicon substrate. Further, by controlling the auxiliary circuit enable line 316, the period for connecting the auxiliary circuit 307 within the horizontal period can also be controlled.

Further, as illustrated in FIGS. 6 A and 6B, a plurality of auxiliary circuits 307 may be provided for a single data line 107 in order to activate/deactivate a plurality of associated auxiliary circuit enable lines in a controlled manner for switching among the current supplying capabilities.

FIG 6A shows a configuration example in which a plurality of auxiliary circuits 307 having the equal current supplying capability are provided to be controlled by enable lines SUBA, SUBB, and SUBC. FIG 6B shows a configuration example in which a plurality of auxiliary circuits 307 having different current supplying capabilities varied as 2 to the power of "n" (2ⁿ) to be controlled by enable lines SUBO, SUBl, and SUB2.

The redundant configuration of FIG 6 A may be used to, for example, avoid circuit defects, or to eliminate variation in properties and achieve uniformity by providing a plurality of auxiliary circuits 307. More specifically, when one auxiliary circuit 307 is defective, another auxiliary circuit 307 may be used. The number of connected auxiliary circuits 307 may be controlled to achieve uniformity in accordance with difference in properties among columns or among pixels. By thus selecting one or more required auxiliary circuits 307, a greater data current on the data line 107 can be obtained, so that the operation for writing the data current into the pixel circuit can be quickly finished.

When, for example, four circuits having current supplying capabilities varied as 2 to the power of "n" (2ⁿ) are provided as in FIG 6B, such a configuration allows formation of the auxiliary circuit whose current supplying capability can be selected from 16 (2⁴=16) options. By controlling the lines SUB0-SUB2, the amount of current flowing to the auxiliary circuit 307 can be set to achieve finer adjustment and control. The pixel easily affected by the wiring capacitance in general is provided in a line distant from the data driver, and therefore the above-described auxiliary circuit 307 is desirably provided at a distant end from the data driver.

For example, the circuit may be formed in the active matrix display array 101 distant from the data driver 102, or may be formed as a circuit in the periphery thereof. Gate Driver

An internal configuration of the gate driver 103 will next be described with reference to FIG 4. The gate driver 103 includes a shift register 401 , a first enable circuit 402, a second enable circuit 403, a first buffer 404, a second buffer 405, and first and second enable control lines 411 (El , E2).

Each input of the first and second enable circuits 402 and 403 for each line is connected to an output Vi (i=0 through n) of each shift register. The other input of the first enable circuit 402 is connected to the first enable control line E 1 , and the other input of the second enable circuit 403 is connected to the second enable control line E2. The states of the first and second select lines 108 and 109, respectively, are controlled by the shift register output Vi, and lines El and E2.

When the output Vn, and the lines El and E2 are all "High", the first and second select lines 108 and 109 for the n^th line attain the "High" state and the "Low" state, respectively, thereby turning on the gate TFT 105 and the diode switch TFT 203 in the pixel in opposite polarities to each other.

When the output Vn is "Low" or the lines El and E2 are "Low", the first and second select lines 108 and 109 attain the "Low" state and the "High" state, respectively, thereby turning off the gate TFT 105 and the diode switch TFT 203 in the pixel in opposite polarities to each other. Even when the lines El and E2 are continuously maintained at a "High" level, the first and second select lines can simultaneously be activated or deactivated in opposite polarities to each other only by the shift register output Vn. Driving Method

The method of driving each pixel circuit in the active matrix display array 101 using the data driver 102, the gate driver 103, the precharge circuit 104, and the auxiliary circuit 110 will be described with reference to a timing chart of FIG. 7. The chart shows a pulse 701 of a shift register output Vk in the k^th stage in the gate driver 103, a pulse 702 output from the shift register in the (k+l)^th stage, a pulse 703 of the first enable line El, a pulse 704 of the second enable line E2, a pulse 705 of the auxiliary circuit enable line 316, a pulse 706 of the output enable line OA of the system A, a pulse 707 of the output enable line OB of the system B, a pulse 708 of the precharge enable line PRE, and a data signal 709 of the data line 107.

In the first half of the period Tk-Tk+1 during which the pulse 701 in the k^th line shifted by the shift register is "High", the output enable lines OA and OB of the data driver are rendered inactive, and the precharge enable line PRE is rendered active, so that the precharge potential VPRE is supplied to the data line 107. In this phase, the first enable control line El is rendered "High", so that the precharge potential VPRE is first written in the pixel.

Next, the precharge enable line PRE is deactivated and the output enable line OA is activated, whereby the tone current data of the system A is supplied to the data line 107. During this period of time, because the second enable line and the auxiliary circuit enable line are both rendered "High", the tone current data of the system A flows to the auxiliary circuit and the pixel circuit, and the indirect tone current flows to the pixel circuit in accordance with the current supplying capability of the auxiliary circuit.

When the current supplying capability of the auxiliary circuit 307 is nine times that of the pixel circuit and the current supplied by the system A is 1 μA, one tenth of the above current, i.e. 0.1 μA, is supplied to the pixel circuit.

By repeating the above operation for each line with the above-described timing, a larger current is supplied to the data line 107, and small current data can indirectly be written into the pixel in each line within the horizontal period. Note that the tone current data of the system B is supplied to the data line 107 in the next horizontal period. (2) Second Embodiment

Voltage-Current Conversion Circuit

FIGS. 9A and 9B show a voltage-current conversion circuit according to a second embodiment of the present invention. A voltage-current conversion circuit 304 in FIG 9 A includes, in addition to the configuration of FIG 5 A, a second voltage-current conversion TFT 901, a second data switch 902. In the configuration of FIG 9B, the second voltage-current conversion TFT 901, the second data switch 902, and a third reset TFT 903 are provided in addition to the configuration of FIG 5B.

The second voltage-current conversion TFT 901 has a gate terminal connected to the gate terminal of the first voltage-current conversion TFT 501, a source terminal connected to a power supply line VSS, and a drain terminal connected to one end of the second data switch, whose other end is connected to the data line 107. As a result, the second data switch 902 is turned on of off as controlled by the second output enable line (not shown), whereby the drain terminal of the second voltage-current conversion TFT 901 is connected/disconnected to/from the data line 107. Therefore, by controlling the first data switch 305 and the second data switch 902, the data line 107 is driven by either the first voltage-current conversion TFT 501 or the second voltage-current conversion TFT 901. Referring to FIG 9B, the third reset switch TFT 903 is disposed for connecting the gate terminal and the drain terminal of the second voltage-current conversion TFT 901. Because the gate terminal of the third reset switch TFT 903 is connected to the gate terminals of the fist and second reset TFTs, each voltage Vth of the first and second voltage-current conversion TFTs 501 and 901 can simultaneously be corrected. The method of correcting the voltage Vth is the same as that described in connection with the first embodiment, and therefore description thereof will not be repeated.

The first and second voltage-current conversion TFTs 501 and 901 are configured to have different current supplying capabilities for the same gate potential. For the convenience of following description, it is assumed here that the first voltage-current conversion TFT 501 has a current supplying capability (x-1) times that of the second voltage-current conversion TFT 901. Driving Method

FIG 10 is a timing chart showing the driving method according to the present embodiment. The figure shows a pulse 1001 of the auxiliary circuit enable line, a control pulse 1002 supplied to the first output enable line of the system A, a control pulse 1003 supplied to the second output enable line of the system A, a control pulse 1004 supplied to the first output enable line of the system B, and a control pulse 1005 supplied to the second enable line of the system B. The first output enable pulse 1002 is a control pulse for turning on the data switch 305 to supply an output of the first voltage-current conversion TFT 501 to the data line, and the second enable pulse is a control pulse for turning on the data switch 902 to supply an output of the second voltage-current conversion TFT 901 to the data line.

In the k^th line selection period Tk-Tk+ 1 during which the output Vk of the shift register in the k^th stage is "High", the precharge potential is supplied to the data line 107 while the output enable lines are inactive and the precharge enable line PRE is active. Therefore, the precharge potential is written into the pixel when the first enable line El is activated.

Subsequently, the auxiliary circuit enable line SUB and the first enable line OAl of the system A are activated, and the first voltage-current conversion TFT supplies the current x*i to the data line 107, thereby supplying the current (x-l)*i to the auxiliary circuit and the current "i" to the pixel circuit. Thereafter, by deactivating the first output enable line OAl and the auxiliary circuit enable line SUB, activating the second output enable line OA2, and supplying current "i" to the data line 107 with the second voltage-current conversion TFT, the current "i" is directly written into the pixel circuit because only the pixel circuit is connected to the data line 107 in this period. Such a driving method allows the data line 107 to accelerate driving with the current x*i while the indirect current "i" is written into the pixel circuit, and a desired current "i" can be directly written only into the pixel circuit in the remaining period.

The advantage of thus writing the current in two stages will be described below. In the first half of the k^th line selection period Tk-Tk+ 1, the current "i" to be written into the pixel by the first voltage-current conversion TFT 501 will not exactly be equal to the desired current "i" if there is a difference in properties between the driving TFT in the auxiliary circuit and the driving TFT in the pixel circuit.

In view of the above, the present embodiment makes it possible to write a value approximate to a desired current in the first writing operation, and to more accurately write the desired current "i" in the second writing operation. This method allows the tone current to be more correctly and rapidly written into the pixels without being affected by difference in properties between the auxiliary circuit and the pixel circuit. (S) Third Embodiment Driving Method

FIG 11 is a timing chart of the gate driver 103 used for describing the driving method of a third embodiment of the present invention.

The chart shows an input pulse 1101 applied to the shift register 401 , a shift clock 1102, and an output pulse 1103 of an output V 1 of a shift register in the first stage. The pulse is sequentially shifted by the shift clock 1102 to produce an output pulse 1104 in the k^th stage, an output pulse 1105 in the (k+1 )^th stage, an output pulse 1106 in the (k+2)^th stage, and an output pulse 1107 in the (k+3)^th stage. It is assumed that the signal "High" is applied to both of the first and second enable lines El and E2, though not shown.

Because a pulse having a four clock cycle width is applied as the input pulse 1101 in FIG 11, four lines, i.e. the k^th line, the (k+l)^th line, the (k+2)^th line, and the (k+3)^th line, are simultaneously selected during the k^th line selection period Tk-Tk+ 1. When a data current 4*i is supplied to the data line 107 during this period, the data current "i", which is a quarter of the above current, is supplied to the k^th line because the driving TFTs in the k^th line, the (k+l)^th line, the (k+2)^th line, and the (k+3)^th line have the same current supplying capability. When a pulse having an "n" clock cycle width is applied as an input pulse, a total of "n" lines are simultaneously selected. Thus, by supplying a data current of n*i to the data line 107, the data current "i" equal to one n^th (1/n) of that current is supplied into the pixel circuit.

When "n" is 10 and the data line of 10 pF is driven with the data current of 1 μ A, a voltage change of 3 V can be achieved in 30 μ s. Therefore, the data current of 0.1 μ A can be written into the pixels within one horizontal period even with the QVGA resolution.

When an auxiliary circuit having a current supplying capability six times that of the pixel circuit is also used, the current equal to one tenth of that supplied to the data line is written into the pixel by simultaneously selecting four lines, and naturally the result same as described above can be achieved.

Unlike the configuration with a dedicated auxiliary circuit, this method provides an advantage of using the pixel circuit as a substitute for the auxiliary circuit by selecting a plurality of lines including the line to which the data is written, and varying the current supplying capability by changing the input pulse width.

It should be noted that the plurality of selected lines are not necessarily the adjoining select lines as in the example of FIG 11, and that they may be spaced apart by several lines or by any distance. In this embodiment, light emission based on the correct data occurs from the time the current data for the pixel of interest is written to the time the current data for another pixel is written. PARTS LIST

1 organic EL display

101 active matrix display

102 data driver

103 gate driver

104 precharge circuit

105 display device

106 control circuit

107 data line

108 first select line

109 second select line

110 auxiliary circuit

111 input bus

112 data control bus

113 gate control bus

201 organic EL element

202 driving TFT

203 switch TFT

204 light control TFT

205 gate TFT

206 storage capacitor

210 select line

211 current supply line

212 fixed potential line 220 data line

230 current source

240 P channel TFT Parts List cont'd

250 P channel TFT

260 TFT

270 N channel TFT

280 storage capacitor

290 organic EL element

301 shift register

302 pulse enable circuit

303 video switch

304 voltage-current conversion circuit

305 data switch

306 precharge switch

307 auxiliary circuit

311 RGB video signal line

312 driver select line

313 output enable line

314 precharge enable line

315 potential supply line

316 enable line

317 select line

401 shift register

402 first enable circuit

403 second enable circuit

404 first buffer

405 second buffer

411 enable control lines

501 voltage-current conversion TFT Parts List cont'd

502 storage capacitor

503 reset TFT

504 reset TFT

505 reset capacitor

701 pulse

702 pulse

703 pulse

704 pulse

705 pulse

706 pulse

707 pulse

708 pulse

709 data signal

901 conversion TFT

902 data switch

903 reset TFT

1001 pulse

1002 control pulse

1003 control pulse

1004 control pulse

1005 control pulse

1101 input pulse

1102 shift clock

1103 output pulse

1104 output pulse Parts List cont'd

1105 output pulse

1106 output pulse

1107 output pulse

Claims

CLAIMS:

1. A display device, comprising: an active matrix display array including pixel circuits arranged in a row and column matrix, each having a current driven diode emissive element, and a plurality of thin film transistors for controlling the diode emissive element; a data line provided corresponding to each column of the matrix for supplying a data current to the pixel circuit in the corresponding column; a data driver for controlling supply of the data current to the data line; a select line provided corresponding to each row of the matrix for supplying a select signal to the pixel circuit in the corresponding row; a gate driver for supplying the select signal to the select line; and an auxiliary circuit connected to the data line; wherein: the auxiliary circuit is capable of supplying part of the data current supplied from the data driver to the data line.

2. A display device according to claim 1 , wherein: the auxiliary circuit has a current supplying capability larger than the pixel circuit.

3. A display device according to claim 1 or 2, wherein: the auxiliary circuit is formed of a plurality of auxiliary circuits having different current supplying capabilities for one data line.

4. A display device according to claim 1, wherein: the auxiliary circuit is provided to be connectable to the data line through a switch, and is connected to the data line at least once in a horizontal period.

5. A display device according to claim 1 , wherein: the data driver is capable of supplying a plurality of data currents to the data line for the same data voltage, and the plurality of data currents are switched within one horizontal period.

6. A display device according to claim 5, wherein: the plurality of data currents are supplied to the data line as a current larger than a data current written to a pixel in a first half of one horizontal period.

7. A display device according to any one of claims 1 -6, wherein: the gate driver simultaneously selects a plurality of select lines.

8. A display device, comprising: an active matrix display array including pixel circuits arranged in a matrix, each having a diode emissive element driven by a current, and a plurality of thin film transistors for controlling the diode emissive element; a data line provided corresponding to each column of the matrix for supplying a data current to the pixel circuit in the corresponding column; a data driver for controlling supply of the data current to the data line; a select line provided corresponding to each row of the matrix for supplying a select signal to the pixel circuit in the corresponding row; and a gate driver for supplying the select signal to the select line; wherein the gate driver simultaneously selects a plurality of select lines to simultaneously supply to a plurality of pixel circuits the data current supplied from the data driver to the data line.