WO2006023996A2

WO2006023996A2 - Methods and apparatus for error correction of transparent gfp (generic framing procedure) superblocks

Info

Publication number: WO2006023996A2
Application number: PCT/US2005/030172
Authority: WO
Inventors: Santanu Bhattacharya; Neeraj Gupta; Yogesh Mittal; Priya Darshini; Suvhasis Mukhopadhyay
Original assignee: Transwitch Corporation
Priority date: 2004-08-23
Filing date: 2005-08-22
Publication date: 2006-03-02
Also published as: US20060041826A1; EP1782542A2; US7260767B2; CN101160727A; EP1782542A4; CN101160727B; WO2006023996A3

Abstract

Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8x8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

Description

METHODS AND APPARATUS FOR ERROR CORRECTION OF TRANSPARENT GFP (GENERIC FRAMING PROCEDURE) SUPERBLOCKS

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates broadly to telecommunications. More particularly, this invention relates to highly efficient error correction of GFP superblocks.

2. State of the Art

The Synchronous Optical Network (SONET) or the Synchronous Digital Hierarchy (SDH), as it is known in Europe, is a common telecommunications transport scheme. SONET was designed in the early 1980s to accommodate a plurality of time division multiplexed continuous signals such as T-I or E-I signals. T-I /E-I signals were designed in the 1960s to carry a plurality of digitized audio (telephone) signals from one telephone company office (switch) to another.

Developed in the early 1970's, ETHERNET was designed primarily to allow multiple personal computers to share a single laser printer. Although ETHERNET has gone through many changes since the first version was used in 1973, it is still fundamentally not synchronous. Unlike SONET/SDH which was developed to carry many continuous streams of data multiplexed in a regularly occurring frame of fixed length, ETHERNET was designed to carry discontinuous data streams in randomly occurring packets of widely varying length. A word used to describe this nature of ETHERNET is "bursty". In addition to ETHERNET, some other networking protocols have been developed for storage area networks (SANs). These other protocols include Fiber Channel, ESCON (enterprise system connection), and FICON (fiber connection). They are similar to ETHERNET in that they are bursty.

For many years, it has been recognized that it would be desirable to transmit ETHERNET packets over long distances using a SONET/SDH network. However, because of the fundamental differences between synchronous frames and asynchronous packets, some mechanism was needed to encapsulate the ETHERNET data within a SONET/SDH frame. The challenge in doing this is to fill the SONET frame with as much ETHERNET data as possible so that bandwidth is not wasted while at the same time providing minimal latency (time data waits in a buffer before being transmitted). One of the latest methods for accomplishing this task is called the Generic Framing Procedure (GFP). GFP is "generic" because it is designed to transport any signal including ETHERNET, Fiber Channel, ESCON, FICON, and others over fixed data rate optical channels in a SONET/SDH network or OTN (optical transport network).

GFP is used in conjunction with other SONET/SDH specifications such as Virtual Concatenated Groups (VCGs) and Link Capacity Adjustment Scheme (LCAS) to map variable length packets into "containers" (also known as "tributaries") of a SONET/SDH frame.

There are currently two modes of mapping data into a GFP frame: frame mapped GFP (GFP-F) and transparent mapped GFP (GFP-T). GFP-F is used for ETHERNET (some versions but not all) and other protocols where the entire client frame is mapped into a single GFP frame. GFP-T facilitates the transport of block coded signals such as those of Fiber Channel, ESCON, FICON, and Gigabit ETHERNET, which also require very low transmission latency.

Prior art Figure 1 illustrates the fields of a GFP frame. The two basic parts of the frame are the core header (4 bytes) and the payload area (variable length up to 65535 bytes). The core header includes a payload length indicator (PLI, 2 bytes) and the core header error correction (cHEC) code (2 bytes). The payload area includes the payload header (4 to 64 bytes), the payload information field (up to 65531 bytes), and an optional payload FCS (4 bytes). The payload header includes the type (4 bytes) and an extension header identifier (O to 60 bytes).

The present invention is concerned with GFP-T. As mentioned above GFP-T facilitates the transport of block coded signals which also require very low transmission latency. These signals are encoded by clients with an 8B/10B block code. This code is used to communicate data and control information. More particularly, the 8-bit data values are mapped (encoded) into a 10-bit "transmission character". The code assignment is arranged so that the number of Is and Os transmitted on the line remains balanced. This increases the number of line transitions, thereby facilitating PLL synchronization. It also maintains DC balance over time. In addition, twelve of the 10- bit codes are reserved for use as control codes so that the data source may signal the data sink.

In order to transport 8B/10B encoded signals over the SONET/SDH network, GFP-T decodes the 8B/10B characters into 8-bit data characters and control codes. Eight of the decoded characters are mapped into the eight payload bytes of a 64B/65B code. This is shown by example in prior art Figure 2. The (leading) flag bits of the 64B/65B code (shown as octet L in Figure 2) indicate whether the 64B/65B block includes any control codes, i.e. a flag=l indicates that the octet in the corresponding position of the next eight octets is a control code. In a GFP-T frame, after the 4 byte payload header, the payload area is filled with a plurality of "superblocks". Each superblock includes eight 64B/65B blocks and one 16-bit CRC, i.e. 67 bytes. The last octet of the superblock before the CRC includes eight flag bits. This is often referred to as the "superblock control byte". Prior art Figure 3 illustrates the mapping of the superblock.

In order to address the physical properties of the transport medium and to aid in maintaining synchronization, GFP frames are scrambled by a self-synchronous scrambler. The scrambler uses a polynomial of x ³+l. The scrambler takes each bit of the payload area (including the superblock CRC) and exclusively ORs it with the scrambler output bit that precedes it by 43 bit positions. The scrambler state is retained between successive GFP frames, making it more difficult for a user to purposely choose a malicious payload pattern (e.g. one which would cause loss of synchronization). The superblock CRC is calculated prior to scrambling and is checked at the decoder after descrambling. An unfortunate drawback of this scrambling technique is that each transmission error produces a pair of errors (43 bits apart) in the descrambled data stream. The CRC, therefore, must be able to correct these two errors. The recommended CRC generator polynomial generates a superblock CRC which can detect three bit errors, correct single bit errors, and correct double bit errors spaced 43 bits apart. To accomplish this, the syndromes for single bit errors and double bit errors spaced 43 bits apart are all unique.

When demapping a GFP-T signal, the superblock control byte must be "realigned" (the flag bits moved back to their original leading bit locations) before the 64B/65B code can be mapped back into 8B/10B code. Before this is done, the superblock CRC is used to detect and possibly correct bit errors in the superblock. The recommended demapping procedure is detailed in ITU specification G.7041, the complete disclosure of which is hereby incorporated herein by reference.

The following description is taken from the G.7041 specification. The 16 error control bits in a superblock contain a CRC-16 error check code over the 536 bits in that superblock. If the demapper detects an error, it should output either 1OB error characters or unrecognized 1OB characters in place of all of the client characters contained in that superblock. This replacement guarantees that the client receiver will be able to detect the presence of the error. The generator polynomial for the CRC-16 is G(x) = x¹ + x¹⁵ + x¹² + x¹⁰ + x⁴ + x³ + x² + x + χ° with an initialization value of zero, where x¹⁶ corresponds to the MSB and x° to the LSB. The superblock CRC is generated by the source adaptation process using the following steps:

1. The first 65 octets of the superblock are taken in network octet order, most significant bit first, to form a 520-bit pattern representing the coefficients of a polynomial M(x) of degree 519.

2. M(x) is multiplied by x¹⁶ and divided (modulo 2) by G(x), producing a remainder R(x) of degree 15 or less.

3. The coefficients of R(x) are considered to be a 16-bit sequence, where x¹⁵ is the most significant bit.

4. This 16-bit sequence is the CRC-16.

Single error correction is also possible with this CRC-16. However, since the sink adaptation process performs the CRC-16 check after the payload descrambling is performed, the error correction circuit should account for single bit errors as well as double errors spaced 43 bits apart coming out of the descrambler.

The sink adaptation process performs steps 1-3 in the same manner as the source adaptation process. In the absence of bit errors, the remainder shall be 0000 0000 0000 0000. Though not stated in the G.7041 specification, when the remainder is not zero it is referred to as a "syndrome". Syndromes can be used to detect the location of a bit error in conjunction with a syndrome table which has a 1 : 1 correspondence with each bit in the payload.

The G.7041 recommendation has several disadvantages. Processing an entire superblock according to the recommendation requires a 536-bit datapath and a relatively large amount of storage space which complicates implementation on a chip. It is also difficult to support high speed applications when processing all sixty-seven bytes at one time. The physical size of the logic introduces latency.

Although parts of the G.7041 recommendation can be ignored while still maintaining interoperability, there are several issues which cannot be ignored. These issues include the following: the flag byte (which is the last byte before the FCS bytes in the superblock) must be corrected before processing any of the other bytes in the superblock; double bit error correction requires that errors be correctable for bits which are 43 bits apart; and there needs to be an indication of whether a detected error has been corrected.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide methods and apparatus for egress side GFP-T superblock error detection and correction.

It is another object of the invention to provide said methods and apparatus using a reduced datapath.

It is a further object of the invention to provide said methods and apparatus with the flag byte being processed before the other bytes.

It is also an object of the invention to provide said methods and apparatus detecting and correcting double bit errors as well as single bit errors. It is an additional object of the invention to provide said methods and apparatus indicating whether detected errors have been corrected.

In accord with these objects, which will be discussed in detail below, the methods of the invention include buffering the 64 bytes of data from a superblock in an 8x8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the flag byte and the 64 data bytes are corrected by comparing the calculated CRC remainder to a single bit error syndrome table and correcting the data, with the flag byte being corrected first. The data and flag byte are then forwarded to the second stage. In the second stage, the data and flag byte are corrected by comparing the calculated CRC remainder to a double bit error syndrome table. The flag byte is checked first by comparing the CRC remainder to syndrome table locations forty-three bits before the eight bits of the flag byte. The data and flag byte are then forwarded to the third stage. In the third stage, the second bit of the double bit error is corrected based on its position relative to the first bit of the double bit error (i.e. 43 bits apart) if the second error is in the same superblock. The error corrected data and flag byte are then forwarded from the third stage to control word realignment logic. According to the invention, processing is done in eight byte chunks at each stage iteratively until all bytes are processed, after which they are forwarded to the next stage. This allows a much narrower datapath which facilitates chip design and reduces latency because the logic circuits are simpler. According to the presently preferred embodiment, when an uncorrected error is detected, 1OB error characters are output only for the last eight bytes of the superblock rather than all of the superblock as recommended in G.7041. This saves storage (56 bytes) and reduces delay in processing because bytes from the payload may continue to move through the process before the entire payload has been checked.

Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a prior art diagram of a GFP frame;

Fig. 2 is a prior art diagram illustrating the mapping of 8B/10B codes into a 64B/65B code;

Fig. 3 is a prior art diagram illustrating the mapping of 64B/65B codes into a GFP-T superblock;

Fig. 4 is a high level schematic diagram illustrating an apparatus for performing the methods of the invention;

Fig. 5 is a high level flow chart illustrating single bit error correction methods according to the invention;

Fig. 6 is a high level flow chart illustrating correction of the first bit error of a double bit error according to the invention;

Fig. 7 is a high level flow chart illustrating correction of the second bit error of a double bit error according to the invention;

Fig. 8 is a single bit error syndrome table; and

Fig. 9 is a double bit error syndrome table.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Turning now to Fig. 4, an apparatus 10 which is suitable for implementing the methods of the invention is shown in a high level block diagram. The incoming superblock is stored in two buffers 12 and 14. The buffer 12 stores the 64 bytes of data and the buffer 14 stores the flag byte. The incoming superblock is also passed through a CRC calculation circuit 16 which outputs the calculated CRC remainder for the superblock to a first comparison logic 18. The first comparison logic 18 compares the calculated CRC remainder to entries in a single bit error syndrome table 20 (described in more detail below with reference to Figures 5 and 8) and outputs a bit error location to single bit error correction logic 22 which also receives data and the flag byte from the buffer 12 and the storage 14. The correction logic 22 corrects single bit errors by inverting the bit at the bit error location indicated by the comparison logic 18.

The calculated CRC remainder from the circuit 16 is also provided to a second comparison logic 24 which compares it to entries in a double bit error syndrome table 26 (described in more detail below with reference to Figures 6, 7 and 9) and outputs a bit error location to a first double bit error correction logic 28 which also receives data and the flag byte from the single bit error correction logic 22. The correction logic 28 corrects the first bit error of double bit errors (or the second bit error if it is in the flag byte) by inverting the bit at the bit error location indicated by the comparison logic 24.

The output of the comparison logic 24 is also provided to second error position calculation logic 30 which adds forty-three to the bit error location and forwards it to a second double bit error correction logic 32. The logic 32 also receives data and the flag byte from the first double bit error correction logic 28. The correction logic 32 corrects the second bit error of double bit errors by inverting the bit at the bit error location indicated by the logic 30. After error correction, the data bytes and the flag byte are forwarded to control word realignment logic and buffer 34 which realigns the flag bits in front of the data bytes, then forwards the realigned superblock for further processing.

According to the presently preferred embodiment, the data bytes are processed eight bytes at a time. For example, one hundred twenty-eight bytes are read from the syndrome table (two bytes for every bit location in eight bytes of data). See Figs. 8 and 9 where each line of the table refers to one byte, each entry corresponding to one bit. If the CRC remainder matches an entry in the syndrome table as found by the comparison logic 18, the corresponding bit in the eight bytes of data is inverted by the correction logic 22. The data is then shifted to the next stage (28) in the process and the next 128- bytes of the syndrome table is examined by the comparison logic 18 in conjunction with the next eight bytes of data from the buffer 12. The process proceeds in a pipeline fashion so that while the logic 18 and 22 are processing the second eight bytes, the logic 24 and 28 are processing the first eight bytes. According to the presently preferred embodiment, the flag byte is processed first so that it is always the first to arrive at the control word realignment logic 34. When the last byte of the superb lock data leaves the buffer 12 a new flag byte replaces the contents of the storage 14 and the buffer 12 contains eight bytes of data from the next superblock. The process is scalable up to an STS- 192 signal without timing difficulty.

Referring now to Fig. 5, the operation of the single bit error correction logic is illustrated in a simplified schematic flow chart. First, at 100, the calculated CRC remainder is compared to the last row of the single bit error syndrome table (eight 16- bit entries) of Fig. 8. If the CRC remainder is equal to any of the eight entries in the row, an error in the flag byte is indicated and the corresponding bit in the flag byte is inverted at 102. In other words, if the remainder is equal to the first entry in the last row of the table, the first bit of the flag byte is inverted. If the remainder is equal to the second entry, the second bit of the flag byte is inverted, etc.

After the flag byte is processed for single bit error the calculated CRC remainder is compared at 104a to the first eight rows of the syndrome table of Fig. 8. These sixty-four entries correspond to the sixty-four bits of the first eight byte chunk of the sixty-four byte data payload. If a match is found, the corresponding bit is inverted at 106a. This process is repeated with the next eight rows of the table and the next eight bytes of data until all sixty-four bytes of data have been processed at 104h and corrected, if appropriate, at 106h.

After the flag byte is processed for single bit error and while the calculated CRC remainder is compared to the first eight rows of the syndrome table of Fig. 8, the flag byte is passed to the next stage where it is processed for double bit errors as illustrated in Fig. 6.

If the first bit error of a double bit error exists in the flag byte, the second bit error will appear in the next superblock. In this case, the error will have been detected as a single bit error and will have been corrected in the first stage described with reference to Fig. 5. If the second bit error of a double bit error is in the flag byte, then both bit errors can be corrected. Similarly, if both bit errors occur in the sixty-four data bytes, both bit errors can be corrected.

Turning now to Figures 6 and 9, according to the presently preferred embodiment, a second error correction flag is set at 108 to "disabled" until a double bit error is detected. At 110, the calculated CRC remainder is compared to the eight entries in the table (Figure 9) which precede the last eight entries by 43 -bits. This attempts to find a second error of a double bit error in the flag byte. If a match is found at 110, the appropriate bit of the flag byte is corrected at 112. Second error correction remains disabled because the second error was actually corrected at 112. The data bytes are processed at 114a-h and if an error is found, it is corrected at one of 116a- 116h. In the case where an error had been corrected in the flag byte, there is no need to enable second error correction. If second error correction is enabled as determined at 118, and an error was corrected at 116a-l 16h, the position of the bit error is incremented by forty-three to thereby determine the location of the second of the double bit error. This location is forwarded to the second double bit error correction logic which functions as illustrated in Fig. 7.

Correction of the second bit error of a double bit error is illustrated in Fig. 7. If second error correction is enabled and the second bit location is known as determined at 122, the second bit error is corrected at 124.

There have been described and illustrated herein methods and apparatus for error correction of transparent GFP superblocks. While particular embodiments of the invention have been described, it is not intended that the invention be limited thereto, as it is intended that the invention be as broad in scope as the art will allow and that the specification be read likewise. It will therefore be appreciated by those skilled in the art that yet other modifications could be made to the provided invention without deviating from its spirit and scope as claimed.

Claims

What is claimed is:

1. A method for correcting errors in a GFP-T (generic framing procedure-transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising: buffering the 64 bytes of data in one buffer; buffering the flag byte in a separate buffer; calculating the CRC remainder; comparing the CRC remainder to a single bit error syndrome table; correcting a single bit error if the CRC remainder matches an entry in the single bit error syndrome table; comparing the CRC remainder to a double bit error syndrome table; and correcting a double bit error if the CRC remainder matches an entry in the single bit error syndrome table, wherein the flag byte is processed first and the data bytes are processed eight bytes at a time.

2. The method according to claim 1, wherein: the method is performed in three stages, in the first stage the flag byte and the data are subjected to single bit error correction, in the second stage the flag byte is subjected to second error double bit error correction and the data is subjected to first error double bit error correction, and in the third stage the data is subjected to second error double bit error correction.

3. An apparatus for correcting errors in a GFP-T (generic framing procedure- transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising: a data buffer for buffering the 64 bytes of data; a flag byte buffer for buffering the flag byte; a CRC calculation circuit for calculating the CRC remainder; a single bit error syndrome table; first comparison logic coupled to said CRC calculation circuit and to said single bit error syndrome table; single bit error correction logic coupled to said data buffer, said flag byte buffer, and to said first comparison logic; a double bit error syndrome table; second comparison logic coupled to said CRC calculation circuit and to said double bit error syndrome table; double bit error correction logic coupled to said single bit error correction logic and to said second comparison logic, wherein the flag byte is processed first and the data bytes are processed eight bytes at a time.

4. The apparatus according to claim 3, wherein: said double bit error correction logic includes first error correction logic coupled to said single bit error correction logic and to said second comparison logic, and second error correction logic coupled to said first error correction logic and to said second comparison logic, and wherein the flag byte and the data are subjected to single bit error correction by said single bit error correction logic, the flag byte is subjected to second error double bit error correction by said first error correction logic, the data is subjected to first error double bit error correction by said first error correction logic, and the data is subjected to second error double bit error correction by said second error correction logic.

5. The apparatus according to claim 4, wherein: said double bit error correction logic includes a second error position calculation logic coupled to said second comparison logic and said second error correction logic.

6. An apparatus for correcting errors in a GFP-T (generic framing procedure- transparent mode) superblock having 64 bytes of data, a flag byte, and a 16 bit CRC, comprising: a data buffer means for buffering the 64 bytes of data; a flag byte buffer means for buffering the flag byte; a CRC calculation circuit means for calculating the CRC remainder; a single bit error syndrome table means for indicating the location of a single bit error; first comparison logic means coupled to said CRC calculation circuit means and to said single bit error syndrome table means, said first comparison logic means for determining whether the CRC remainder matches an entry in said single bit error syndrome table means; single bit error correction logic means coupled to said data buffer means, said flag byte buffer means, and to said first comparison logic means, said single bit error correction logic means for correcting a single bit error indicated by said first comparison logic means; a double bit error syndrome table means for indicating the location of a first error of a double bit error; second comparison logic means coupled to said CRC calculation circuit means and to said double bit error syndrome table means, said second comparison logic means for determining whether the CRC remainder matches an entry in said double bit error syndrome table means; double bit error correction logic means coupled to said single bit error correction logic means and to said second comparison logic means, said double bit error correction logic means for correcting a double bit error indicated by said second comparison logic means, wherein the flag byte is processed first and the data bytes are processed eight bytes at a time.

7. The apparatus according to claim 6, wherein: said double bit error correction logic means includes first error correction logic means coupled to said single bit error correction logic means and to said second comparison logic means, said first error correction logic means for correcting one error of a double bit error, and second error correction logic means coupled to said first error correction logic means and to said second comparison logic means, and wherein the flag byte and the data are subjected to single bit error correction by said single bit error correction logic means, the flag byte is subjected to second error double bit error correction by said first error correction logic means, the data is subjected to first error double bit error correction by said first error correction logic means, and the data is subjected to second error double bit error correction by said second error correction logic means.

8. The apparatus according to claim 7, wherein: said double bit error correction logic means includes a second error position calculation logic means coupled to said second comparison logic means and said second error correction logic means, said second error position logic means for determining the location of a second error double bit error.