WO2006024025A2

WO2006024025A2 - Optical-mode-confined and electrical-current-confined semiconductor light sources utilizing resistive interfacial layers

Info

Publication number: WO2006024025A2
Application number: PCT/US2005/030570
Authority: WO
Inventors: Dennis G. Deppe
Original assignee: Nanosource, Inc.
Priority date: 2004-08-25
Filing date: 2005-08-24
Publication date: 2006-03-02
Also published as: WO2006024025A3

Abstract

A semiconductor device comprises: a first region (180) having a semiconductor interface between a first semiconductor (130) and a second semiconductor (150), and a second region (170), laterally adjoining the first region (180). The first semiconductor (130) is characterized by Fermi level pinning within an energy gap of the first semiconductor material (130) and further characterized by a first conductivity level in the vicinity of the interface that substantially blocks electrical current flow through the semiconductor interface. The second region (170) includes a semiconductor characterized by a second conductivity level substantially higher than the first conductivity level such that the second region (170) is adapted to enable electrical current to pass through the second region (170), thus defining a current injection path in the device.

Description

OPTICAL-MODE-CONFINED AND ELECTRICAL-CURRENT- CONFINED SEMICONDUCTOR LIGHT SOURCES UTILIZING RESISTIVE INTERFACIAL LAYERS

RELATED APPLICATION

[0001] This application claims the benefit of priority from U.S. Provisional

Application No. 60/604,790, Attorney Docket No. 60886-5003-PR, filed August 25, 2004, which provisional application is incorporated by reference herein in its entirety.

TECHNICAL FIELD

[0002] The disclosed embodiments relate generally to solid-state devices, and more particularly to semiconductor optoelectronic diodes.

BACKGROUND [0003] III-V semiconductors are used to fabricate optoelectronic devices including semiconductor light sources such as laser diodes, superluminescent diodes, optical amplifiers, optical switches, and light emitting diodes. These devices generally require electrical confinement as well as optical mode confinement, so that the electrically injected current is directed into an active volume that also confines one or more optical modes of a cavity. The active volume may be based on bulk semiconductor confined by heterojunctions, planar quantum wells, quantum wires or quantum dots. These active materials may include InGaN for ultraviolet and blue emission, InGaAlP for visible light emission between 600 nm to 700 nm, AlGaAs for light emission in the 700 nm to 850 nm range, GaAs for emission in the 800 to 880 nm range, InGaAs for emission in the 900 nm to 1.2 μm range, and InGaNAs for emission in the 1.1 μm to 1.6 μm wavelength range. Combinations of these materials, including their nanostructures (quantum wires or quantum dots), can also be used to obtain even greater wavelength emission ranges for a given VCSEL substrate and mirror material. For example, planar layers of GaInNAs or GaAsSb, or InGaAs, or their nanostructures can be used to obtain 1.3 μm emission. Generally very high quality semiconductor interfaces are thought to be needed for semiconductor light sources. This is especially true for the active materials where light generation occurs.

[0004] For example, semiconductor laser diodes can be made into compact, high efficiency optical sources. A lateral-cavity laser diode generally is formed from a cavity in which the lasing optical mode propagates back and forth along a path that lies within the plane of the epitaxial crystal growth more or less collinear with an epitaxial film. Lateral cavity lasers are useful for high power light sources, fiber communication, free space communication, sensing, integrated photonics, and many more applications.

[0005] A vertical-cavity laser diode is formed from a cavity in which the lasing optical mode propagates along a path that lies perpendicular to the plane of the epitaxial crystal growth. A vertical-cavity surface-emitting laser (VCSEL), in which the cavity is a vertical cavity and light emission is extracted from the surface of the epitaxial film, can be formed from epitaxial semiconductor materials to create a very compact, low optical loss, all-semiconductor microcavity. The VCSEL has become an important laser device since it can operate efficiently at low power levels with good beam characteristics, and is relatively easy to manufacture. VCSELs have applications as fiber optic sources and in sensing, as well as for bar code scanners, compact disk storage, displays, solid state lighting, and others. In a VCSEL a GaAs substrate is often used on which

distributed Bragg reflecting (DBR) mirrors and active materials are grown using single crystal epitaxy. Other semiconducting or nonsemiconducting substrates, such as InP or sapphire, can be used with different active materials to create VCSELs that operate over a wide range of wavelengths.

[0006] Conventional techniques have also shown that it is also possible to combine a lateral-cavity and a vertical-cavity, through confinement of the vertical mode with mirrors while obtaining a significant propagation component of the lasing mode, into a lateral- vertical-cavity laser. These type s of devices have been demonstrated in which the laterally propagating mode is strongly influenced by the vertical-confinement. These types of combined lateral-vertical-cavity laser diodes can provide greater control over the optical frequency of the laterally propagating mode, while maintaining a nearly planar crystal surface on which to perform epitaxial growth. Lateral-cavity, vertical-cavity, and lateral- vertical-cavity laser diodes generally use conducting materials within the cavity to excite the optically active material. Generally, semiconductor materials conduct p- and n-type charge to inject electrons and holes into the active material and obtain light emission, with the conducting materials being placed between the two mirrors of the cavity, or with the mirrors themselves forming the conducting materials. They may also use unipolar injection structures to pass only electrons through gain stages to obtain light emission. In this type of device the single charge type makes transitions within its energy band, utilizing quantum confinement structures to obtain light emission from its intraband or intralevel relaxations. In each of these cases both mode confinement and current confinement present important consideration in device performance and how that device performance impacts the systems that use the laser diode devices.

[0007] In order to reduce the operating current, improve the efficiency, and improve the speed of either lateral-cavity, vertical-cavity, or combined lateral-vertical-cavity laser diodes, and to control the optical mode of optical amplifiers, superluminescent diodes, optical switches, or light emitting diodes, it is highly desirable to laterally confine both the optical mode and the injected electrical current to nearly the same device volume. Although conventional techniques have shown that the simultaneous electrical and optical confinement can be obtained by simply etching a free-standing mesa or pillar to remove some of the semiconductor, and thus form index guides and restrict the current flow, this approach leads to surface damage and optical scattering, and the optical loss and impact of surface damage increase as the size of the mesa or pillar is reduced. The increasing optical loss with reducing mesa or pillar size also leads to an undesirable increase in threshold current density upon reducing the laser device's active size below a certain size. If no lateral confinement exists, and the lasing mode is only confined due to the formation of a gain region, diffraction loss degrades the laser diode's performance through increasing the lasing threshold and increasing its internal optical loss with reducing device size, which in turn can reduce the efficiency, operating speed. Therefore obtaining very low loss optical confinement combined with current confinement to the optical mode area is important to achieving high speed, high efficiency, and high performance.

[0008] It is also possible to control both the optical mode and the electrical injection through implantation of impurities such as protons or oxygen into the semiconductor, and therefore form highly resistive regions that limit the current injection to form optical gain or light emission only in certain regions of the semiconductor. This technique, though mostly free of strain since it is based only on semiconductor materials, has limited application to confining the electrical current and confining the optical mode. If the implantation enters the region of light generation or amplification, the resulting defects formed can increase the operating current and reduce the device reliability. If the implantation defects and damage is maintained sufficiently removed from the active material to avoid damage of the active region invariably loss of electrical confinement occurs, combined with optical loss due to diffraction. [0009] Another means used in conventional techniques is to confine an optical mode and electrical injection current path to the same area, especially for VCSELs, is through use of conversion of AlGaAs layers to form internal thin but bulk layers of AlO through steam oxidation. These layers are generally 200 A or thicker. The AlO material thus formed possesses a smaller refractive index than the surrounding semiconductor material and can optically confine a lasing mode, and at the same time serves as an electrical insulator to direct current into the region of the lasing mode. This steam oxidation process, though producing lasers that can exhibit good device characteristics, requires careful control to avoid introducing strain due to the thick oxide layers that degrade the device reliability. Another problem is that the steam oxidation is a bulk diffusion process and requires careful timing, and can produce poor uniformity in device size across a wafer or from wafer to wafer, hi addition, the AlO formed from steam oxidation has a thermal expansion coefficient that generally differs from the surrounding semiconductor material, and as such can in addition to degrading device reliability limits the thermal annealing steps that can be performed on the device. If the layer to be steam oxidized is made thinner than ~150 A, its steam oxidation rate decreases with the rate highly sensitive to the layer thickness. Another problem with the steam oxidation is that it has not proven as useful to fabricate lasers or light emitting diodes formed from materials other than those containing AlGaAs with Al making up more than 90% of the combined Al and Ga composition.

[0010] Still another means used in conventional techniques to confine an optical mode and electrical injection path is to etch rather deep ridge or pillar, and then regrow epitaxial semiconductor of a reduced refractive index relative to the active material over the ridge that contains either a deep-level impurity that renders the regrown material semi- insulating, or to regrow materials of alternating conductivity types to form reverse biased p- n junctions. The epitaxially regrown materials then directs the current into the device active region through its p-n junctions, or low bulk resistivity, and confines the light to the same active region through optical waveguiding. The resulting device, called a buried heterostructure since it includes heterojunctions generally in 3 dimensions due to the overgrowth, can provide excellent performance because of its combined optical and electrical confinement. However, the deep etching and overgrowth require a great deal of optimization and because of this are difficult processes to carry out with high reproducibility in a manufacturing environment, and variations in fabrication can lead to poor yield and poor reliability. The deep etching must be carefully controlled to obtain smooth sidewalls, and the patterns that can be implemented are limited by the etch behavior of the sidewalls. Strain and defects that result from the overgrowth of the deeply etched structure can impact the device reliability. Therefore the large aspect ratio of the etch depth to device dimension complicate the device fabrication, and can reduce the yield and reliability.

[0011] Light emitting diodes also benefit from confinement of the electrical current injection and confinement of the optical mode. Generally, the light is emitted through an opening in an electrode to the diode, and current must be passed from the electrode into the region that generates the light while leaving an opening in the electrode through which the light may escape. Conventional techniques have shown that confining the optical mode to a small volume may be used to further control the efficiency and directionality of the light signal through cavity enhancement of the emission rate into preferred directions, but placement of the electrodes, while maintaining efficient injection of the current into the light emitting region, and efficient light emission through the electrode opening, is difficult.

[0012] There is also interest in reducing semiconductor light sources to very small dimensions. These technologies used in scaling devices include photonic crystals, microdisk lasers, and microcavity VCSELs. By reducing the active volume of the light source the efficiency can be improved for low power operation, and the modulation speed can be increased. These benefits stem from the photonic confinement in a small optical cavity.

However, efficient electrical injection into such structures has been difficult, and the fabrication is complicated by the small feature sizes. Again fabricating devices with large aspect ratios can become impractical, especially if the device itself consists of thin film semiconductor material such as commonly used for photonic crystals, microdisks, and sometimes VCSELs. A fabrication approach that maintains planarity while also providing the needed electrical injection and photonic confinement is therefore highly desirable for these new semiconductor light sources. The inclusion of dielectric materials to provide the confinement can again introduce strain that complicates the fabrication and degrades the device reliability.

[0013] There has also been efforts in the past in developing optoelectronic devices that utilize thin semiconductor films to confine light, such as air-semiconductor Bragg reflectors or air-clad lateral waveguides such as used in photonic crystal or other lateral cavity lasers. Serious drawbacks of such devices are electrical contacting, mechanical stability due to internal strain caused by non-semiconductor materials, and dissipation of excess heat generated by the active device.

[0014] Therefore semiconductor fabrication processes for photonic devices based on lasing, light amplification, switching, or spontaneous light emission in general require deep etching, thick insulating layers of either semiconductor material or materials other than semiconductors that can cause strain, or regrowth over etched structures that have large aspect ratios of their height to their lateral dimensions. They can be difficult to implement to obtain highly uniform device performance across a wafer or from wafer-to-wafer in a manufacturing environment, and strain due to the non-semiconductor materials in general have different thermal expansion coefficients from the semiconductor and can cause reduced device reliability. In addition, scaling of the optoelectronic sources to small sizes can be difficult to implement because of the aspect ratios that result from etching or active materials, or the necessity of timing associated with diffusion processes used to form thick oxide layers. On the other hand, if nearly planar fabrication is used in these technologies, such as proton or some other impurity implantation to form highly resistive layers, the efficiency of the electrical injection is reduced or the active semiconductor materials may be degraded.

[0015] Thus, the art of semiconductor lasers, superluminscent diodes, and light emitting diodes, although producing various methods to form semiconductor lasers using lateral cavity laser diodes, vertical-cavity laser diodes, and lateral-vertical-cavity laser diodes, and light emitting diodes, recognizes a need for a device structure that can provide confinement of the electrically injected current to the same area as a confined optical mode, to give high operating efficiency, and be fabricated with a high reproducibility across a wafer and from wafer to wafer, and that is absent of mechanical strain and lateral size variation due to external process parameters to allow device scaling to small dimensions. In addition, there is a recognized need for a fabrication technique that can be applied to thin film devices for the purpose of introducing air-semiconductor interfaces in close proximity to an active material in order to achieve strong optical mode confinement to a small volume, and yet provide for efficient electrical current injection into the device and efficient excess heat dissipation from the device. SUMMARY

[0015] The disclosed embodiments are directed to lateral-cavity diodes, vertical- cavity diodes, lateral-vertical-cavity diodes, superluminescent diodes, optical amplifiers, optical switches, and light emitting diodes that use lateral electrical current confinement to a desired region of a semiconductor through a selective decrease in conductivity created by selectively pinning the semiconductor's Fermi level at an interface in the region of decreased conductivity. The decrease in conductivity in the region of the interface that undergoes Fermi level pinning is due to a reduction in the number of mobile charge carriers in the surrounding crystal regions. The conductivity change in the disclosed embodiment is created by Fermi level pinning induced at an interface between two III- V semiconductor materials, either of the same or differing material compositions, through selective introduction of impurities or defects to the desired interface. The semiconductor material outside the region of Fermi level pinning can provide high conductivity due to its larger number of mobile charge carriers. The Fermi-level pinning at the interface is therefore used to obtain a lateral conductivity change (in the crystal plane) in the semiconductor material by laterally modifying only the semiconductor heterointerface in a selected region.

[0016] It is among the advantages of the disclosed embodiments that the region of

Fermi level pinning and resulting conductivity change can be defined using lithography, while at the same time other regions of the interface that may be lithographically defined are protected and exhibit high electrical conductivity. In this manner electrical current can be caused to flow only in the desired regions, while the aspect ratio of any patterned materials needed for device definition is kept small. The small aspect ratio of patterning is a key step in device scaling and lateral definition of device size, and allows both small and complex features of electrical current and optical mode confinement to be laterally introduced in a highly controlled manner (i.e. lithographically defined) to create high performance III-V devices.

[0017] It is also among the advantages of the disclosed embodiments that the semiconductor materials at the interface can be chosen to introduce very little material strain, and do not require nonsemiconductor materials such as dielectrics or thick oxides. The absence or minimization of strain internal to the device can then lead to robust devices with high device reliability. [0018] It is also among the advantages of the disclosed embodiments that electrical confinement described in this embodiment can be obtained with a very low aspect ratio of height to define lateral device size. In fact the aspect ratio of the patterning can be made zero, resulting in fully planar devices. A low aspect ratio provides for scaling of the photonic devices to very small dimensions, so as to create photonic devices that operate at low power and yet can exhibit high efficiency. This enables the fabrication of very small photonic crystal, microdisk, or vertical-cavity devices that have efficient current injection into their active regions.

[0019] It is also among the advantages of the disclosed embodiments that intracavity epitaxial phase-shifting mesas that provide optical confinement of the optical modes can be selectively positioned at interfaces also producing high conductivity, so as to obtain electrical current injection into those device regions that also confine the optical mode. In this manner the electrical confinement and the optical confinement can be achieved in a self- aligned manner. In a vertical cavity device the phase-shifting mesa can be used to provide a resonance shift in the vertically confined optical mode, and the vertical resonance shift can also serve to provide lateral optical mode confinement. In a lateral cavity device the phase- shifting mesa provides a change in the vertical resonance in the laterally confined mode, and again the optical mode is laterally confined by the phase-shifting mesa to the same semiconductor region at which current injection occurs.

[0020] In some embodiments the phase-shifting mesa and the region outside the phase-shifting mesa may be placed within one or more additional current confining epitaxial recessed regions of high electrical resistance. The recessed regions lie outside the intracavity phase-shifting layer and serve to additionally confine the electrical current flow and can also be used to identify the position of the phase-shifting mesa layer. This can be useful when the aspect ratio of the phase shifting mesa's height to width is small, or made to be zero. In such a case the device's active region can be clearly distinguished by examining the crystal surface.

[0021] It is also among the advantages of the present embodiments that mode confining region can be portioned into closely spaced phase-shifting mesa layers of same or differing lateral sizes in order to precisely control the transverse modal behavior of the photonic device, and that the current confinement is simultaneously obtained to the same phase-shifting mesas. For example, stable multimode operation can be forced by the phase- shifting mesa layers using various individually mesa sizes in a densely packed array, or single mode may be obtained by carefully choosing the mesa sizes and array pattern. The phase-shifting mesa regions can also be partitioned to form intracavity gratings that further control the lateral profile of the optical mode, while at the same time controlling the optical gain profile through the lateral conductivity changes. In this manner the lateral optical mode control due to the phase-shifting mesa pattern and the lateral optical gain profile may be made to have a preferred overlap to induce single mode operation, despite a relatively large modal area. Or the lateral optical mode and gain profiles may be designed to induce multimode operation. Again the phase shifting mesa aspect ratios can be made to be zero, so that only the current injection is patterned to small feature sizes.

[0022] It is also among the advantages of the present embodiments that the aspect ratio of the phase-shifting mesa regions can be made negative by making the mesa region a recessed region, while retaining electrical current confinement to the recessed region. In this way optical coupling between elements can be enhanced due to antiguiding from regions of current injection where optical gain or light emission exists.

[0023] It is also among the advantages of the disclosed embodiments that additional conducting regions can be introduced in the device. For example high conductivity regions can be formed in the upper mirror of a VCSEL outside the mode confining cavity region to maintain low optical loss in the VCSEL' s optical mode, while simultaneously obtaining low electrical resistance in the device. Therefore, the selective introduction of low conductivity regions formed through the Fermi level pinning at an interface can be used to decoupled to a large degree the current injection path from the optical cavity, by funneling the current into the active region only close to the active region. Diode light sources can then be formed with low loss optical cavities while the diodes also exhibit low electrical resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 shows a schematic cross-section diagram of a an embodiment in which a phase-shifting mesa is formed within a VCSEL cavity with a given material at the surface of the phase-shifting mesa, while the region just outside the phase-shifting mesa has a material at its crystal surface that differs from that of the phase-shifting mesa. The different materials are chosen to obtain a decrease in conductivity through the region outside the phase-shifting mesa due to the different material used at this crystal surface versus that of the phase-shifting mesa.

[0025] Figure 2 shows a schematic cross-section diagram of a second embodiment of a VCSEL, with shallow phase-shifting mesa layers that laterally confine the optical mode and a given material composition at the mesa surface, and a different material composition just outside the phase-shifting mesa region that decreases the conductivity in this region. These phase-shifting mesa layers are formed in a recessed region formed from a larger diameter aperture. The area outside the recessed region is rendered highly resistive to electrical current through either doping changes that create reverse biased p-n junctions, or semi-insulating semiconductor. The semi-insulating semiconductor can be formed by controlling the growth conditions to induce Fermi level pinning defects or through introducing impurities that create deep levels to pin the Fermi level within the energy gap of the semi-insulating semiconductor. In some cases the recessed region outside the phase- shifting mesa layers may also be made conducting to current, while only the area outside the larger diameter aperture is made to block current. This may be desirable, for one example, when the phase-shifting mesa layers are formed in a close packed array to control the lateral optical mode. However, the recessed region may also be made highly resistive to current flow by using properly doped regions to form one or more reverse biased p-n junctions adjacent to the phase-shifting mesa layers, while the phase-shifting mesa layers alone forms the conducting channel.

[0026] Figure 3 shows a schematic cross-section diagram of a third embodiment of a

VCSEL, that again uses shallow phase-shifting mesa layers that laterally confine the optical mode and a given material composition at the mesa surface, and a different material composition just outside the phase-shifting mesa region that decreases the conductivity in this region. In this embodiment the mirror conductivity outside the mesa but within the upper mirrors is increased through the introduction of additional p-type doping. In this manner the optical loss can be kept low in the cavity region, while the electrical resistance of the VCSEL can be decreased through the high conductivity regions formed in the upper mirror. This technique of reducing the electrical resistance can be used with or without additional recessed regions to block the current and identify the location of the phase- shifting mesa regions. [0027] Figure 4 shows current versus voltage characteristics measured for regions that either are (a) in the mesa region in which the surface of the mesa is p-GaAs, or (b) in a region outside the mesa region in which the surface of the crystal is p-Al_o.3Gao.₇As. The current versus voltage curve for region (a) shows an abrupt "turn-on" in the current flow at a voltage of -1.2 V, corresponding to the turn-on voltage of a p-n InGaAs quantum well active region. High conductivity is therefore obtained through the mesa region, with little change to the current versus voltage characteristics obtained from the p-n InGaAs quantum well diode. The current versus voltage curve for region (b) shows that significant current does not flow until the forward voltage is increased to ~4.5 V. The active sizes of the devices used for either (a) or (b) are 30 μm diameter.

[0028] Figure 5 Light vs. current curve for the 7 μm diameter mesa confined

VCSEL of Fig. 6 in which the low conductivity region outside the phase-shifting mesa is formed from an interface between p Alo.₃Gao.-₇As at the surface outside the phase-shifting mesa and p-GaAs, and the high conductivity region through the mesa is formed from the interface between p-GaAs at the surface of the phase-shifting mesa region and p-GaAs.

[0029] Figure 6 shows a schematic cross-section diagram of an embodiment of a lateral cavity device that can serve as a laser diode, superlumiscent diode, optical amplifier diode, or optical switch in which Fermi-level pinning is induced at an interface outside a mode confining mesa. In this embodiment the refractive index of the mesa material is chosen such that the optical mode is confined to the mesa region, and current injection is also confined to the same region. Note that the mesa can be patterned to form a curved or flared cross-section to optically couple multiple active regions into a single waveguide, such as through y-coupled guides or multimode interference guides. In addition a curve can be introduced into the guide with precise control to prevent lasing in a device desired for superlumiscent operation.

[0030] Figure 7 shows various patterns that may be introduced, in which the shaded regions represent regions that from looking down on the surface are regions that exhibit high conductivity, while outside these shaded regions are regions that containing Fermi level pinning at one or more interfaces and exhibit reduced conductivity, (a) shows a pattern that may be used for a lateral cavity laser, in which the shaded regions form both the active current injection path and an index grating to reflect light back and forth along a dimension, (b) shows an elliptical grating that may be used in a VCSEL to control the lateral mode and polarization, (c) shows a photonic lattice pattern that may be used to create a microcavity light emitting diode, or a coupled VCSEL mode. These patterns are presented only to illustrate that embodiments may use a wide array of patterns so as to control the optical mode, while simultaneously obtaining electrical injection into those regions that also confine the optical mode

[0031] Figure 8 shows a schematic illustration of a cross-section in which the active region is formed within a phase-shifting mesa, and covered with epitaxial material. Fermi level pinning is again used outside the mesa region to confine the electrical current.

[0032] Figure 9 shows a schematic illustration of a cross-section in which the active material is part of the overgrowth, again with Fermi level pinning used outside the phase- shifting mesa region to confine the electrical current laterally.

DETAILED DESCRIPTION OF EMBODIMENTS

[0033] The embodiments are described herein with reference to a series of examples that use Fermi level pinning at a semiconductor interface to provide electrical current confinement laterally in the plane of a photonic device. An intracavity shallow epitaxial phase-shifting mesa layer in the semiconductor cavity is used to obtain confinement of the optical mode to the same region by creating a lateral change in the materials refractive index. The conductivity of the phase-shifting mesa layer and its surrounding crystal regions is achieved through doping of shallow impurities that generate mobile charge carriers to obtain a given conductivity type through the phase-shifting mesa layer. Outside this phase-shifting mesa layer Fermi level pinning is selectively created at one or more semiconductor interfaces and used to remove mobile charge carriers from the surrounding semiconductor materials of the interface, and thus decrease the semiconductor conductivity in the regions of Fermi level pinning outside the phase-shifting mesa layers. The barrier creation due to Fermi level pinning can be enhanced by adding a p-n junction such that the p-n junction also requires an applied voltage to enter a regime of high current flow. A forward voltage bias is then partly dropped over the region of Fermi level pinning as well as the p-n junction. The combined voltage required for high current flow can be substantially greater than that of the p-n junction alone.

[0034] The creation of Fermi level pinning is caused by exposing the surface of a semiconductor used to form the interface in the region where the Fermi level pinning is desired to an ambient that introduces a deep level impurities, such as oxygen or another atomic species, to the surface, or by incorporation of native defects at the surface that form deep levels, or the incorporation of both impurities and native defects, while protecting the surface from the ambient in regions where high conductivity is desired, such as with thin semiconductor masking layers. These thin masking layers can themselves be epitaxial semiconductor, to insure that the region in which high conductivity is desired is free of Fermi level pinning. The masking layers can then be preferentially cleaned, for example to form the phase-shifting mesa layer prior to a subsequent overgrowth of conductive epitaxial material. The surface exposed to the ambient to incorporate deep level impurities or native defects, and not cleaned of the impurities or defects, along with the other surfaces that are protected or preferentially cleaned, are then covered with additional epitaxial material to form interfaces within the semiconductor device that either exhibit Fermi level pinning and reduced conductivity, or are relatively free of Fermi level pinning and exhibit by comparison high conductivity.

[0035] The protection of the interface can also be accomplished using thin epitaxial semiconductor materials that are maintained during exposure of the entire crystal surface to the impurity introducing ambient, and then subsequently removing the masking layers prior to a subsequent epitaxial growth over the surfaces to form the desired interfaces. Or the semiconductor material at the surface of the phase-shifting mesa layer (or layers) may be chosen to differ from that of the surface where Fermi level pinning is desired, such that deep level impurities remain in the region where Fermi level pinning is desired at the same time they are cleaned from the surface of the phase-shifting mesa layer. The epitaxial growth over the impurity containing surface that forms interface of reduced conductivity, simultaneous with epitaxial growth over the preferentially cleaned interface, leads to Fermi level pinning outside the region of cleaned interface that exhibits high conductivity and defines the lateral pattern desired for electrical current to flow.

[0036] Because the semiconductor interface or interfaces that undergo Fermi level pinning can be formed close to the active material, and because impurities are localized only to the internal semiconductor interface, the electrical current confinement can be obtained without introducing material strain or impurities or defects into the device's active region. In this manner very high quality active material can be maintained even in the presence of Fermi level pinning at interfaces placed in close proximity to the active material.

[0037] It is also possible to use the disclosed embodiments to obtain epitaxial overgrowth of the active material itself, and thus prevent electrical diffusion of charge carriers laterally from the regions desired for current injection. This is possible by choosing the material interfaces such that the interface that is desired to undergo Fermi level pinning is chosen of a material that retains impurities that produce the Fermi level pinning, while the material interfaces of the active region are chosen of materials that can be cleaned of the impurities. This is especially true, for example, for Al-bearing semiconductors that are exposed to an oxygen containing ambient to oxidize the surface of the Al-bearing material and non- Al-bearing materials. If the active material is formed from non-Al containing materials, and also exposed to the oxygen containing ambient, the non-Al-bearing materials can be cleaned of the oxygen impurities under a procedure in which the Al-bearing materials retain the oxygen impurities. Therefore, while the Al-bearing surfaces undergo Fermi level pinning due to their retention of oxygen impurity, the non-Al-bearing surfaces are effectively cleaned. In this manner depinning of the Fermi-level is obtained upon a subsequent epitaxial growth step, which at the same time retains the Fermi-level pinning in those regions of the exposed Al-bearing materials. In this manner the conductivity may be altered in those crystal regions in which impurities such as oxygen have been introduced to the Al-bearing material, while high conductivity and efficient electrical injection is obtained to those regions of non- Al-bearing materials exposed to the same ambient but effectively cleaned. Oxygen, though demonstrated to be effective in carrying out this process, is not the only impurity that may be used to induce the Fermi level pinning. Atomic nitrogen may also be readily delivered from a plasma source and will readily react with the crystal surface to form compounds that lead to Fermi level pinning. Other deep level impurities may also be used, especially those conveniently delivered to the crystal surface and that react to form stable compounds and deep level states that cause Fermi level pinning.

[0038] It is not necessary to choose different materials between the phase-shifting mesa regions and those desired to create Fermi level pinning on which to receive the subsequent epitaxial growth. A given semiconductor material may have some of its surface exposed to an ambient that introduces an impurity onto the crystal surface that induces Fermi level pinning, while another area of the same semiconductor material is protected by a thin semiconductor layer. The area desired to receive the Fermi level pinning impurity may be exposed by selective etching of the protective material. Once the Fermi level pinning impurity is introduced onto the semiconductor surface layers, the semiconductor can be introduced into the growth chamber and the protective material selectively removed by etching. The selective etching thus forms a semiconductor surface laterally patterned to have the Fermi level pinning impurities localized only to desired regions, but otherwise planar with no crystal steps. Upon a subsequent epitaxial growth onto the crystal surface this lateral pattern can be transferred into laterally defined crystal regions forming those that contain buried interfaces that have the Fermi level pinning impurities and exhibit low conductivity, and those that are free of the impurities and exhibit high conductivity. The epitaxial material deposited on the Fermi level pinned interfaces has been shown to exhibit smooth surface profile and high lateral conductivity.

[0039] In all these cases buried regions are formed within the semiconductor device that form lateral patterns of varying conductivity to laterally confine the injected electrical current into the desired active regions. This lateral patterning of the crystal conductivity can be accomplished with or without phase-shifting mesas that exhibit small crystal steps to simultaneously confine the optical mode to the same region that receives the injected current.

Example 1 [0040] Referring now to Fig. 1, an embodiment is described of a VCSEL diode.

Starting with a III- V semiconductor substrate 90, a lower mirror stack of layers 100 is deposited followed by an active region of layers 110 that include one or more layers of bulk, planar quantum well, quantum wire, or quantum dot material layers 120. On this active region are layers 130 and 150 which form the semiconductor interface regions on which Fermi level pinning is implemented to create low conductivity material to block electrical current flow and layers 130, 140 and 150 to create high conductivity regions that pass the electrically injected current. The Fermi level pinning is introduced selectively at desired interfaces (shown in Fig. 1 as a cross-hatch at the interface between layers 130 and 150 to form low conductivity material in cavity regions 180, while high conductivity is maintained at the interface between layers 140 and 150 to pass current through the cavity region 170. An upper mirror of layers 160 is also formed, with low electrical conductivity to the interface region between layers 140 and 150 in cavity region 170. The layer 150 also forms a phase- shifting intracavity mesa of thickness Dt with the purpose of creating a vertical resonance shift between cavity regions 170 and 180 so as to confine the optical mode in cavity region 170. In practice the thickness Dt is chosen to cause sufficient change in the vertical cavity resonance in cavity region 170 relative to 180 so as to confine the optical mode, while also being sufficiently small so as to limit optical scattering losses and avoid disruption of the epitaxial crystal growth that occurs at the edges of the phase-shifting mesa formed by layer 140. In practice the thickness of Dt can vary depending on the desired mode confinement and the need to obtain low optical loss. Practical values for low optical loss are on the order of 10% of the cavity wavelength in the material of interest. For example, values ranging from 50 A to 300 A have been effectively used for GaAs-based VCSELs operating at 0.98 μm, corresponding to a wavelength of ~0.3 μm in GaAs. Using this technique a VCSEL can be fabricated that includes electrical current confinement to the same device region that confines the optical mode, cavity region 170, and yet is free of material strain and defects that may hinder the device reliability. Electrodes 80 and 185 are formed on the device to facilitate applying a voltage bias to pass current through cavity region 170 and into the active region 110. The electrode placement may vary, and light emission may be taken from the surface as shown in Fig. 1, or an opening made in the electrode 80 for light emission through the substrate. In addition, substrate 90 may be removed in some cases to facilitate integration if required.

[0041] The current blocking ability in cavity region 180 by the Fermi level pinning at the interface between layers 130 and 150 can be enhanced by the choice of doping type and levels in the device. To enhance the current blocking feature at least the upper portion of the lower mirror layers 100 may be doped to yield semiconductor material of a given conductivity type, while layers 130 and 150 are doped to yield semiconductor material of the opposite conductivity type. When Fermi level pinning is induced between layers 130 and 150 a depleted region forms at this interface reducing its conductivity and forming a potential barrier for mobile charge flow across the interface. Upon applying a voltage to the electrodes so as to forward bias the p-n junction across the active region of layers 110 in cavity region 170, part of this voltage in cavity region 180 will be dropped over the interface that undergoes Fermi level pinning. Current will be blocked as long as sufficient barriers are maintained due to both the Fermi level pinning at interface 130 and 150, and the p-n junction at the active region 110. Applying a forward bias to the device, so as to inject charge into the active region 110 through the layers of the cavity region 170 also reduces the barriers to charge flow in cavity region 180 due to depletion of the region at the interface between layers 130 and 150. Upon sufficient forward voltage the barriers due to the Fermi level pinning are reduced due to depletion of doped regions around the interface, and one or both charge carrier types from the doped layers 100 and the layers 150 and 160 allow current flow. Increasing the doping level in layer 130 especially, and inclusion of addition doping in the upper portion of the active region 110, can be effective in inhibiting this depletion and increasing the effectiveness of the current blocking due to reduced conductivity in cavity region 180.

Example 2

[0042] Referring now to Fig. 2 a second embodiment of a VCSEL diode is disclosed.

In Fig. 2 a lower mirror 200 is again formed on a semiconductor substrate containing an active region of layers 210 that contain one or more active layers of bulk, planar quantum well, quantum wire, or quantum dot active material of layers 220, and which include layers 230 and 240. In this embodiment additional layers 260 and 270 may also be included for the purpose of creating a recessed region that clearly delineates from the crystal surface the lateral placement of the phase-shifting mesa layer 240 of thickness Δt in cavity region 190. Upper mirror layers 280 are formed to create at least three distinct cavity regions, region 290 that serves to confine the optical mode and electrically injected current, cavity region 291 that includes the low conductivity region formed due to Fermi level pinning at the interface between layers 230 and 250, and cavity regions 292 that include additional layers of either 260, 270, or both. This embodiment is useful when the thickness Δt of the phase-shifting mesa of layer 140 is made so small that its lateral position as observed looking down on the wafer is difficult to determine. This is also useful for the case that Δt is made to be zero, using the technique described above to create Fermi level pinning only in the cavity region 291 to reduce the conductivity in this region, while the conductivity is maintained high for current injection in cavity region 290. Layers 260 or 170 may be designed to effect current blocking by incorporation of back-biased p-n junctions, or through use of Fermi level pinning, or through incorporation of bulk impurities or native defects.

Measurement of Current Blocking and VCSEL Demonstration

[0043] Referring now to Fig. 3, current versus voltage measurements are presented that demonstrate the conductivity change that can be achieved using the Fermi level pinning technique. In this semiconductor crystal regions of Alo.₃Ga_o.₇As doped with C acceptor atoms at a level of 5x10¹⁸ cm^'3 are exposed to an oxygen ambient to incorporate oxygen impurities at the exposed surface. In other semiconductor crystal regions the Al_o.₃Gao.₇As doped with the C acceptor atoms is protected by a GaAs layer doped with C acceptor atoms at a level of 10¹⁹ cm^"3. The crystal regions exposed are p-type semiconductor, and grown above a light emitting active region of Alo.o₅Gao.95As of thickness 0.28 μm containing three InGaAs planar quantum wells of 60 A thickness with GaAs barriers of 100 A, and a lower n-type heterostructure confining layer doped with Si donor atoms at a level of 5xlO¹⁷ cm^'3. The upper part of the quantum well active region of Alo.o₅Gao.₉₅ As is doped with C acceptor atoms at a level of 5x10 ^u cnv*. After exposure to the oxygen ambient, the oxygen impurity atoms are selectively cleaned from the GaAs crystal surface using thermal desorption of the oxygen and its compounds under conditions that effectively clean the GaAs surface, while oxygen impurities and its compounds are retained on the Al_o.₃Gao.₇As surface. A subsequent epitaxial growth of GaAs doped p-type with C atoms at a level of 10 cm^' is performed on the crystal surface to obtain single crystal p-type GaAs in both crystal regions. Fermi level pinning is therefore obtained at the regrown p-type Al₀.₃Gao.₇As/GaAs interface due to the oxygen impurity atoms selectively placed at the interface formed by the ambient exposed Alo_.3Gao_.7As and the GaAs deposited in the subsequent epitaxial growth.

[0044] Despite the presence of acceptor impurities in the same concentrations in the

Alo_.3Gao.-₇As region under the GaAs phase-shifting mesa, and in the Alo.₃Gao.₇As region under the GaAs regrown interface, depletion of the mobile holes in the regions of the regrown Al₀.₃Gao.₇As/GaAs substantially reduces the conductivity in this region. The Fermi level pinning outside the phase-shifting mesa region therefore forms a potential barrier for hole flow, while the p-n junction of the active material creates a potential barrier for electron flow. Under the same bias conditions that electrical current flow easily passes through the phase- shifting GaAs mesa region, it is effectively blocked in the regions outside the mesa due to the Fermi level pinning.

[0045] Electrodes are formed to both the Fermi level pinned Alo.₃Ga_o.₇As/GaAs interface containing the oxygen impurities, and the protected region in which the oxygen impurities have been cleaned from the GaAs surface. Figure 3 shows that the turn-on voltage in the region the Alo.₃Gao.₇As/GaAs has been protected, labeled "On the Mesa" in Fig. 3, is that expected for a GaAs-based diode and is ~1.2 V. The region undergoing Fermi level pinning at the oxygen exposed interface of the Alo.₃Gao.₇As/GaAs, labeled "Off the Mesa" in Fig. 3, has a turn-on voltage of -4.5 V. Both electrodes contact areas are identical for the measurements and are 30 μm in diameter. The dramatic reduction in conductivity due to Fermi level pinning caused by oxygen impurities at the Alo.₃Gao.₇As/GaAs interface is due to the depletion of mobile charge carriers in the region of this interface, and that sustains a large voltage drop before allowing electrical current to pass.

[0046] Examining the current vs. voltage characteristics of Fig. 3 more closely, we see that when the "On the Mesa" device enters the operating regime at 1.2 V and above and easily passes current, of between 0.5 mA to 9 mA, the "Off the Mesa" device effective blocks current to well below 100 μA. The conductivity change that can be achieved using this technique can therefore readily exceed a factor of 100 in the electrical operating regime important for device operation. In practice, the change in conductivity or current flow that is required for a device will depend on relative sizes, or ratio, of the active area where current flow is desired relative to the surrounding areas where current flow is blocked to obtain efficient device operation. In most embodiments it is highly desirable to confine the current such that 90% or more of the total injected current is confined to the device active area.

[0047] Referring now to Fig. 4, we present the light versus current characteristics of a

VCSEL fabricated using the technique herein disclosed, based on the embodiment of Fig. 2. Figure 4 shows the characteristics of a GaAs-based VCSEL containing an 8 μm diameter phase-shifting mesa to form cavity region 290 of Fig. 2. The region corresponding to 291 of Fig. 2 is due to a 15 μm outer diameter ring, and cavity region 292 consists of a 100 μm diameter mesa. Spectral measurements are made of the light emission characteristics and shown in Fig. 5 to demonstrate that light emission and lasing comes only from cavity region 290. Electrodes are placed on the upper surface of the diode in cavity region corresponding to 292 in Fig. 2. No other dielectric or current confinement layers are used in the device. The threshold current under continuous wave operation is shown to be only 1 mA at room temperature, and the slope efficiency is 25%.

Example 5

[0048] Referring now to Fig. 5, an embodiment is disclosed of a VCSEL mat uses additional doped regions to increase the conductivity through its upper mirror to layers that provide high conductivity to the active area. An advantage of this embodiment is that the doping levels may be kept low in much of the cavity region that confines the optical mode, while the electrical resistance is low through a path outside the optical mode. Beginning with lower mirror layers 300 deposited on a semiconductor substrate, active region layers 310 are formed containing the bulk, planar quantum well, quantum wire, or quantum dot layers 320, and an upper layer 330 and phase-shifting mesa layer 340. Fermi level pinning is selectively formed at the interface between layers 330 and 350 to reduce the conductivity in the cavity regions 380, while forming a high conductivity path in the lower layers of the upper mirror 360 and layer 350. An implantation or diffusion of dopant impurities is then performed to increase the conductivity of the upper mirror selectively in regions 390, and form a high conductivity connection to the phase-shifting mesa layer 340. Using this embodiment much of the upper mirror layers 360 in cavity region 370 can remain free of doping to obtain low optical loss, while high electrical conductivity can still be achieved in the VCSEL.

Example 6

[0049] Referring now to Fig. 6, an embodiment of a lateral cavity photonic device is presented in which the optical mode is confined due to a lateral index change between the phase-shifting mesa and its surrounding material, while electrical current injection is again confined to the same region as the optical mode. The lateral cavity device includes a lower semiconductor cladding layer 400, and active region 410 containing one more layers 420 of bulk, planar quantum well, quantum wire, or quantum dot active material, and upper layer 430 on which is formed a phase-shifting mesa layer 440. In this lateral cavity device the phase-shifting mesa layer shifts the vertical resonance of an optical mode confined to propagate laterally in the active region 410. Fermi level pinning is selectively created at the interface between layers 430 and 450 to reduce the conductivity in cavity region 470, while maintaining high conductivity at the interface between layers 440 and 450. The thickness Δt of the phase-shifting mesa layer 440 can be chosen to optically confine one or more lasing modes in the cavity region 460 through the lateral change in refractive index obtained between layers 440 and 450, while electrical current is also restricted to the same cavity region 460 by the high conductivity electrical path between layers 450 and 440.

[0050] In each of the embodiments above the device may also be a spontaneous light emitter, or a device that operates in the superluminescent regime, or an optical amplifier, or an optical switch. For example, the lateral cavity device of Example 6 also serves to define an optical waveguide that may route the light from one optical element to another in an integrated photonic chip. In addition, the lateral cavity device may be augmented with vertical cavity confinement, so as to obtain a propagating wavevector that propagates with slow velocity in the plane of the crystal and thus exhibits reduced optical loss. In addition, the lateral cavity device combined with vertical cavity confinement may exhibit a wavevector that lies mainly in the vertical direction, so as to obtain high reflectivity due to a cleaved facet or etched mirror due to its angle of incidence on the mirror. In addition, additional lateral photonic confinement, such as due to a photonic crystal or microdisk, may be employed with these embodiments so as to restrict the current flow into a small active area, while maintaining low optical loss, low mechanical strain, and high electrical conductivity into the device active region, with the current confined due to the formation of Fermi level pinning at selected interfaces internal to the semiconductor device.

Example 7

[0051] Referring now to Fig. 7, it is understood that various patterns of high conductivity and low conductivity may be incorporated laterally in the device, along with phase-shifting mesas if desired, so as to further control the optical mode and preferentially inject current into these patterns. For example, a distributed feedback or laser with a distributed Bragg reflector may be fabricated in which electrical current is injected into regions preferentially that also provide feedback into the cavity. Figure 7 (a) illustrates the pattern for such a device looking down at the device surface, with the shaded regions being those in which high conductivity and possibly phase-shifting mesas are formed while the unshaded regions are those that have undergone Fermi level pinning and thus exhibit reduced conductivity. Figure 7 (b) illustrates an elliptical grating that may be desirable for a VCSEL. Figure 7 (c) illustrates a densely packed 2-dimensional grating that may be useful to introduce gaps to prevent propagation of selected optical modes, or be used to fabricate a high efficiency light emitting diode. The patterns in Fig. 7 are not intended to represent all the patterns that may be desired, but only examples that show how the embodiments may be employed in further controlling the optical mode and current injection into the modes.

Example 8

[0052] Referring now to Fig. 8, it is understood that it is not necessary to form the

Fermi level pinning above the active region, but the Fermi level pinning may also be induced at interfaces below the active region. Figure 8 shows that beginning on layer 500 a layer 510 may be formed followed by layers 520, 530, and 540. Layers 520, 530, and 540 are used to form the active region of the device. Following selective removal of these layers in the desired regions, Fermi level pinning is induced on the surface of layer 510 and a subsequent epitaxial growth of layers 550 and 560 is used to selectively create the Fermi level pinning at the interface between layers 510 and 550 in the cavity region 580. Layer 550 may provide additional heterojunction confinement to the active region, while layer 560 provides additional waveguide confinement in the cavity region 570.

[0053] To enhance the current blocking function of the Fermi level pinning at the interface between layers 510 and 520, doping may be incorporated along with heterojunctions such that layer 500 exhibits one conductivity type, while layers 510, 550, and 560 exhibit the opposite conductivity type. Fermi level pinning at the interface between layers 510 and 550 therefore deplete the interface and surround crystal regions of mobile charge carriers, while a p-n junction at the interface 500 and 510 provide additional current blocking as described above. In such a device, mobile charge carriers of the conductivity type of layer 500 are injected, upon forward bias, injected into layer 510 in cavity region 570 and are transported and captured in the active region formed by layers 520, 530, and 540 to create the devices optical response.

Example 9 [0054] Referring now to the embodiment in Fig. 9, it is understood that the active region or part of the active region may be formed in a subsequent growth following the creation of Fermi level pinning in the selected device regions. Figure 9 shows that beginning on semiconductor layer 600, the adjacent layer 610 and 620 are also formed. Layer 620 is patterned to expose layer 610 for inducement of Fermi level pinning. Following this, the cavity region 670 which in this case includes layer 620 is selectively cleaned and a subsequent epitaxial growth is used to form layers 630, 640, 650, and 660. Fermi level pinning is created selectively at the interface of layers 610 and 630 in cavity region 680, while layers 630, 640, and 650 form the device active region. Doping can be carried out as in the description of Example 8 to enhance the current blocking in cavity regions 680.

[0055] The disclosed embodiments can also be applied to optoelectronic devices such as VCSELs, lateral cavity laser diodes, vertical/lateral cavity laser diodes, optical amplifiers, microcavity light emitting diodes, superluminescent diodes, or optical switches, that use single or multiple air-semiconductor interfaces to confine the optical mode. These types of optoelectronic devices can be susceptible to internal device strain when they use thin films, or because of the proximity of their active materials to the air-semiconductor interface. The disclosed embodiments are therefore applicable to photonic crystal lasers, VCSELs based on air-semiconductor Bragg reflectors, and microcavity light emitting diodes. In such embodiments it can be an advantage for heat dissipation to employ metal electrodes formed within etched vias so as to make electrical contact close to the active material while at the same time providing a high thermal conductivity path through which to dissipate excess heat generated by the device. This type of fabrication can be facilitated by employing the current confinement technique based on Fermi level interface pinning to eliminate or reduce internal device strain while at the same time providing high efficiency current injection into the device active region.

Claims

WHAT IS CLAIMED IS:

1. A semiconductor device comprising: a first region having a semiconductor interface between a first semiconductor and a second semiconductor, the first semiconductor characterized by Fermi level pinning within an energy gap of the first semiconductor, and further characterized by a first conductivity level proximate the interface that substantially blocks electrical current flow through the semiconductor interface; and a second region, laterally adjoining the first region, including a third semiconductor characterized by a second conductivity level higher than the first conductivity level, such that the second region is capable of passing electrical current.

2. The semiconductor device of claim 1, wherein the device is a vertical-cavity surface- emitting laser.

3. The semiconductor device of claim 1, wherein the device is a lateral cavity semiconductor laser.

4. The semiconductor device of claim 1, wherein the device is a spontaneous light source.

5. The semiconductor device of claim 1 , wherein the device is a photodetector.

6. The semiconductor device of claim 1, wherein the device is monolithically integrated with one or more additional semiconductor devices.

7. The semiconductor device of claim 1, wherein the Fermi-level pinning is induced by selective introduction of impurities into a region of the interface.

8. The semiconductor device of claim 1, wherein the Fermi-level pinning is induced by selective introduction of native defects into a region of the interface.

9. The semiconductor device of claim 1, wherein the first and second semiconductors are III- V semiconductors.

10. The semiconductor device of claim 1, further comprising: an epitaxial phase-shifting mesa selectively positioned proximate to the interface to provide optical confinement.

11. The semiconductor device of claim 10, wherein the phase-shifting mesa is disposed within a current confining epitaxial recessed region having substantially high electrical resistance.

12. The semiconductor device of claim 11, wherein the recessed region is disposed outside a phase-shifting mesa layer and confines electrical current flow.

13. The semiconductor device of claim 1 , further comprising: a mode confining region portioned into phase-shifting mesa layers having sizes selected to control a transverse modal behavior of the device.

14. The semiconductor device of claim 1 , further comprising: phase-shifting mesa regions positioned proximate to the interface and partitioned to form gratings for controlling a lateral profile of an optical mode of the device while controlling an optical gain profile through lateral conductivity changes.

15. The semiconductor device of claim 1, wherein the phase-shifting mesa regions are recessed and adapted to confine electrical current.