WO2006036334A3 - Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication - Google Patents

Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication Download PDF

Info

Publication number
WO2006036334A3
WO2006036334A3 PCT/US2005/028828 US2005028828W WO2006036334A3 WO 2006036334 A3 WO2006036334 A3 WO 2006036334A3 US 2005028828 W US2005028828 W US 2005028828W WO 2006036334 A3 WO2006036334 A3 WO 2006036334A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
layer
memory cell
layers
programming
Prior art date
Application number
PCT/US2005/028828
Other languages
English (en)
Other versions
WO2006036334A2 (fr
Inventor
Gowrishankar L Chindalore
Craig T Swift
Original Assignee
Freescale Semiconductor Inc
Gowrishankar L Chindalore
Craig T Swift
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Gowrishankar L Chindalore, Craig T Swift filed Critical Freescale Semiconductor Inc
Priority to EP05790366A priority Critical patent/EP1792336A2/fr
Priority to JP2007532334A priority patent/JP5103182B2/ja
Priority to CN200580031541XA priority patent/CN101432858B/zh
Publication of WO2006036334A2 publication Critical patent/WO2006036334A2/fr
Publication of WO2006036334A3 publication Critical patent/WO2006036334A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Cette invention concerne une cellule de mémoire à porte flottante (10) dont la porte flottante comporte deux couches de porte flottante (18, 22). La couche supérieure (22) est gravée selon un contour qui laisse intacte la couche inférieure (18). La porte de commande (38) épouse le contour de la porte flottante (22), ce qui augmente la capacitance entre ces deux portes. Les deux couches (18, 22) de la porte flottante peuvent être séparées par une couche d'arrêt gravée très mince en polysilicium (20). Cette couche d'arrêt gravée (20) est suffisamment épaisse pour arrêter la gravure du polysilicium, tout en étant de préférence assez mince pour être transparente électriquement. Les électrons peuvent se déplacer librement entre les deux couches (22, 18). Ainsi, la gravure de la couche supérieure (22) ne pénètre pas dans la couche inférieure (18), mais les première (18) et seconde (22) couches agissent, pour une porte flottante, comme une couche conductrice continue.
PCT/US2005/028828 2004-09-17 2005-08-15 Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication WO2006036334A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP05790366A EP1792336A2 (fr) 2004-09-17 2005-08-15 Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication
JP2007532334A JP5103182B2 (ja) 2004-09-17 2005-08-15 フローティングゲート素子を形成する方法
CN200580031541XA CN101432858B (zh) 2004-09-17 2005-08-15 用于浮置栅极存储单元的编程和擦除结构以及制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/944,244 2004-09-17
US10/944,244 US7183161B2 (en) 2004-09-17 2004-09-17 Programming and erasing structure for a floating gate memory cell and method of making

Publications (2)

Publication Number Publication Date
WO2006036334A2 WO2006036334A2 (fr) 2006-04-06
WO2006036334A3 true WO2006036334A3 (fr) 2009-04-02

Family

ID=36074588

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/028828 WO2006036334A2 (fr) 2004-09-17 2005-08-15 Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication

Country Status (7)

Country Link
US (2) US7183161B2 (fr)
EP (1) EP1792336A2 (fr)
JP (1) JP5103182B2 (fr)
KR (1) KR20070048247A (fr)
CN (1) CN101432858B (fr)
TW (1) TWI412085B (fr)
WO (1) WO2006036334A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4377676B2 (ja) * 2003-12-24 2009-12-02 株式会社東芝 半導体装置およびその製造方法
US7615445B2 (en) * 2006-09-21 2009-11-10 Sandisk Corporation Methods of reducing coupling between floating gates in nonvolatile memory
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
CN102282651A (zh) * 2009-01-29 2011-12-14 国际商业机器公司 具有非平面浮动栅极的存储器晶体管及其制造方法
US8415217B2 (en) * 2011-03-31 2013-04-09 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288256A (en) * 1977-12-23 1981-09-08 International Business Machines Corporation Method of making FET containing stacked gates
US6323088B1 (en) * 1998-04-08 2001-11-27 Micron Technology, Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication an operation
US6495467B2 (en) * 2001-02-19 2002-12-17 Samsung Electronics Co., Ltd. Method of fabricating a non-volatile memory device
US20030057473A1 (en) * 1999-04-27 2003-03-27 Eiji Kamiya Nonvolatile semiconductor memory device
US6713834B2 (en) * 2000-10-30 2004-03-30 Kabushiki Kaisha Toshiba Semiconductor device having two-layered charge storage electrode

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0232539A (ja) * 1988-07-22 1990-02-02 Hitachi Ltd 半導体装置の製造方法及びエッチング方法
JP2908163B2 (ja) * 1993-02-25 1999-06-21 株式会社東芝 半導体装置の製造方法
US5413949A (en) * 1994-04-26 1995-05-09 United Microelectronics Corporation Method of making self-aligned MOSFET
JP2590746B2 (ja) * 1994-07-29 1997-03-12 日本電気株式会社 半導体装置の製造方法
KR0161399B1 (ko) * 1995-03-13 1998-12-01 김광호 불휘발성 메모리장치 및 그 제조방법
JPH09148460A (ja) * 1995-11-28 1997-06-06 Sony Corp 不揮発性半導体記憶装置及びその製造方法
KR0179163B1 (ko) * 1995-12-26 1999-03-20 문정환 비휘발성 메모리 셀 및 그 제조방법
KR100192551B1 (ko) * 1996-05-16 1999-06-15 구본준 반도체 메모리 소자 및 그의 제조방법
US6495487B1 (en) * 1996-12-09 2002-12-17 Uop Llc Selective bifunctional multimetallic reforming catalyst
JP3598197B2 (ja) * 1997-03-19 2004-12-08 株式会社ルネサステクノロジ 半導体装置
US6342715B1 (en) * 1997-06-27 2002-01-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
KR100318683B1 (ko) * 1998-12-17 2001-12-28 윤종용 산화막/질화막/산화막 유전층의 형성방법
TW490860B (en) * 1998-12-24 2002-06-11 United Microelectronics Corp Manufacturing of flash memory cell
US6323514B1 (en) * 1999-07-06 2001-11-27 Micron Technology, Inc. Container structure for floating gate memory device and method for forming same
JP4443008B2 (ja) * 2000-06-30 2010-03-31 富士通株式会社 半導体装置及びその製造方法
TW463248B (en) * 2000-09-26 2001-11-11 Macronix Int Co Ltd Method for forming gates
JP2002176114A (ja) * 2000-09-26 2002-06-21 Toshiba Corp 半導体装置及びその製造方法
US6627942B2 (en) 2001-03-29 2003-09-30 Silicon Storage Technology, Inc Self-aligned floating gate poly for a flash E2PROM cell
US6791142B2 (en) 2001-04-30 2004-09-14 Vanguard International Semiconductor Co. Stacked-gate flash memory and the method of making the same
US6391722B1 (en) 2001-07-13 2002-05-21 Vanguard International Semiconductor Corporation Method of making nonvolatile memory having high capacitive coupling ratio
US6537880B1 (en) 2001-09-13 2003-03-25 Vanguard International Semiconductor Corporation Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch isolation and large capacitance between control and floating gates
DE10146215A1 (de) * 2001-09-19 2003-04-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeicherelement-Anordnung, Verfahren zum Betreiben einer Halbleiterspeicherelement-Anordnung und Halbleiterspeicherelement-Anordnung
KR100426485B1 (ko) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 셀의 제조 방법
US6780712B2 (en) 2002-10-30 2004-08-24 Taiwan Semiconductor Manufacturing Company Method for fabricating a flash memory device having finger-like floating gates structure
US6716705B1 (en) 2002-06-03 2004-04-06 Lattice Semiconductor Corporation EEPROM device having a retrograde program junction region and process for fabricating the device
EP1376676A3 (fr) 2002-06-24 2008-08-20 Interuniversitair Microelektronica Centrum Vzw Dispositif de mémoire rémanente multibit et procédé
US6908817B2 (en) * 2002-10-09 2005-06-21 Sandisk Corporation Flash memory array with increased coupling between floating and control gates
KR100454135B1 (ko) * 2002-10-10 2004-10-26 삼성전자주식회사 비휘발성 기억소자의 형성방법
KR100482765B1 (ko) * 2002-12-12 2005-04-14 주식회사 하이닉스반도체 플래쉬 메모리 소자의 플로팅 게이트 형성 방법
US6897116B2 (en) * 2003-09-12 2005-05-24 United Microelectronics Corp. Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device
US6943118B2 (en) * 2003-09-18 2005-09-13 Macronix International Co., Ltd. Method of fabricating flash memory
US7557042B2 (en) 2004-06-28 2009-07-07 Freescale Semiconductor, Inc. Method for making a semiconductor device with reduced spacing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288256A (en) * 1977-12-23 1981-09-08 International Business Machines Corporation Method of making FET containing stacked gates
US6323088B1 (en) * 1998-04-08 2001-11-27 Micron Technology, Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication an operation
US20030057473A1 (en) * 1999-04-27 2003-03-27 Eiji Kamiya Nonvolatile semiconductor memory device
US6713834B2 (en) * 2000-10-30 2004-03-30 Kabushiki Kaisha Toshiba Semiconductor device having two-layered charge storage electrode
US6495467B2 (en) * 2001-02-19 2002-12-17 Samsung Electronics Co., Ltd. Method of fabricating a non-volatile memory device

Also Published As

Publication number Publication date
US7745870B2 (en) 2010-06-29
US20070117319A1 (en) 2007-05-24
CN101432858A (zh) 2009-05-13
TWI412085B (zh) 2013-10-11
CN101432858B (zh) 2012-06-27
JP2008513999A (ja) 2008-05-01
KR20070048247A (ko) 2007-05-08
US20060063328A1 (en) 2006-03-23
TW200623275A (en) 2006-07-01
WO2006036334A2 (fr) 2006-04-06
JP5103182B2 (ja) 2012-12-19
US7183161B2 (en) 2007-02-27
EP1792336A2 (fr) 2007-06-06

Similar Documents

Publication Publication Date Title
JP2007300098A5 (fr)
WO2008076152A3 (fr) Grille flottante à échelle nanométrique et procédés de formation
TWI264826B (en) Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method
TW200629574A (en) Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
TW200701236A (en) Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US9379255B2 (en) Non-volatile memory cell having a floating gate and a coupling gate with improved coupling ratio therebetween
WO2005048299A3 (fr) Transistor a trois electrodes isolees electroniquement, et son procede de formation
EP1860686A3 (fr) Dispositif de mémoire semiconducteur possédant une électrode à porte de commande dans une cavité et procédé de fabrication du dispositif de mémoire semiconducteur
JP2003234422A5 (fr)
JP2002141469A5 (fr)
TW200735378A (en) Split gate memory cell and method for fabricating the same
CN104091803A (zh) 分离栅极式存储器、半导体器件及其制作方法
WO2006036334A3 (fr) Structure de programmation et d'effacement pour une memoire a porte flottante, et procede de fabrication
TW200518268A (en) Improved method for manufacturing a 2-transistor memory cell, and improved memory cell thus obtained
CN107342288A (zh) 分裂栅型双位非易失性存储器单元
TW200644178A (en) Flash memory and manufacturing method thereof
EP1020902A3 (fr) Procédé de fabrication d'une cellule mémoire à grille divisée
CN108735751B (zh) 一种浮栅存储单元及其制备方法
EP1498945A3 (fr) Cellule de mémoire FLASH à basse consommation et son procédé
CN105514045B (zh) 闪存存储器栅极结构及其制作方法
TW200739909A (en) Semiconductor device and manufacturing method thereof
CN103839950B (zh) Tft‑lcd阵列基板及其制造方法
TW200419786A (en) Flash memory cell and fabrication thereof
TW351852B (en) Process for manufacturing flash memory cell structure
WO2003100841A3 (fr) Procede pour produire une cellule de memoire, cellule de memoire et ensemble de cellules de memoire

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005790366

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007532334

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020077006135

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 200580031541.X

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 2005790366

Country of ref document: EP